具有数字信号处理器 (dsp) 和2.1 模式的 2 x 20w 数字音频 · pdf filetas5731...

TAS5731
www.ti.com.cn ZHCS602A DECEMBER 2011REVISED SEPTEMBER 2013
(DSP) 2.1 2 x 20W : TAS5731
1
2 I2S 8kHz 48kHz fS (LCD) 20W 8 / 18V (THD) + N = (LED)
10% 90%
8V 21V 3.3V TAS5731 20W
2.12 (SE) + 1 (BTL)
2 SE 4 BTL 70m RDS(on) MPEG
12V / 2 / 8W SE 12V / 4 / 15W BTL
TAS5731 (EQ) 8BQ2 x TAS5731 (DRC)384kHz 352KHz TAS5727 (P2P) (PWM) 20Hz 20kHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 20112013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not English Data Sheet: SLOS726necessarily include testing of all parameters.
http://www.ti.com.cn/product/cn/tas5731?qgpn=tas5731http://www.ti.com.cnhttp://www.ti.com.cn/product/cn/tas5731#sampleshttp://www-s.ti.com/sc/techlit/SLOS726.pdf

RESET
PDN
SDA
PLL_FLTM
PLL_FLTP
AVDD/DVDD PVDD
3.3 V 8 V21 V
SCL
DigitalAudio
Source
I CControl
2
ControlInputs
B0264-25
LoopFilter
SDIN
LRCLK
SCLK
MCLK
OUT_A
OUT_B
BST_A
BST_B
LCSE
LCSE
PVDD
PVDD
OUT_C
OUT_D
BST_C
BST_D
LCBTL
TAS5731
ZHCS602A DECEMBER 2011REVISED SEPTEMBER 2013 www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED 2.1 APPLICATION DIAGRAM
2 Copyright 20112013, Texas Instruments Incorporated
http://www.ti.com.cn/product/cn/tas5731?qgpn=tas5731http://www.ti.com.cn

MCLK
SCLK
LRCLK
ProtectionLogic
Click and PopControl
Digital Audio Processor(DAP)
SDA
SCL
4 -Orderth
Noise Shaperand PWM
SRC
Sample RateAutodetectand PLL
SerialControl
MicrocontrollerBasedSystemControl
Terminal Control
OUT_A
OUT_B
2 HBFET Out
OUT_C
OUT_D
2 HBFET Out
B0262-14
SDINSerialAudioPort
TAS5731
FUNCTIONAL VIEW
Copyright 20112013, Texas Instruments Incorporated 3

Temp.Sense
VALID
FAULT
AGND
PowerOn
Reset
Under-voltage
Protection
GND
PWM_DOUT_D
PGND_CD
PVDD_CD
BST_D
GateDrive
PWMRcv
OvercurrentProtection
4
Protectionand
I/O Logic
PWM_COUT_C
PGND_CD
PVDD_CD
BST_C
TimingGateDrive
CtrlPWMRcv
GVDD_OUT
PWM_BOUT_B
PGND_AB
PVDD_AB
BST_B
TimingGateDrive
CtrlPWMRcv
PWM_AOUT_A
PGND_AB
PVDD_AB
BST_A
TimingGateDrive
CtrlPWMRcv
Ctrl
Pulldown Resistor
Pulldown Resistor
Pulldown Resistor
Pulldown Resistor
4
GVDDRegulator
GVDDRegulator
Timing
Isense
B0034-08
PW
M C
ontr
olle
r
TAS5731
Figure 1. Power-Stage Functional Block Diagram

+
L R
+ +
+ +
+
Vol1
Vol2e
alp
ha
1B
Q
1B
Q
1B
Q
1B
Q
6B
Q
6B
Q
1B
Q
1B
Q
1B
Q
Input Muxing
Log
Math
Attack
Decay
1
Maste
r O
N/O
FF
(0x46[0
])
EnergyMAXMUX
ealp
ha
B0
32
1-1
4
1 1
1 1
1 151 V
1O
M
52 V
2O
M
I2C:57VDISTB
I2C:56VDISTA
60 V
6O
M
55
2A
I2C
:53
V
1IM
31
2B
2F, 58
32
36, 5C
59
IC
Subaddre
ss in R
ed
2
5D
5E
29
30
I2C
:54
V
2IM
L R1B
Q1B
Q
Vol1
5A
5B
21 (
D8, D
9)
61
+
+ +
1 0
Auto
-lp
(0x46 B
it 5
)
Log
Math
Attack
Decay
1
Maste
r O
N/O
FF
(0x46[1
])
EnergyMAXMUX
ealp
ha
ealp
ha
ealp
ha
Vol2
+ +
3D
3D
3A
3A
1 0 3
TAS5731
DAP Process Structure
Copyright 20112013, Texas Instruments Incorporated 5

SSTIMER
NC
PLL_FLTP
VR_ANA
PBTL
AVSS
PLL_FLTM
BST_A
NC
PVDD_AB
OUT_A
RESET
PVDD_AB
STEST
PD
N
VR
_D
IG
OS
C_R
ES
DV
SS
O
DVDD
MC
LK
AD
R/F
ALU
LT
SC
LK
SD
IN
LR
CLK
AV
DD
SD
A
SC
L
DVSS
GND
VREG
BS
T_B
NC
NC
OU
T_C
PVDD_CD
BST_D
PG
ND
_A
B
OU
T_B
PG
ND
_C
D
OUT_D
AGND
PG
ND
_A
B
NC
PG
ND
_C
D
PVDD_CD
BS
T_C
NC
GVDD_OUT
P0075-25
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
TAS5731
DEVICE INFORMATION
PHP Package(Top View)
PIN FUNCTIONSPIN 5-VTYPE (1) TERMINATION (2) DESCRIPTIONTOLERANTNAME NO.
AGND 30 P Local analog ground for power stage, which should be connected tothe system ground.
ADR/FAULT 14 DIO Dual function terminal which sets the LSB of the 7-bit I2C address to"0" if pulled to GND and to "1" if pulled to DVDD. If configured to bea fault output by the methods described in IC Address Selection andFault Output, this terminal is pulled low when an internal fault occurs.A pull-up or pull-down resistor is required, as is shown in the TypicalApplication Circuit Diagrams. If pulled high (to DVDD), a 15kresistor should be used to minimize in-rush current at power up andto isolate the net if the pin is used as a fault output, as describedabove.
AVDD 13 P 3.3-V analog power supplyAVSS 9 P Analog 3.3-V supply groundBST_A 4 P High-side bootstrap supply for half-bridge ABST_B 43 P High-side bootstrap supply for half-bridge B
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output(2) All pullups are 20-A weak pullups and all pulldowns are 20-A weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pull-ups logic 1 input; pulldowns logic 0 input). Devices that driveinputs with pullups must be able to sink 20 A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must beable to source 20 A while maintaining a logic-1 drive level.

TAS5731
PIN FUNCTIONS (continued)PIN 5-VTYPE (1) TERMINATION (2) DESCRIPTIONTOLERANTNAME NO.
BST_C 42 P High-side bootstrap supply for half-bridge CBST_D 33 P High-side bootstrap supply for half-bridge DDVDD 27 P 3.3-V digital power supplyDVSS 28 P Digital groundDVSSO 17 P Oscillator groundGND 29 P Analog ground for power stageGVDD_OUT 32 P Gate drive internal regulator outputLRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample-rate clock)MCLK 15 DI 5-V Pulldown Master clock inputNC 5, 7, No connect
40,41,
44, 45OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-k, 1% resistor to DVSSO.OUT_A 1 O Output, half-bridge AOUT_B 46 O Output, half-bridge BOUT_C 39 O Output, half-bridge COUT_D 36 O Output, half-bridge DPBTL 8 DI Pulldown Low means BTL mode; high means PBTL mode. Information goes
directly to power stage.PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWMstop sequence.
PGND_AB 47, 48 P Power ground for half-bridges A and BPGND_CD 37, 38 P Power ground for half-bridges C and DPLL_FLTM 10 AO PLL negative loop-filter terminalPLL_FLTP 11 AO PLL positive loop-filter terminalPVDD_AB 2, 3 P Power-supply input for half-bridge output A and BPVDD_CD 34, 35 P Power-supply input for half-bridge output C and DRESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic
low to this pin. RESET is an asynchronous control signal thatrestores the DAP to its default c

具有数字信号处理器 (dsp) 和2.1 模式的 2 x 20w 数字音频 · pdf filetas5731...

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