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Zynq intr – part 2

Description of the interrupt between PL to PS in Vivado 2014.x

Content

Concat block in 2014.x

The concat block maintains the interrupts order.

Page 4: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

PS interrupt setup in 2014.x

The note attached to the interrupt setup tick box is misleading:

It gives an incorrect idea of what is happening

See on the next slide for what is actually happening

Page 5: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

Two auto-generated source files are now of interest:– Dev_processing_system7_0_0.v is a wrapper for – Processing_system7_v5_4_processing_system7.v

PS7 source files

Page 6: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

This is a new parameter introduced in 2014.x.

It is assigned a value in Dev_processing_system7_0_0.v and passed to Processing_system7_v5_4_processing_system7.v

The parameter value passed is “DIRECT”.

C_IRQ_F2P_MODE

Page 7: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

Generated PS source file in 2014.x The “DIRECT” parameter is now used in mapping the interrupt vector IRQ_F2P to the internal interrupt vector irq_f2p_i

Page 8: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

An illustration of the interrupt mapping for IRQ_F2P_MODE = DIRECT

Page 9: © Copyright 2014 Xilinx. Zynq intr – part 2. © Copyright 2014 Xilinx. Description of the interrupt between PL to PS in Vivado 2014.x Content

Summary of interrupt mapping strategy in 2014.x in DIRECT mode.

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