a - sscc 2021

November 7 (Sun) - 10 (Wed), 2021Lotte Hotel Busan, Korea (Hybrid Conference)

Advanced program

IEEE Asian Solid - State Circuits ConferenceA - SSCC 2021

www.a-sscc2021.org

A-SSCC 2021 2 November 7 (Sun) - 10 (Wed), 2021

TutorialsSunday, November 7


Tutorial Crystal Ballroom 3

Tutorial 1 09:00-10:30Incremental Delta-Sigma ADCs: Past, Present, and Future

Youngcheol ChaeYonsei University, Seoul, Korea

BiographyYoungcheol Chae received the B.S., M.S., and Ph.D. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea in 2003, 2005 and 2009, respectively. He was with Delft University of Technology, Delft, The Netherlands from 2009 to 2011. Dr. Chae joined the Yonsei University in 2012 and is currently an Associate Professor. His work has focused on data converters and sensor interfaces. This results in 100+ journal and conference papers and 30+ patents. He is a member of the TPCs of International Solid-State Circuits Conference (ISSCC) and Asian Solid-State Circuits Conference (A-SSCC). He has served as a Guest Editor of the Journal of Solid-State Circuits and a Distinguished Lecturer of IEEE Solid-State Circuits Society. He received the Best Young Professor Award in Engineering from Yonsei University in 2018, the Haedong Young Engineer Award from IEIE in 2017, and the Outstanding Research Award of Yonsei University (2017, 2019, 2020).

Abstract In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This tutorial explores the fundamentals of IADCs, discusses the advantages of different hybrid architectures, and explains how to improve the energy-efficiency with various design techniques.

Tutorial 2 10:50-12:20Mm-Wave PA Designs – Fundamentals, Architectures, and The State of the Art

Hua WangETH Zürich

BiographyHua Wang received his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena in 2007 and 2009. He was with Intel and Skyworks Solutions from 2010 to 2011. From 2012 to 2021, he was an associate professor with tenure at the Georgia Institute of Technology and the founding GT Center of Circuits and Systems (CCS). Dr. Wang joined the Swiss Federal Institute of Technology in Zürich (ETH Zürich) in 2021 as a full professor and Chair of the Electronics.Dr. Wang is interested in innovative analog, mixed-signal, RF, and mm-wave integrated circuits and hybrid systems for communication, sensing, and bioelectronics applications. He has authored or co-authored over 190 peer-reviewed journal and conference papers.Dr. Wang received the DARPA Director’s Fellowship Award in 2020, the DARPA Young Faculty Award in 2018, the NSF CAREER Award in 2015, the Qualcomm Faculty Award in 2020 and 2021, and the IEEE MTT-S Outstanding Young Engineer Award in 2017.

Abstract This tutorial presents a focused overview of mm-wave power-amplifier (PA) designs in silicon, including design fundamentals, advanced PA architectures, and the start-of-the-art design examples.




The tutorial will start with an introduction of PA performance metrics and their impacts on wireless systems. Next, it presents the design fundamentals of PA active devices and passive networks as well as power combining strategies. The tutorial discusses advanced PA architectures, including Doherty, Outphasing, and Hybrid PAs, for high efficiency, linearity, and bandwidth. Antenna-PA co-designs are covered as well to achieve on-antenna power combining, active load modulation, and reconfiguration. Further, advance and challenges of high mm-Wave PAs will be covered to address the emerging beyond-5G/6G applications. Finally, the tutorial studies several state-of-the-art mm-wave PA design examples.

Tutorial 3 14:00-15:30Always-On Systems for Next-Gen IoT – From Less Battery to Battery-Less

Massimo AliotoNational University of Singapore

Biography Massimo Alioto is a Professor at the National University of Singapore, where he leads the Green IC group, the Integrated Circuits Embedded Systems area, and the FD-fAbrICS research center. Previously, he held visiting positions at the University of California Berkeley (BWRC), University of Michigan Ann Arbor, University of Siena, Intel Labs, EPFL.He is author of >300 publications and four books, focusing on ultra-low power integrated system design, machine intelligence, and hardware security, among the others.Currently, he is the Editor-in-Chief of IEEE Transactions on VLSI Systems, Distinguished Lecturer of the IEEE Solid-State Circuits Society, and sub-committee member of ISSCC and ASSCC. Prof. Alioto is an IEEE Fellow.

Abstract Scaling up the IoT requires its edge to be more autonomous in terms of both energy and intelligence. Edge devices are expected to be mostly- or always-on to avoid missing physical events, in spite of highly-uncertain miniaturized energy sources.This tutorial introduces the fundamental principles and state-of-the-art circuits to build systems for always-on sensing and monitoring, where intelligence and adaptation are deeply embedded along the entire signal chain, as well as the energy chain. Techniques for ultra-wide power-performance adaptation are presented to keep power within a tight budget in the common case, while occasionally enabling deep event analysis (e.g., via AI). The main sub-systems of IoT sensor nodes are covered, ranging from sensor interfaces to processing/edge intelligence, power management and wireless communications.At the end of the tutorial, attendees will gain an insight into architectures and circuit techniques for always-on pervasive integrated systems with very limited energy availability.

Tutorial 4 15:50-17:20Fundamentals of NAND Flash Memory

Chi-Weon YoonSamsung Electronics

BiographyChi-Weon Yoon is a Vice President of Technology in Samsung Electronics, Hwa-sung, Korea. He received M.S and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004 respectively. After receiving the degree, he joined Samsung Electronics and have worked for more than 16 years at Flash Memory Design Team. He holds over 110 global patents about non-volatile memory related circuits and cell operation algorithms. His current research interests include design of high performance and low cost cell-operation algorithms, analog circuits and high speed I/O circuits.




AbstractAs 4th industrial revolution emerges, market demand for big data and AI computing is exponentially growing. Since high capacity and high performance data storage will play a role as a key enabler in data-centric era, related technology is one of the hottest topics of discussion. Along with this trend, NAND flash memory technology also has continued to evolve in terms of higher bit density and higher performance to meet the demand.In this tutorial, key technologies for implementing NAND flash memory will be presented. The tutorial starts from the basics such as operation concepts, related key circuits and process. Then, it will cover the issues the flash memory is currently facing and state-of-the-art technologies to overcome that hurdles when implementing higher capacity/performance data storage system in detail. Finally, some of candidates for future NAND flash will be introduced.


Monday, November 8IEEE Asian Solid - State Circuits Conference

A - SSCC 2021Plenary Speech

Plenary SpeechCrystal Ballroom

Plenary Speech I 08:50-09:35Creating the Future with Silicon in the Smart & Connected WorldES JungPresident & Chief Technology Officer, Samsung Electronics Device Solutions

BiographySince December 2020, Dr. Jung has been serving as CTO in Samsung Electronics Device Solutions. As the previous General Manager of Samsung Foundry Business, and Head of Semiconductor R&D Center and of System LSI Manufacturing Operation Center, he has brought his technology leadership and has successfully launched pure Samsung Foundry Business.During his tenure as GM of Samsung Foundry, Samsung Foundry has attracted many new business opportunities, and announced the world’s first EUV and embedded MRAM mass production. As Head of Samsung Semiconductor R&D Center, he has led advanced logic and specialty process technologies, including mass production of foundry industry's first 32/28nm high-k, metal gate and 14nm FinFET, world's first mass production of 10nm FinFET and Gate All-Around architecture. Moreover, Samsung's global leadership in DRAM and NAND Flash process technologies has been furthered. Since his appointment as CTO, he is leading research and development for the advanced process, equipment and material being in charge of Samsung Semiconductor R&D Center and Mechatronics R&D Center.He is a Member of the National Academy of Engineering of Korea. He has been awarded Grand Award in 2020 by The Institute of Electronics and Information Engineers, and the Silver Tower Order of Industrial Service Merit by the Korean Government in 2016. He holds MS in Physics from Seoul National University and Ph.D. in Physics from the University of Texas at Arlington.

AbstractThe COVID-19 Pandemic has changed the way we live and the social structure is experiencing paradigm shift, from face-to-face interactions to contactless interactions. This rapid transition is accelerating the evolution of smart & connected devices even further; which was already initiated by the 4th industrial revolution. The promising applications (automotive, AI, IoT, etc.) for smart & connected world will increase the demand of various semiconductor devices dramatically. Therefore, it is expected that the key driver of this trend will be semiconductors. However, the scaling and performance improvement of semiconductors are getting harder every year and numerous technologies are suggested to overcome these limitations.In this speech, I will present the current status of development of semiconductors and discuss few activities that are prepared to overcome the scaling and performance limitations. Also, I would like to emphasize the importance of the ecosystem that is needed in order to strengthen collaboration and continue the semiconductor evolution.

Plenary Speech II 09:35-10:20Zero Trust Security for Intelligent ElectronicsCharles Ching-Hsiang HsuChairman, eMemory Technology Inc.Chairman, PUFsecurity Cooperation

BiographyDr. Charles Hsu is the Chairman and founder of eMemory Technology Inc. He founded eMemory in 2000, aiming to provide the most innovative NVM IP technology. eMemory has achieved several technological breakthroughs and became the biggest logic-based non-volatile memory (Logic NVM) developer and provider globally. In 2019, Dr. Hsu founded PUFsecurity Cooperation, providing cost-effective and easy-to-adopt PUF-based (Physically Unclonable Function) hardware security IPs

Monday, November 8



A - SSCC 2021Plenary SpeechMonday, November 8

and solutions.Prior to founding eMemory, Dr. Hsu was the Chairman of the Institute of Electronics Engineering of National Tsing-Hua University (NTHU) from 1998 to 2000. He was also a professor in the Department of Electrical Engineering at NTHU from 1992 to 2000. Before returning to Taiwan, Dr. Hsu was a researcher at the IBM T.J. Watson Research Center in New York State, USA, since 1987. From 2010 to 2019, Dr. Hsu also served as the Executive Board Director of the Taipei Computer Association and has been invited to serve as the Board Director of the National Applied Research Laboratories in Taiwan since 2018. Dr. Hsu received his M.S. and Ph.D. in Electrical Engineering from the University of Illinois, Urbana-Champaign, in 1985 and 1987, respectively, and his B.S. in Electrical Engineering from the National Tsing Hua University (NTHU), Taiwan, in 1981.Dr. Hsu is renowned for his extensive research and inventions and received the Outstanding Research Award from the Taiwan National Science Council, the National Invention and Creation Gold Medal Award from the Taiwan Ministry of Economic Affairs, the Distinguished Alumni Award of NTHU, and the Distinguished Achievement Award from the Chinese Institute of Engineers, USA.

AbstractIn the IoT era, many edge devices are connected through the internet to servers and clouds, providing a lot of analytics information. To improve the smartness of edge devices, artificial intelligence (AI) is often deployed to edge devices to extract valuable data and help make decisions and reactions.While technology advanced, there are more devices connected to the cloud, creating more vulnerabilities. Security problems that were overlooked have now become critical issues. Therefore, building a secure and safe environment for intelligent devices is a MUST. PUF (Physically Unclonable Function), a reliable in-born silicon fingerprint built on each chip, can enable the chip to achieve security with Zero Trust Architecture, safeguarding the operation of connected, intelligent devices. Zero Trust security only accepts authenticated and authorized users and devices, and requires ”always verified.” We believe PUF-based security on-chip will bring hardware security to the forefront of the AIoT era and play an important role in securing devices.


SessionsMonday, November 8


Session 1: A1L-A Advanced Design, Reliability & Integration TechniquesCrystal Ballroom 1

Chair 1 Saki Hatta (NTT Japan) Chair 2 Taejoong Song (Samsung Electronics)

1.1 (3155) A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator10:40-11:05

Wataru Saito, Yoichi Iizuka, Norihito Kato, Ryota Otake, Fukashi MorishitaRenesas Electronics Corporation, Japan

1.2 (3005) A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration11:05-11:30 Xiping Jiang3, Fengguo Zuo3, Song Wang3, Xiaofeng Zhou3, Bing Yu3, Yubing Wang3, Qi Liu3,

Ming Liu1, Yi Kang2, Qiwei Ren3

1Institute of Microelectronics of the Chinese Academy of Sciences, China; 2University of Science and Technology of China, China; 3Xi'an UniIC Semiconductors, China

1.3 (3173) Dynamic Voltage Stress Sensing Circuits for Screening Out Early Device Reliability Issues in Advanced Technology Nodes11:30-11:55 Ghil-Geun Oh, Min-Hye Ho, Yeon-Jung Shin, Jae-Wook Choi, Ju-Youn Kim, Young-Dae KimSamsung Electronics, Korea

1.4 (3216) A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-Board × 9-Chip × 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems11:55-12:20 Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao YamaokaHitachi, Ltd., Japan

1.5 (3055) Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling12:20-12:45 Shenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J C Lee, Cheng-Hsiang HsiehTaiwan Semiconductor Manufacturing Company, Limited, United States



A - SSCC 2021

Special Session 1 IT Vision in Asia10:40-12:40 / Crystal Ballroom 2

"Beyond 5G, paving a path toward 6G"Software-Defined Beyond 5GAkihiro NakaoThe University of Tokyo

BiographyProf. Akihiro Nakao received B.S. (1991) in Physics, M.E. (1994) in Information Engineering from the University of Tokyo. He was at IBM Japan, Tokyo Research Laboratory, and IBM Texas Austin from 1994 till 2005. He received M.S. (2001) and Ph.D. (2005) in Computer Science from Princeton University. He has been teaching as an associate professor (2005-2014) and as a professor (2014-present) in Applied Computer Science, at Interfaculty Initiative in Information Studies, Graduate School of Interdisciplinary Information Studies, the University. From 2019 to 2021, he has served as Vice Dean of the University of Tokyo’s Interfaculty Initiative in Information Studies. He was appointed as an adviser to the President of the University of Tokyo in 2019 and has been a special adviser to the President of the University of Tokyo in 2020 and present. He was appointed as Chairman of 5G/Beyond 5G committee, Space ICT Promotion Initiative Forum and as Chairman of International Committee, Beyond 5G Promotion Consortium (2020-present). In April 2021, he has moved to School of Engineering, the University of Tokyo (2021-present) He is serving as Director, Collaborative Research Institute for NGCI, (Next-Generation Cyber Infrastructure), the University of Tokyo (2021-present).

AbstractThe need for robust communication infrastructure development to ensure the continuation of our socio-economic activities is being reaffirmed as a viable counter-measure to the new coronavirus infection that occurred simultaneously around the world. After the commercialization of 5G in 2020, the investment in the R&D of the next-generation cyber infrastructure has begun towards 2030. The aim of building next-generation cyber infrastructure is to transform socio-economic activities into more convenient and affluent ones by collecting and analyzing a large amount of data in real-time and draw high level predictions beyond human knowledge and uniting physical and cyber worlds together, by utilizing advanced features of communications such as high capacity, low-latency, and high-density connectivity. In this presentation, we posit that the enabling the prompt and flexible customizability in communication infrastructure in response to the social requirements is one of the key strategies towards defining a new generation cyber infrastructure and that democratizing end-to-end communication technologies using software-defined techniques plays an even further significant role in near future than present. We introduce our research activities towards software defined Beyond5G, the next generation cyber infrastructure.

Marching toward 6G: National Research Program in TaiwanTzong-Lin WuNational Taiwan University

BiographyTzong-Lin Wu received the B.S.E.E. and Ph.D. degrees from National Taiwan University (NTU), Taiwan, in 1991 and 1995, respectively. He was with National Sun Yat-Sen University from 1998 to 2005. He joined NTU in 2005 and is currently a Professor of the Department of Electrical Engineering and an Associate Dean of the College of Electrical Engineering and Computer Science, NTU, since 2018. His research interests include EMC/EMI and signal/power integrity design for high-speed digital/optical systems. Dr. Wu served the IEEE EMC Society as a Distinguished Lecturer in 2008–2009 and a Member of Board of Directors (BoD) during 2016–2022. Dr. Wu is an IEEE fellow, and he is currently the Editor-in-Chief of the IEEE TRANSACTIONS

IT Vision in Asia



A - SSCC 2021IT Vision in Asia

ON EMC. He is now the Chair of National Research Program for Next Generation Communication Systems initiated by Ministry of Science and Technology (MOST) in Taiwan.

AbstractMobile communication has become an important infrastructure that must constantly evolve to meet the requirements of emerging applications. As 5G systems are just being rolled out, researchers from academia and industry have begun to conceptualize the next generation mobile communication (6G). In Taiwan, a government-sponsored program for 6G researches was kicked off in June, 2021. The program aims at developing breakthrough technologies, cultivating communication talents, integrating academic and industrial R&D resources, building collaboration with international research teams and standard organizations. This talk will also briefly introduce the program scope which covers the core technologies to enable the 6G communication with extreme high speed, extreme coverage, and intelligent and diverse capability.

A Perspective of China’s 6G ResearchesZhisheng NiuTsinghua University

BiographyZhisheng Niu graduated from Beijing Jiaotong University, China, in 1985, and got his M.E. and D.E. degrees from Toyohashi University of Technology, Japan, in 1989 and 1992, respectively. During 1992-94, he worked for Fujitsu Laboratories Ltd., Japan, and in 1994 joined with Tsinghua University, Beijing, China, where he is now a professor at the Department of Electronic Engineering. His major research interest is wireless communications and networking. He received the Outstanding Young Researcher Award from Natural Science Foundation of China in 2009, Best Paper Awards from IEEE Communication Society Asia-Pacific Board in 2013, and Distinguished Technical Achievement Recognition Award from IEEE Communications Society Green Communications and Computing Technical Committee in 2018. Currently he is serving as Editor-in-Chief of IEEE Trans. Green Commun. & Networks. He was selected as a distinguished lecturer of IEEE Communication Society (2012-2015) as well as IEEE Vehicular Technologies Society (2014-2018). He is a fellow of both IEEE and IEICE.

AbstractAs one of the leading markets in the world, Chinese operators have started to build their 5G trial networks since December 2018, reaching to 900K+ 5G BSs and 360M+ 5G users today. As a result, research focus has been shifting from 5G to 5.5G as well as 6G technologies. Several nationwide promotion groups on 6G technologies have been established and tens of 6G-related R&D projects have been funded. This talk will highlight such R&D activities in China and discuss about their potential challenges and research directions.

Public-Private 6G Lifetime Collaboration in KoreaDong Ku Kim5G Forum (Yonsei University)

BiographyDONG KU KIM received his Ph.D. from the University of Southern California, Los Angeles, in 1992. He worked on CDMA systems in the cellular infrastructure group of Motorola at Fort Worth, Texas. He has been a professor at the School of Electrical and Electronic Engineering, Yonsei University, since 1994. He was a founding chair of the 5G Forum in 2013, which is a think thank for 5G strategy, 5G commercialization, SME promotion, 5G vertical trial and promotion, and future technologies. He is a chair of the 5G Forum executive committee and a member of the 5G+ strategy committee of the Ministry of Science and ICT. He is also co-chair of the 6G R&D strategy committee of MSIT. He received the Yellow Stripes of the Order of Service Merit from



A - SSCC 2021IT Vision in Asia

the Korean government for the contribution of the world's first commercialization of 5G, ecosystem creation, and the diffusion of convergence among 5G-based industries in April 2020. He received IEEE Communication Society Career Award for Public Service in the Field of Telecommunication on Dec. 2020. He also received the Award of Excellence in the leadership of 100 Leading Technologies for Korea 2020 from the National Academy of Engineering of Korea in Dec. 2013. His current research interests are 5G mobile communication systems, full-duplex MIMO, tactile internet, 5G-V2X technologies using lens-based MIMO, and smart ocean buoy communication.

AbstractIn April 2019 just after Korea rolled out the world first 5G commercialization, the MSIT put out a series of moves to ramp up the 5G diffusion opportunities to a variety of vertical industry. The 5G+ strategy drives cross-ministerial public private collaboration to promote 5G for industry. In 2020, the digital new deal projects started to adopt 5G and AI to public administration and public-infrastructure. Last August, the ministry put out the 6G R&D strategy and its public-private collaboration. In this talk, we will share some of lessons from 5G, and how we would do better in 6G in Korea.




Session 2: A2L-A Power Conversion & Wireless Power TransferCrystal Ballroom 1

Chair 1 Hyun-Sik Kim (KAIST) Chair 2 Makoto Takamiya (Univ. of Tokyo)

2.1 (3014) An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current14:00-14:25 Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo MartinsUniversity of Macau, Macau

2.2 (3255) A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM14:25-14:50

1University of Macau, Macao, China; 2Southern University of Science and Technology, Shenzhen, China

2.3 (3068) A 87.2%-Efficiency 27.12MHz Current-Mode Wireless Power Receiver with Ramp-Assisted Energy Delivery Controller for Implantable Devices14:50-15:15 Ziyang Luo, Hoi LeeUniversity of Texas at Austin, United States

2.4 (3205) A 5.7GHz RF Wireless Power Transfer Receiver Using 84.5% Efficiency 12V SIDO Buck-Boost DC-DC Converter with Internal Power Supply Mode15:15-15:27 Tomohiro Higuchi1, Dai Suzuki1, Ryo Ishida1, Yasuaki Isshiki1, Kazuki Arai2, Kohei Onizuka2, Kousuke Miyaji1

1Shinshu University, Japan; 2Toshiba Corporation, Japan

2.5 (3002) A Multi-Phase Series-Parallel with Bond Wire Auxiliary Fully-Integrated 250pF Switched-Capacitor with 13.6mV Output Ripple for Supplying Temperature Sensor with 0.1°C Accuracy to Early Detect COVID-19

15:27-15:39

Shu-Yung Lin1, Chin-Hsiang Liang1, Kai-Syun Chang1, Ke-Horng Chen1, Ying-Hsi Lin2, Shian-Ru Lin2, Tsung-Yen Tsai2

1National Yang Ming Chiao Tung University, Taiwan; 2Realtek Semiconductor Corp, Taiwan

Session 3: A2L-B AI & Vision ProcessorsCrystal Ballroom 2

Chair 1 Yongtae Kim (Kyungpook National University) Chair 2 Jun Yin (University of Macau)

3.1 (3221) FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling14:00-14:25 Surin Gweon, Sanghoon Kang, Donghyeon Han, Kyoung-Rog Lee, Kwantae Kim, Hoi-Jun YooKAIST, Korea

Wen-Liang Zeng1, Caolei Pan1, Chi-Seng Lam1, Sai-Weng Sin1, Chenchang Zhan2, Rui PauloMartins1




3.2 (3126) RAODAT: An Energy-Efficient Reconfigurable AI-Based Object Detection and Tracking Processor with Online Learning14:25-14:50 Yuchuan Gong, Qingsong Liu, Luying Que, Conghan Jia, Jiahui Huang, Ye Liu, Jiayan Gan, Yuxiang Xie, Yong Zhou, Lili Liu, Xiaoqiang Xiang, Liang Chang, Jun ZhouUniversity of Electronic Science and Technology of China, China

3.3 (3225) A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution14:50-15:15 Shifu Wu2, Kalana De Silva1, Snehlata Gutgutia1, Bevan Baas2, Massimo Alioto1

1National University of Singapore, Singapore; 2University of California, Davis, United States

3.4 (3261) A 4.57µW@120fps Vision System of Sensing with Computing for BNN-Based Perception Applications15:15-15:40 Han Xu2, Zheyu Liu2, Ziwei Li1, Erxiang Ren1, Maimaiti Nazhamati2, Fei Qiao2, Li Luo1, Qi Wei2, Xinjun Liu2, Huazhong Yang2

1Beijing Jiaotong University, China; 2Tsinghua University, China

Session 4: A2L-C Terahertz & Millimeter-Wave Circuits & SystemsCrystal Ballroom 3

Chair 1 Tae Wook Kim (Yonsei University) Chair 2 Chien-Nan Kuo (National Yang Ming Chiao Tung University)

4.1 (3170) A 76-Gbit/s 265-GHz CMOS Receiver14:00-14:25 Shinsuke Hara3, Ruibing Dong3, Sangyeop Lee1, Kyoya Takano5, Naoya Toshida2, Satoru Tanoi3,

Tatsuo Hagino3, Mohamed Mubarak3, Norihiko Sekine3, Issei Watanabe3, Akifumi Kasamatsu3, Kunio Sakakibara2, Shunichi Kubo4, Satoshi Miura4, Yohtaro Umeda5, Takeshi Yoshida1, Shuhei Amakawa1, Minoru Fujishima1

1Hiroshima University, Japan; 2Nagoya Institute of Technology, Japan; 3National Institute of Information and Communications Technology, Japan; 4THine Electronics, Japan; 5Tokyo University of Science, Japan

4.2 (3075) 245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2- and 4-Way Power Combining14:25-14:50 Byeonghun Yun1, Dae-Woong Park2, Kyung-Sik Choi1, Ho-Jin Song3, Sang-Gug Lee1

1KAIST, Korea; 2KAIST/IMEC, Korea; 3Pohang University of Science and Technology, Korea

4.3 (3163) A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-Bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS14:50-15:15 Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong ChiTsinghua University, China

4.4 (3133) A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology15:15-15:27 Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong ChiTsinghua University, China




4.5 (3056) A 150-to-1050 GHz Terahertz Detector in 65 nm CMOS15:27-15:39 Zhao-Yang Liu, Feng Qi, Ye-Long Wang, Peng-Xiang Liu, Wei-Fan Li

Shenyang institute of automation, Chinese academy of sciences, China

Session 5: A2L-D Circuits & Systems for Emerging ApplicationsPearl Room

Chair 1 Ping-Hsuan Hsieh (National Tsing Hua University) Chair 2 Minkyu Je (Korea Advanced Institute of Science and Technology (KAIST))

5.1 (3177) A 0.033-mm2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity Up to 480pF14:00-14:25 Hyeyeon Lee2, Changuk Lee2, Jae-Youl Lee1, Yoon-Kyung Choi1, Youngcheol Chae2

1Samsung Electronics, Korea; 2Yonsei University, Korea

5.2 (3238) A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-Transistor Adiabatic Logic with an Inductively Connected External Antenna14:25-14:50 Saito Shibata, Reiji Miura, Yoshiki Sawabe, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro KurodaUniversity of Tokyo, Japan

5.3 (3161) A 389TOPS/W, 1262fps at 1Meps Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS14:50-15:02 Sumon Bose1, Arindam Basu2

1Nanyang Technological University, Singapore; 2Nanyang Technological University and City University of Hong Kong, Hong Kong

5.4 (3189) A Millimeter-Scale Computing System with Adaptive Dynamic Load Power Tracking15:02-15:14 Seokhyeon Jeong1, Yejoong Kim1, Yuyang Li2, Inhee Lee2

1CubeWorks, United States; 2University of Pittsburgh, United States

5.5 (3204) A 1280 × 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation15:14-15:26 Pei-Yi Lai Lee4, Ya-Wen Yang1, Sih-Han Li1, Jian-Jhih Sun4, Tzu Yi Hung4, Chih-Wen Lu5, Yen-

Hsiang Fang1, Wei-Hung Kuo1, Li-Chun Huang1, Guo-Dung Su2, Poki Chen3

1Industrial Technology Research Institute, Taiwan; 2National Taiwan University, Taiwan; 3National Taiwan University of Science and Technology, Taiwan; 4National Tsing Hua University, Taiwan; 5National Yang Ming Chiao Tung University, Taiwan

5.6 (3114) A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout15:26-15:38 Alican Caglar2, Steven Van Winckel1, Steven Brebels1, Piet Wambacq2, Jan Craninckx1

1IMEC, Belgium; 2IMEC, Vrije Universiteit Brussel, Belgium



A - SSCC 2021

PIM (Processing in Memory) will go with Analog or Digital?

Date: Nov. 8, 2021Time: 16:00-17:40 (Korea Standard Time)

Abstract:The unprecedented growth in computing and processing has led to massive amounts of data movement from off-chip units to on-chip memories. To deal with the complex processing, shall we use analog circuits or digital circuits? If digital, what are the popular techniques and the main bottleneck? If analog, what are the emerging solutions and the design challenges? In this panel discussion session, we will have 6-7 experts as the panelists to share their view.

Organizer/Co-organizer: Zhihua Wang, Tsinghua University, China Bo Zhao, Zhejiang University, China

Moderator: Seung-Tak Ryu, KAIST, South Korea Bo Zhao, Zhejiang University, China

Panelists/Positions:1. Feng Lin (Changxin Memory Technology) Bio: Feng Lin received his Ph.D. in Electrical Engineering from University of Idaho, United States in 2000, and MSEE and BSEE degrees from University of Electronics, Science and Technology of China in 1995 and 1992 respectively. From 2000 to 2019, Dr. Lin was with Micron Technology, Inc. in Boise, Idaho, as a Senior Member of Technical Staff, developing industry leading memory products, including GDDR6x, Hybrid-memory cube (HMC), and various low-power and high-speed memory interfaces. Dr. Lin holds over 120 US and international patents and is a co-author of textbook DRAM Circuit Design, Fundamental and High-Speed Topics(IEEE Press 2007). Since 2019, Dr. Lin isa Fellow in Product R&D departmentat Changxin Memory Technologies, Inc.,overseeingtechnologydevelopment of advancedmemory products.His research interests include high-speed energy efficient I/O, signal & power integrity, advanced memory architecture and memoryapplications in AI and datacenters.

Abstract: Will industries embrace processing-in-memory (PIM)? And How?AI (artificial intelligent) and ML (machine learning) bring computing into data centric world. Conventional Von-Neumann architecture creates big bottleneck for data movement between CPU and off-chip memory, which results in limited bandwidth, longer latency and wasted energy. Processing-in-memory (PIM) has been brought up to break the memory wall and combinedata storage and compute in one place. The concept is not new, but it hardly finds its place in the industry, especially for DRAM-based approach. Asgeneral-purpose DRAM getsbigger and faster, there is still needs to exploring PIM for some special applications and maximize overall performance per watts. This talk will give a few examples for real PIM implementations in the industry, their pros and cons, and discuss potential solutions to make it a reality in the memory industry.

2.Tony T. Kim (Nanyang Technological University) Bio: Prof. Tony Tae-Hyoung Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics. In November 2009, he joined Nanyang Technological University where he is currently an associate professor. His current research interests include in-memory computing for edge computing, emerging memory circuit design, energy-efficient circuits and systems for IoT and wearable devices, and variation tolerant circuits and systems.

Panel Discussion



A - SSCC 2021Panel Discussion

He has received many awards including Best Demo Award at 2016 IEEE APCCAS, International Low Power Design Contest award at 2016 IEEE/ACM ISLPED, etc. He is an author/co-author of +190 journal and conference papers and holds 17 US and Korean patents. He was the Chair of IEEE SSCS Singapore Chapter in 2015~2016. He is the Chair-Elect/Secretary of IEEE CASS VLSI Systems & Applications Technical Committee and a senior member of IEEE.

Abstract: Will nonvolatile memories help to improve the efficiency of PIM? Which nonvolatile memories are more promising? What are the challenges in nonvolatile PIM design? What are the pros and cons of nonvolatile PIM? What are the target applications of nonvolatile PIM? Can nonvolatile PIM provide satisfactory accuracy?

3. Ken Takeuchi (University of Tokyo) / How to heterogeneously integrate PIM for Edge AI?Bio: Ken Takeuchi is currently a Professor at Department of Electrical Engineering and Information Systems, Graduate School of Engineering of The University of Tokyo. He is now working on data-centric computing such as computation in memory, approximate computing, data scale computing, AI chip design and brain-inspired memory. He received the B.S. and M.S. degrees in Applied Physics and the Ph.D. degree in Electric Engineering from The University of Tokyo in 1991, 1993 and 2006, respectively. In 2003, he also received the M.B.A. degree from Stanford University. He has authored numerous technical papers, one of which won the Takuo Sugano Award for Outstanding Paper at ISSCC 2007. He served as the symposium chair of Symposium on VLSI Circuits 2021. He has also served on the program committee member of International Solid-State Circuits Conference (ISSCC), Custom Integrated Circuits Conference (CICC), Asian Solid-State Circuits Conference (A-SSCC), International Memory Workshop (IMW) and International Conference on Solid State Devices and Materials (SSDM).

Abstract: How to heterogeneously integrate PIM for Edge AI? By the thermal limit, the frequency of general CPU is hitting the ceiling. Thus, domain specific computing with dedicated accelerators like PIM is required especially for emerging AI applications. This talk discusses how to heterogeneously integrate traditional CPU and PIM for edge AI applications. Software support such as programming model & compiler is essential. Moreover, co-design of algorithm, circuit & device becomes KEY. In addition, to achieve a massively parallel MAC (Multiply-Accumulate) operation, voltage sensing vs. current sensing of PIM is discussed.

4.Yuchao Yang (Peking University, China) Bio: Yuchao Yang serves as Director of Center for Brain Inspired Chips at Peking University and Executive Director of Center for Brain Inspired Intelligence at Chinese Institute for Brain Science. His research interests include memristors, neuromorphic computing, and in-memory computing. He has published over 100 papers in high-profile journals and conferences such as Nature Electronics, Nature Communications, Nature Nanotechnology, Science Advances, Advanced Materials, Nano Letters, IEDM, etc. as well as 5 book chapters. His papers have been cited >5500 times, with an H-index of 33. He was invited to give >30 keynote/invited talks on international conferences and serves as TPC chair or member for 9 international conferences. Yuchao Yang serves as the Associate Editor for Nano Select and editorial board member of Chip, Scientific Reports and Science China Information Sciences. He was invited to guest edit 3 special issues and write 12 News & Views, review articles, etc. He is a member of IEEE, MRS and RSC. He is a recipient of the National Outstanding Youth Science Fund, Qiu Shi Outstanding Young Scholar Award, Wiley Young Researcher Award, MIT Technology Review Innovators Under 35 in China, and the EXPLORER PRIZE.

Abstract: How to conduct PIM through memristors? Since the connection of the theoretical memristor concept with physical resistive switching devices in 2008, tremendous progress has been made in terms of material and device technology developments and their applications in memory and computing systems. The physical embodiments of memristors correspond to various resistive switching devices based on different mechanisms. These mechanisms endow the memristors with rich nonlinear dynamics, which is key to constructing biologically plausible dynamic computing systems. Memristor can be described as a set of differential equations that indicate how the internal state variables determine device characteristics and how external electrical stimulations influence these state



A - SSCC 2021Panel Discussion

variables. The increases in the number of state variables and internal dynamics have dramatically enriched the dynamics and functionality of memristors. Further exploration and control of such dynamics are essential for highly efficient information processing applications.

5. Bin Gao (Tsinghua University, China) Bio: Bin Gao is currently an Associate Professor with the School of Integrated Circuits, Tsinghua University, Beijing, China. He received the B.S. degree in 2008 and Ph.D. degree in 2013, both from Peking University, Beijing, China. His current research interests include fabrication, characterization, and modeling of emerging semiconductor devices, especially RRAM, and design of computation-in-memory and neuro-inspired computing system. He has published more than 100 technical papers on Nature, Nature Electronics, Proceedings of the IEEE, EDL, TED, JSSC, IEDM, ISSCC, VLSI, etc. His total citation is over 6000. He was a recipient of the IEEE EDS Ph.D. Student Fellowship in 2012. He served as Sub-committee Chair of IEDM, EDTM, and ICTA, and TPC member of DAC, IRPS, IPFA, etc.

Abstract: What’s the design challenges in analog RRAM for PIM?Resistive Random Access Memory (RRAM) technology provides great opportunity for implementation of Computation-in-Memory (CIM) and Processing-near-Memory (PNM) architecture. Using RRAM as a main part of the system, a new computation hierarchy can be designed, in which analog RRAM array will serve as a CIM core for matrix-related computation and digital RRAM will serve as large-capacity distributed on-chip memory. At the current stage, digital RRAM technology is pretty mature, but analog RRAM technology still faces several major challenges, including device reliability degradation, accuracy loss, large AD/DA overhead, etc. In the future, system-technology co-optimization (STCO) is highly required for analog RRAM based CIM system to address the above challenges. On-chip training function will help to improve the computing accuracy and extend the application fields of analog RRAM based CIM chips. 1POPS computing power per chip and 20TOPS/W energy efficiency (whole SoC chip) on the RRAM chip for AI acceleration applications can be expected within 3 years


Tuesday, November 9IEEE Asian Solid - State Circuits Conference

A - SSCC 2021Plenary SpeechTuesday, November 9

Plenary SpeechCrystal Ballroom

Plenary Speech III 09:00-09:45From Labs to Startups: Reinventing Engineering EducationZexiang LIProfessor, Department of Electronic & Computer Engineering, HKUSTChairman of Songshan Lake XbotParkChairman of Googol TechnologyChairman of DJI

BiographyZexiang Li attended the South-Central University in 1978, received his BS (with honor) degrees in Electrical Engineering and Economics from Carnegie-Mellon University in 1983, his MS degree in EECS in 1985, MA in mathematics and PhD in EECS in 1989, all from the University of California at Berkeley. He worked at ALCOA, the Robotics Institute of CMU and the AI Lab of MIT (89-90). He was an assistant professor at the Courant Institute of New York University (90-92). In 1992, he joined the Department of Electronic and Computer Engineering of the Hong Kong University of Science and Technology and is currently a professor of the department. He founded the Automation Technology Center (ATC) and Robotics Institute (RI).In 2019, Prof. Li was selected as co-recipient of the 2019 IEEE Robotics and Automation Award for his influential “contributions to the development of civilian drones, aerial imaging technology, robotics engineering advancement, innovation and entrepreneurship.”

AbstractEducation serves an important role to cultivate the new generations. And the world is changing fast by advanced technologies. Pursue the leading technology and combine with the user needs, is the key to innovate.In this speech, I would like to present the exploration of engineering education with real examples, from doing my first start-ups to the current innovation eco-system. Compared with existing traditional education system, the biggest step is to combine the engineering students with design background students together, to form a multidisciplinary environment, that may ignite sparks.In addition, I will discuss the challenges we face and the opportunities we have in the Great Bay Area.

Plenary Speech IV 09:45-10:30Electronic Skins for Robotics and WearablesTakao SomeyaDean, School of Engineering, The University of Tokyo

BiographyTakao Someya received his Ph.D. degree in electrical engineering from the University of Tokyo in 1997. Since 2009, he has been a professor of Department of Electrical and Electronic Engineering, The University of Tokyo. From 2001 to 2002, he worked at the Nanocenter (NSEC) of Columbia University and Bell Labs, Lucent Technologies, as a Visiting Scholar. His current research focus is on stretchable and flexible organic electronics for the applications to healthcare, biomedical and robotics. He conducted NEDO/JAPERA Project as Project Leader (2011-2019) and currently leading JST/ACCEL Super-bioimager Project as Research Director (2017-2022). Prof. Someya received The 16th Leo Esaki Prize and the Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology in 2019. He was appointed a global scholar of Princeton University (2009-2017), MRS board of directors (2009-2011), and National University of Singapore (NUS)



A - SSCC 2021Plenary Speech

GlobalFoundaries Visiting Professor (2016-2019). His current appointments are: The Technical University of Munich (TUM) Hans Fischer Senior Fellow (2017-), Director of The Japan Society of Applied Physics (2018-), Associate Editor of Science Advances, and IEEE Spectrum Editorial Advisory Board Member.His current research interests include organic transistors, flexible electronics, plastic integrated circuits, large-area sensors, and plastic actuators.

AbstractWearable technology enables personalization of medical care. To expand its emerging applications, soft biomedical sensors have attracted much attention. Use of soft electronic materials for devices that come into contact with the skin can minimize discomfort of wearing sensors and, thanks to recent progress, intimate and conformal integration of electronics with the human skin can be created to continuously monitor health conditions for long periods. It has potential to drastically change the nature of medical examination and treatment. My talk will review recent progress in stretchable thin-film electronics for applications to robotics and wearables and address its issues and prospects.


SessionsTuesday, November 9


Session 6: B1L-A Temperature & Voltage ManagementsCrystal Ballroom 1

Chair 1 Michael Choi (Samsung, Korea) Chair 2 Wanyuan Qu (Zhejiang University)

6.1 (3262) Auto-Calibration Technique for Current-Based Bandgap Voltage Reference10:50-11:15 Chi-Wa U, Man-Kay Law, Chi-Seng Lam, Rui Paulo Martins

University of Macau, China

6.2 (3092) A 3.1-µW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C11:15-11:40 Jee-Ho Park, Jung-Hye Hwang, Changyong Shin, Seong-Jin KimUlsan National Institute of Science and Technology, Korea

6.3 (3154) An Output Capacitor-Less Low-Dropout Regulator Using a Wide-Range Single-Stage Gain-Boosted Error Amplifier & a Frequency-Dependent Buffer with a Total Compensation Capacitance of 2.5pF in 0.5 µm CMOS

11:40-12:05

Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Sung-Wan HongSogang University, Korea

6.4 (3107) Zero Current Detector with Slope Judgement Calibration in Mobile Battery Charger IC12:05-12:17 Kye-Seok Yoon, Hye-Bong Ko, Jin-Woo So, Sung-Woo Lee, Sung-Kyu Cho, Woon-Hyung Heo,

Ho-Sung Son, Seung-Hoon Kim, Dong-Joon Kim, Kwon-Yub Hyung, Dae-Woong Cho, Jung-Wook Heo, Hyoung-Seok Oh, Sung-Ung KwakSamsung Electronics, Korea

6.5 (3243) A Process Scalable Voltage-Reference-Free Temperature Sensor Utilizing MOSFET Threshold Voltage Variation12:17-12:29 Shogo Harada, Mahfuzul Islam, Takashi Hisakado, Osami WadaKyoto University, Japan

Session 7: B1L-B FPGA Design for AI/ML ApplicationsCrystal Ballroom 2

Chair 1 Yongjoo Lee (Pohang University of Science and Technology (POSTECH)) Chair 2 Hayun Chung (Korea University)

7.1 (3224) A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator Using Multi-Thread Computing and Binary Max Engine for Object Detection10:50-11:15 Chaoming Fang1, Habib Derbyshire2, Wenyu Sun2, Jinshan Yue2, Haobing Shi1, Yongpan Liu2

1Pi2star Technology, China; 2Tsinghua University, China




7.2 (3229) An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-Precision Re-Training11:15-11:40 Wooyoung Jo, Juhyoung Lee, Seunghyun Park, Hoi-Jun YooKAIST, Korea

7.3 (3111) A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator Using the Double-Layer MAC and DSP Efficiency Enhancement11:40-11:52 Jixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo MartinsUniversity of Macau, Macau

7.4 (3125) A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots11:52-12:17 Jipeng Wang1, Yi Zhan1, Zhaoxu Wang1, Zixuan Peng1, Jiarui Xu1, Bingqiang Liu1, Guoyi Yu1, Fengwei An2, Chao Wang1, Xuecheng Zou1

1Huazhong University of Science and Technology, China; 2Southern University of Science and Technology, China

7.5 (3059) Tiny Neural Network Search and Implementation for Embedded FPGA: A Software-Hardware Co-Design Approach12:17-12:29 Jinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng ZhaoBeihang University, China

Session 8: B1L-C Smart MemoryCrystal Ballroom 3

Chair 1 Ik Joon Chang (Kyunghee University) Chair 2 Tony T. Kim (Nanyang Technological University)

8.1 (3195) A 40nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier

10:50-11:15

Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi KonoRenesas Electronics Corporation, Japan

8.2 (3081) A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking 11:15-11:40 Lu Lu, Tony Tae-Hyoung Kim

Nanyang Technological University, Singapore

8.3 (3239) Realizing Direct Convolution in Memory with Systolic-Ram11:40-12:05 Jacob Rohan, Jaydeep Kulkarni

University of Texas at Austin, United States




8.4 (3235) CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation12:05-12:17 Brian Crafton2, Samuel Spetalnick2, Jong-Hyeok Yoon1, Wei Wu3, Carlos Tokunaga3, Vivek De3, Arijit Raychowdhury2

1Daegu Gyeongbuk Institute of Science and Technology, Korea; 2Georgia Institute of Technology, United States; 3Intel, United States

8.5 (3096) A 48 Tops and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration12:17-12:29 Chih-Sheng Lin1, Fu-Cheng Tsai1, Jian-Wei Su1, Sih-Han Li1, Tian-Sheuan Chang2, Shyh-Shyuan Sheu1, Wei-Chung Lo1, Shih-Chieh Chang1, Chih-I Wu1, Tuo-Hung Hou1

1Industrial Technology Research Institute, Taiwan; 2National Yang Ming Chiao Tung University, Taiwan

Session 9: B1L-D Clock Recovery & GenerationPearl Room

Chair 1 Yong Chen (University of Macau) Chair 2 Gyungsu Byun (Inha University)

9.1 (3182) A 48Gb/s 2.4pJ/B PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS10:50-11:15 Haram Ju1, Kwangho Lee2, Woosong Jung2, Deog-Kyoon Jeong2

1Korea Electronics Technology Institute, Korea; 2Seoul National University, Korea

9.2 (3108) A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth11:15-11:40 Yen-Kuei Lu2, Miao-Shan Li2, Ching-Yuan Yang2, Chin-Lung Lin1

1ILI Technology Corp., Taiwan; 2National Chung Hsing University, Taiwan

9.3 (3140) An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS Process11:40-12:05 Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan SankaranTexas Instruments, United States

9.4 (3041) A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction12:05-12:17 Yu-Sian Lu, Cheng-Lung Lee, Wei-Zen ChenNational Yang Ming Chiao Tung University, Taiwan




Session 10: B2L-A SAR-based Hybrid ADCs & TDCCrystal Ballroom 1

Chair 1 Seung-Tak Ryu (KAIST) Chair 2 Tsung-Heng Tsai (National Chung Cheng University)

10.1 (3113) A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-Insensitive Voltage-Time-Voltage Converter14:00-14:25 Chih-Cheng Chen, Chih-Cheng HsiehNational Tsing Hua University, Taiwan

10.2 (3047) An Input-Buffer Embedding Dual-Residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation14:25-14:50 Seungyong Lim1, Raymond Mabilangan1, Dong-Jin Chang1, Youngjae Cho2, Michael Choi2, Seung-Tak Ryu1

1KAIST, Korea; 2Samsung Electronics, Korea

10.3 (3187) A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration14:50-15:15 Yu-Sian Liao, Wei-Zen ChenNational Yang Ming Chiao Tung University, Taiwan

10.4 (3228) 1.55mW 2GHz Erbw 7b 800MS/s 3-Stage Pipelined SAR ADC in 28nm CMOS Using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with Only 16fF Input Capacitance15:15-15:27 Hyeonsik Kim2, Seonkyung Kim3, Jintae Kim1

1Konkuk University, Korea; 2Konkuk University / Mixed Signal Electronics Laboratory, Korea; 3Samsung Electronics, Korea

10.5 (3129) A 4.39ps, 1.5GS/s Time–To-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array15:27-15:39 Yongkuo Ma1, Peiyuan Wan1, Hongda Zhang1, Zhi Wan2, Xiaoyu Zhang1, Xu Liu1, Zhijie Chen1

1Beijing University of Technology, China; 2Changchun University of Science and Technology, China

Session 11: B2L-B Security & Signal Processing SoCsCrystal Ballroom 2

Chair 1 Tsung-Te Liu (National Taiwan University) Chair 2 Joo Young Kim (Kaist)

11.1 (3097) A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices14:00-14:25 Sheng-Jung Yu2, Yu-Chi Lee1, Chia-Hsiang Yang1

1National Taiwan University, Taiwan; 2University of California, Berkeley, United States




11.2 (3167) A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message Ems Algorithm in 22nm FinFET Technology14:25-14:50 Jeongwon Choe, Youngjoo LeePohang University of Science and Technology, Korea

11.3 (3034) A 0.46pJ/Bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER<6.7×10-614:50-15:15 Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo MartinsUniversity of Macau, China

11.4 (3156) A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring15:15-15:40 Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang

National Taiwan University, Taiwan

Session 12: B2L-C High-Performance VCOs & PLLsCrystal Ballroom 3

Chair 1 Dixian Zhao (Southeast University) Chair 2 Jaehyouk Choi (KAIST)

12.1 (3179) A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS14:00-14:25 Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui Paulo MartinsUniversity of Macau, China

12.2 (3169) A 196.2 dBc/Hz FOMT 16.8-to-21.6 GHz Class-F23 VCO with Transformer-Based Optimal Q-Factor Tank in 65-nm CMOS14:25-14:50 Feifan Hong, Tianao Ding, Dixian ZhaoSoutheast University, China

12.3 (3130) A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref14:50-15:15 Zule XuUniversity of Tokyo, Japan

12.4 (3139) A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter15:15-15:27 Mario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore LevantinoPolitecnico di Milano, Italy

12.5 (3143) A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-Less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing Alignment15:27-15:39 Khoi Trong Phan1, Yue Chao2, Howard Cam Luong1

1Hong Kong University of Science and Technology, Hong Kong; 2Qualcomm, United States




Session 13: B2L-D Imagers & ToFsPearl Room

Chair 1 Noriyuki Miura (Osaka University) Chair 2 Youngchoel Chae (Yonsei University)

13.1 (3069) A 7m-Range, 4.3mW/Ch. Ultrasound ASIC with Universal Energy Recycling TX for All-Weather Metamorphic Robotic 3D Vision System14:00-14:25 Han Wu2, Miaolin Zhang2, Jiaqi Guo2, Zhichun Shao3, Kian Ann Ng1, Jiamin Li2, Lian Zhang2, Yilong Dong2, Liuhao Wu2, Chne-Wuen Tsai2, Benjamin Ho Yin Lee2, Liwei Lin3, Jerald Yoo2

1Digipen institute of technology, Singapore; 2National University of Singapore, Singapore; 3University of California, Berkeley, United States

13.2 (3176) Self-Powered Light Sensor for Simultaneous Intensity-and-Direction Sensing and Maximum-Energy Harvesting with Shared Photodiodes14:25-14:50 Tai-Haur Kuo, Kuan-Yu Chen, Hsiao-Ping Lin, Shang-Jung LiuNational Cheng Kung University, Taiwan

13.3 (3230) An Integrated 8A Pulsed VCSEL Array Driver Under 12V Supply with Built-In Pulse Monitor and Automatic Peak Current Control for Direct Time-of-Flight Applications14:50-15:02 Tao Xia1, Xuefeng Chen2, Yuwei Wang2, Yuan Li1, Yifan Wu2, Lei Wang2, Liujia Song2, Shenglong Zhuo1, Zhihong Lin1, Patrick Yin Chiang1

1Fudan University, China; 2PhotonIC Technologies Shanghai Co., Ltd, China

13.4 (3116) A 640×512 30µm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-Out Integrated Circuit with Fully On-Chip Image Algorithm Pixel-Level Calibration15:02-15:14 Yan Zeng2, Shiheng Yang2, Yueduo Liu2, Zehao Li2, Wengang Huang1, Xiaozong Huang1, Xiong Zhou2, Jiaxin Liu2, Qiang Li2

1China Electronics Technology Group Corporation No.24 Research Institute, China; 2University of Electronic Science and Technology of China, China

13.5 (3101) A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems15:14-15:26 Yi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-

Hao Huang, Po-Chiun HuangNational Tsing Hua University, Taiwan

13.6 (3004) A 70mW Indirect Time-of-Flight Image Sensor with Depth Dynamic Range Enhancement and Fixed Depth Noise Compensation15:26-15:38 Canxing Piao2, Yeonsoo Ahn2, Donguk Kim2, Jihoon Park3, Jubin Kang4, Minseok Shin1, Kangbong Seo1, Seong-Jin Kim4, Jung-Hoon Chun3, Jaehyuk Choi3

1SK hynix Inc, Korea; 2Sungkyunkwan University, Korea; 3Sungkyunkwan University, SolidVue, Korea; 4Ulsan National Institute of Science and Technology, Korea



A - SSCC 2021ESSCIRC Joint Session

Special Session 2 ESSCIRC Joint Session

A −109.1 dB/−98 dB THD/THD+N Chopper Class-D Amplifier with >83.7 dB PSRR Over the Entire Audio BandHuajun ZhangDelft Univ of Technology

BiographyHuajun Zhang received the B.E. degree in electrical and computer engineering from Shanghai Jiao Tong University, Shanghai, China, in 2015, and the B.S.E. and M.S. degrees in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2015 and 2017, respectively. From May 2017 to February 2019, he was a Mixed Signal Design Engineer with Analog Devices, Inc., Norwood, MA, USA. He is currently pursuing the Ph.D. degree with the Delft University of Technology, Delft, The Netherlands, working on Class-D audio amplifiers.

AbstractThis paper reports a chopper Class-D audio amplifier that obtains high PSRR over the entire audio band. A chopping scheme is proposed to minimize intermodulation distortion between pulse-width modulation (PWM) and chopping in the audio band. A high-voltage chopper is developed to handle a 14.4 V PWM signal. Timing matching techniques are proposed to minimize chopping nonidealities which ensure good PSRR and THD. Fabricated in a 180nm BCD process, the prototype obtains a PSRR >109 dB at 217 Hz and >83.7 dB over the entire audio band. It also achieves −109.1 dB/−98 dB THD/THD+N and can deliver a maximum of 13 W to an 8-Ω load.

A 67mW D-Band FMCW I/Q Radar Receiver with an N-Path Spillover Notch Filter in 28nm CMOSAnirudh KankuppeImec / Free University of Brussels

BiographyAnirudh Kankuppe received the M.Sc. degree in Microelectronics and Microsystems from the Hamburg University of Technology, Hamburg, Germany in 2017. He was a Design Engineer with Cadence Design systems, India from 2012 to 2014. During his M.Sc., he was a recipient of Gifted Student Scholarship from TU Hamburg and National Merit Scholarship from Government of India in 2005. He is pursuing a Ph.D. in mm-wave and RF integrated circuits with Vrije Universiteit Brussel, Brussels, Belgium in collaboration with imec, Leuven, Belgium and currently working as a Researcher in the Advanced RF group at imec, Leuven, Belgium. His research is focused on mm-wave radar circuits, receivers and wireline ADCs.

AbstractA 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close-by large reflectors and the system power consumption is 67mW.




A Resolution-Adaptive 8mm2 9.98Gb/S 39.7pJ/B 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOSOscar CastanedaETH Zurich

BiographyOscar Castañeda received his M.Sc. degree in Electrical and Computer Engineering from Cornell University in 2020. He is currently a Ph.D. Candidate in the Integrated Information Processing (IIP) group at the Department of Information Technology and Electrical Engineering, ETH Zürich. In 2019, he received a Qualcomm Innovation Fellowship, as well as a Top 10 Best Student Presentation Award at SRC TECHCON. His research interests include digital signal processing, emerging computer architectures, and digital VLSI circuit and system design.

AbstractAll-digital millimeter-wave massive multi-user MIMO receivers enable extreme data-rates but require high power consumption. To reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband processing to the instantaneous communication scenario. The scalable 32-antenna, 65nm CMOS receiver occupies a total area of 8mm² and integrates ADCs with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.

A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band RejectionAmir BozorgUC Dublin

BiographyAmir Bozorg received the M.Sc. degree (with Hons.) in Microelectronics from Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran in 2012 and his Ph.D. in Electrical engineering from University College Dublin (UCD), Ireland in 2021. From 2016 to 2018, he was consulting for TSMC, Hsinchu, Taiwan, on a 16-nm ADPLL/RX for automotive radar applications. From 2017 to 2020 he was working as an R&D Scientist at S3 Semiconductor (now Dialog Semiconductor) Dublin, Ireland, where he was developing a K-band phased-array receiver. He has also raised venture capital from Atlantic Bridge Ventures, Dublin, Ireland, for commercializing an ADPLL-based phased-array transmitter for automotive radars. Since 2020 he has been working with Equal1 Labs Ltd. in Dublin, Ireland as a Research Scientist. He has authored or coauthored several IEEE journal papers, an upcoming book on discrete-time receivers, and holds four issued U.S. patents in the field of RF-CMOS design. His research interests include millimeter-wave/RF transceivers, discrete-time receivers, ADPLLs, and oscillators.

AbstractThis paper introduces a new architecture of a discrete-time charge-rotating low-pass filter (LPF) which achieves a high-order of filtering and improves its stop-band rejection while maintaining a reasonable duty cycle of the main clock at 20%. Its key innovation is a linear interpolation within the charge-accumulation operation. Fabricated in 28-nm CMOS, the proposed IIR LPF demonstrates a 1--9.9 MHz bandwidth programmability and achieves a record-high 120 dB stop-band rejection at 100 MHz while consuming merely 0.92 mW. The in/out-of-band IIP3 is +18.6/+26.6 dBm.




200-GS/S ADC Front-End Employing 25% Duty Cycle Quadrature Clock GeneratorGregory CookeUniversity of Toronto

BiographyGregory Cooke is a MASc. candidate at the University of Toronto under Prof. Sorin P. Voinigescu. He is working on high-bandwidth, high-sampling rate ADC frontend circuits for fiber-optic network applications in SiGe BiCMOS.

AbstractA 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25%duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.



A - SSCC 2021Industry Forum

Special Session 3 Industry Forum16:00-18:00 / Pearl Room

Trend, Hurdle, and Core Technologies For Next Generation High Performance Storage SystemChi-Weon YoonSamsung Electronics

BiographyChi-Weon Yoon is a Vice President of Technology in Samsung Electronics, Hwa-sung, Korea. He received M.S and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1999 and 2004 respectively. After receiving the degree, he joined Samsung Electronics and have worked for more than 16 years at Flash Memory Design Team. He holds over 110 global patents about non-volatile memory related circuits and cell operation algorithms. His current research interests include design of high performance and low cost cell-operation algorithms, analog circuits and high speed I/O circuits.

AbstractIt is obvious that high performance data storage system will be a key enabler in upcoming 4th industrial revolution. NAND flash memory and storage system design technologies also have evolved in terms of more bit density and higher performance to meet demands. But the technology is now facing several technical hurdles as the device technology continues to scale down and requirements from market is becoming harsher.In this talk, design challenges and solutions for implementing of high-performance data storage system will be covered. More Specifically, Issues and state-of-the-art technologies for next generation NAND flash memories will be discussed in detail, followed by an introduction of a frequency boosting chip solution for high speed and capacity storage system implementation.

Challenges and opportunities for in-memory/ near-memory computing and AI acceleratorsRam KrishnamurthyIntel Corporation

BiographyRam K. Krishnamurthy received the Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA, in 1997. He has been at Intel Corporation since 1997. He is currently a Senior Principal Engineer at Intel Labs, Hillsboro, OR, USA, where he heads the High-Performance and Low-Voltage Circuits Research Group. In this role, he leads research in high-performance, energy-efficient, and low-voltage circuits for next generation microprocessors, accelerators, and Systems-On-Chip (SoCs). He holds 200 issued patents and has published 200 papers and four book chapters on high-performance and energy-efficient circuits. He has received two Intel Achievement Awards, the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award, and the IEEE European Solid State Circuits Conference Best Paper Award. He is a Fellow of the IEEE.

AbstractThis presentation will highlight some of the emerging challenges and opportunities for sub-5nm process machine learning and AI technologies in the rapidly evolving IoT industry. With Moore’s law process technology scaling well into the nano-scale regime, future SoC platforms ranging from high performance cloud servers to ultra-low-power edge devices will demand advanced AI capabilities and energy-efficient deep neural networks. New and emerging IoT markets for autonomous vehicles, drones, and wearables require even higher performance at much lower cost while reducing energy consumption. Some of the prominent barriers to designing high performance and energy-efficient AI processors and SoCs in the sub-




5nm technology nodes will be outlined. New paradigm shifts necessary for integrating special-purpose machine learning accelerators into next-generation SoCs will be explored. Emerging trends in SoC circuit design for machine learning and deep neural networks, specialized accelerators for in-memory and near-memory computing, reconfigurable multi-precision matrix multipliers, ultra-low-voltage logic, memory and clocking circuits, AI inference accelerators including binary neural networks and associated on-chip interconnect fabric circuits are described. Future brain-inspired neuromorphic computing circuit design challenges and technologies will also be reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

A quantitative method to assess ROI of new silicon features in the context of SoC productHarry MuljonoIntel

BiographyHarry Muljono is a Principal Engineer in the Xeon Product Group at Intel Corporation, where he leads a back-end team for future generation processors. Harry started his career in 1992 as an IO designer for Intel’s i486-DX2 processor, followed by Pentium® II, Itanium® and successive Xeon® processors. He holds 50 US patents with more pending in the area of analog circuits/DFx and has co-authored 20 conference and IEEE journal papers. Harry received a B.S. in Electrical Engineering degree from University of Portland, Portland, OR and an M.Eng. in Electrical Engineering degree from Cornell University, Ithaca, NY.

AbstractA methodology is proposed to quantify a range of silicon metrics (power, area, performance, etc) in terms of SoC product cost. The result leads to a scoring index that can be used to assess ROI of specific silicon features in the context of SoC design process, assisting product decision making in a competitive market.

Computer Vision Hardware AcceleratorsKevin Ke XuSANECHIPS TECHNOLOGY CO., LTD

BiographyDr. Ke Xu got the B.S. and M.S. degrees in Electrical Engineering Department from Fudan University, Shanghai, China, in 2000 and 2003, respectively, and the Ph.D. degree with Outstanding Award from the Department of Electronic Engineering, The Chinese University of Hong Kong in 2007. He was also the Post-doctoral Research Fellow in Department of Electrical and Computer Engineering in University of Toronto in 2009.He served various senior roles as Staff/Algorithm Engineer, Chip Architect, Research Scientist, in different companies from startups to Fortune 500 such as IBM and Qualcomm, in China, Canada and USA. As key R &D member for Snapdragon 810/820/835 development in Qualcomm headquarter in San Diego, he was in charge of computer vision and video processing system design. He joined ZTE Microelectronics in 2015 as AI Chief Scientist and Director of Engineering, where he is in charge of AI, autonomous driving, and multimedia chip designs. He led a R&D group of more than 100 engineers with tens of technical experts. He developed several multimedia SoCs including smart phone, IPTV, IPC with advanced technology. He is also the Principal Researcher in State Key Laboratory of Mobile Network and Mobile Multimedia Technology. His expertise includes artificial intelligence, computer vision, virtual/augmented reality, computer architecture, multimedia technology, and VLSI design. He published more than 20 papers in international journals and conferences, and more than 20 patents holding.




AbstractComputer Vision (CV) is one of the most important research area of artificial intelligence. With the rapid development of deep neural networks, the computation for vision tasks become extremely complex and time-consuming. As the Moore’s Law slows down or even comes to an end, how to accelerate vision computing using domain specific accelerators is essential to both algorithm and hardware designers. This talk aims to provide an overview of CV hardware architectures, and the techniques being explored to efficiently accelerate the computation. It addresses and compares various state-of-the-art domain specific architectures and implementations.


SessionsWednesday, November 10


Session 14: C1L-A Performance Enhancement Techniques for Oversampled ADCsCrystal Ballroom 1

Chair 1 Jintae kim (Konkuk University) Chair 2 Nan Sun (Tsinghua University)

14.1 (3147) Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal Feedforward09:00-09:25 Beomsoo Park2, Changsok Han1, Nima Maghari2

1Marvell Semiconductor, Inc., United States; 2University of Florida, United States

14.2 (3050) A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR Over 1MHz BW09:25-09:50 Yanchao Wang2, Siladitya Dey2, Tao He2, Lukang Shi2, Jiawei Zheng2, Manjunath Kareppagoudr2, Yi Zhang2, Kazuki Sobue1, Koichi Hamashita1, Koji Tomioka1, Gabor Temes2

1Asahi Kasei Microdevices, Japan; 2Oregon State University, United States

14.3 (3123) A 0.9V 0.022mm² 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique09:50-10:15 Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho AhnSogang University, Korea

14.4 (3012) A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-Level Feedback Scheme10:15-10:27 Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang ZengFudan University, China

14.5 (3236) A 4th-Order CT I-DSM with Digital Noise Coupling and Input Pre-Conversion Method for Initialization10:27-10:39 Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak RyuKAIST, Korea

Session 15: C1L-B Secure & Resilient CircuitsCrystal Ballroom 2

Chair 1 Yoonmyung Lee (Sungkyunkwan University) Chair 2 Shuou Nomura (Kioxia Corporation)

15.1 (3218) A Current-Integrated Differential NAND-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security09:00-09:25 Jongmin Lee, Yoonmyung LeeSungkyunkwan University, Korea




15.2 (3025) An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss in 28nm CMOS09:25-09:50 Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun YangSoutheast University, China

15.3 (3122) An Adaptive Clocking System Using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS09:50-10:15 Dongin Kim2, Seonghwan Cho1


15.4 (3180) A Feedback Architecture of High Speed True Random Number Generator Based on Ring Oscillator10:15-10:27 Xin Cheng, Haowen Zhu, Xinyi Xing, Yunfeng Zhang, Yongqiang Zhang, Guangjun Xie, Zhang ZhangHefei University of Technology, China

15.5 (3119) A ±20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration10:27-10:39 Chun Yu Lin, Yu-Wei Huang, Tsung-Hsien LinNational Taiwan University, Taiwan

Session 16: C1L-C High-Power & Low-Power RF TechniquesCrystal Ballroom 3

Chair 1 Minjae Lee (Gwangju Institute of Science and Technology) Chair 2 Satoshi Tanaka (Murata Manufacturing Co. Ltd.)

16.1 (3100) A 3-to-78GHz Differential Distributed Amplifier with Ultra-Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process09:00-09:25 Jincheng Zhang1, Tianxiang Wu1, Yong Chen2, Junyan Ren1, Shunli Ma1

1Fudan University, China; 2University of Macau, China

16.2 (3142) A 24-to-32GHz Series-Doherty PA with Two-Step Impedance Inverting Power Combiner Achieving 20.4dBm Psat and 38%/34% PAE at Psat/6dB PBO for 5G Applications09:25-09:50 Masoud Pashaeifar, Anil Kumaran, Mohammadreza Beikmirza, Leo de Vreede, Morteza AlaviDelft University of Technology, Netherlands

16.3 (3103) 0.6V 8.1/0.2µW Ultra-Low-Power Logarithmic Power Detectors Employing Subthreshold MOS Transistors09:50-10:02 Keun-Mok Kim1, Hyun-Gi Seok2, Jeong-Il Seo1, Kyung-Sik Choi1, Sang-Gug Lee1


16.4 (3072) A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference

10:02-10:14

Dawei Ye1, Yuting Tu1, Wenjun Gong1, Rongjin Xu1, C. -J. Richard Shi2

1Fudan University, China; 2University of Washington, United States




16.5 (3141) -17 dBm Differential Charge Pump EPC Gen2 UHF RFID Demodulator for 9 dB Receive Sensitivity Boost10:14-10:26 Anand Savanth, Philex Fan, Sahan Gamage, Thanusree Achuthan, Fernando Garcia-RedondoArm Limited, United Kingdom; Arm Limited, Taiwan

16.6 (3148) A 2.85mm2 RF Transceiver in 40nm CMOS for IoT Micro-Hub Applications10:26-10:38 Zexue Liu, Yi Tan, Chen Xu, Heyi Li, Haoyun Jiang, Xinyu Bao, Dong Wang, Junhua Liu, Huailin

LiaoPeking University, China

Session 17: C1L-D High Performance MemoryPearl Room

Chair 1 Junyoung Song (Incheon National University) Chair 2 Shyh Shyuan Sheu (Industrial Technology Research Institute)

17.1 (3120) A 21Gb/s Duobinary Transceiver for GDDR Interfaces with an Adaptive Equalizer09:00-09:25 Jae-Woo Park2, Dongsuk Kang2, Injae Park2, Minsu Park2, Xuefan Jin2, Kyu-Dong Hwang1, Dae-

Han Kwon1, Jung-Hoon Chun3

1SK hynix Inc, Korea; 2Sungkyunkwan University, Korea; 3Sungkyunkwan University, SolidVue, Korea

17.2 (3080) A 24Gb/s/Pin PAM-4 Built Out Tester Chip Enabling PAM-4 Chips Test with NRZ Interface ATE09:25-09:50 Hyungmin Jin, Jindo Byun, Hyunyoon Cho, Hojun Yoon, Jin-Hee Park, Kyoungsoo Kim,

Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Sang-Hyun LeeSamsung Electronics, Korea

17.3 (3109) Energy-Efficient Charge Sharing-Based 8T2C SRAM In-Memory Accelerator for Binary Neural Networks in 28nm CMOS09:50-10:15 Hyunmyung Oh1, Hyungjun Kim1, Daehyun Ahn1, Jihoon Park1, Yulhwa Kim1, Inhwan Lee1, Jae-Joon Kim2

1Pohang University of Science and Technology, Korea; 2Seoul National University, Korea

17.4 (3099) A 16Kb Transpose 6T SRAM In-Memory-Computing Macro Based on Robust Charge-Domain Computing10:15-10:27 Jiahao Song, Yuan Wang, Xiyuan Tang, Runsheng Wang, Ru HuangPeking University, China

17.5 (3088) A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-Speed Interface10:27-10:39 Tongsung Kim, Anil Kavala, Hyunsuk Kang, Youngmin Jo, Jungjune Park, Kyoungtae Kang, Byung-Kwan Chun, Dong-Ho Shin, Dong-Su Jang, Byunghoon Jeong, Chi-Weon Yoon, Jinyub Lee, Jai Hyuk SongSamsung Electronics, Korea; Samsung Electronics, India


Wednesday, November 10IEEE Asian Solid - State Circuits Conference

A - SSCC 2021Convergence Workshop

Special Session 4 Convergence Workshop11:00-12:40 / Crystal Ballroom 1

Antenna-in-Package (AiP) TechnologyYueping ZhangNanyang Technological University, Singapore

BiographyYueping Zhang (M’03-SM’07-F’10) is a full Professor at Nanyang Technological University, Singapore, a Distinguished Lecturer of the IEEE Antennas and Propagation Society (IEEE AP-S), a Member of the IEEE AP-S Paper Award Committee, and a Fellow of IEEE.Prof ZHANG has published numerous papers, including two invited and one regular papers in the Proceedings of the IEEE and one invited paper in the IEEE Transactions on Antennas and Propagation. He received the Sergei A. Schelkunoff Prize Paper Award from the IEEE AP-S in 2012.Prof Zhang holds 7 US patents. He has made pioneering and significant contributions to the development of AiP technology. He received the John Kraus Antenna Award from the IEEE AP-S in 2020.His current research interests include the development of antenna-on-chip (AoC) technology for very large-scale antenna integration and characterization of chip-scale propagation channels at terahertz for wireless chip area network (WCAN).

AbstractAiP technology integrates an antenna or antennas with a radio or radar transceiver die (or dies) into a standard surface mount package. AiP technology well balances performance, size, and cost. Hence, it has been widely adopted by chip makers for highly integrated radios and radars. It is the antenna and packaging technology for the fifth generation (5G) cellular networks and beyond operating in the millimeter-wave (mmWave) bands. This talk will provide an overview of the development of AiP technology.

NTT’s IOWN Concept for enabling Smart WorldKatsushi ShindoNTT, Japan

BiographyKatsushi Shindo is currently leading NTT's R&D of Innovative Optical and Wireless Network (IOWN) and the realization of businesses that utilize IOWN as a manager of the IOWN Development Office.He is also the leader of the Reference Implementation Model Task Force, a joint Technical Working Group and Use Case Working Group of the IOWN Global Forum.He has worked as a bridge between technology and business since he joined NTT.His areas of expertise include video distribution, interactive video communication, IOT, and cloud/edge computing. Nowadays, he is exploring innovative ways to implement lower power, lower cost end-to-end systems using innovative technologies such as optical communications, disaggregated computing and AI.

AbstractIn the field of Cyber Physical System and Remote World, there will be a variety of attractive use cases in the Beyond 5G era.NTT has proposed the “IOWN concept”, which aims to develop and provide the next-generation IT infrastructure based on optical technology. For enabling such use cases, we have to manage the "data volume explosion," "communication latency," and "power consumption.” In this presentation, I will explain the IOWN concept proposed by NTT and the technical efforts to realize it, and also introduce the IOWN Global Forum, in which diverse members are collaborating to develop the IOWN



A - SSCC 2021Convergence Workshop

technologies and services.

Challenges and Opportunities of Dry-Contact EEG RecordingsPreben KidmoseAarhus University, Denmark

BiographyPreben Kidmose received the M.Sc. degree in engineering in 1998 and the Ph.D. degree in signal processing in 2001 from Technical University of Denmark. From 2001 – 2011 he was employed in the medical device industry (Widex and UNEEG medical). Since 2011 he has been at Aarhus University, Denmark, where he holds a position as professor in electrical and biomedical engineering at the Department of Electrical and Computer Engineering. Areas of research include: signal processing and machine learning methods for electrophysiological signals (in particular electroencephalography), biomedical sensors and wearable biomedical devices; biomedical electrical instrumentation; biomedical sensors; and system engineering/design of medical devices. He is a pioneer and leading researcher of ear-EEG and has (co-)authored more than 25 scientific papers related to the ear-EEG method.

AbstractNon-invasive recording of electrical signals from the brain (EEG) has a huge potential in wearable devices and is envisioned to open a wide field of new opportunities within consumer electronics and medical devices, where dry-contact electrodes is an attractive technology. This presentation overviews the state-of-the-art within wearable EEG recording devices, and discuss the technology challenges from an electrical instrumentation perspective, and exemplify with experiences from dry-contact ear-EEG research.



A - SSCC 2021Learn to Establish and Achieve Professionalism (LEAP)

Special Session 5 Learn to Establish and Achieve Professionalism (LEAP)11:00-12:40 / Crystal Ballroom 2

SAPEON X220: High-performance AI Accelerator for High-quality AI ServicesSoojung RyuVice president, SK Telecom, Korea

BiographySoojung Ryu is a Vice President at SK telecom. She is leading SAPEON development, which is the first Korean commercialized AI accelerator chip for server. Before joining SK telecom, she was a University-Industry Collaboration Professor at Seoul National University. She is currently a member of AI and SW Advisory Committee of Ministry of Science and ICT in Korea. She worked for Samsung Electronics from 2004 to 2018 as a processor architect after she received her Ph.D. degree in Electrical & Computer Engineering from Georgia Institute of Technology. She was a Samsung Corporate Vice President from Dec 2014 to 2018. She was leading a processor design and SW framework development for digital signal processor (Samsung Reconfigurable Processor) and Samsung Mobile Graphics Processing Unit. She served as a Board of Directors of Heterogeneous System Architecture (HSA) Foundation from 2017 to 2018 and also a Specification contributor from 2013 to 2018. Her current research focus is deep neural network accelerator design as well as the high performance processor solutions for various application areas.

AbstractThe increasing demand for high-quality AI-Based services has accelerated the development of dedicated AI-specific hardware. AI accelerator, SAPEON X220 design focuses on AI inference performance by maximizing compute-intensity without sacrificing the flexibility. High-density MAC array and programmable vector cores are orchestrated by dynamic scheduler to achieve a high overall performance. In this talk, I will show the case studies used in commercial services such as AI speaker and intrusion detection system as well as the potential services in Data Center including image enhancement. Service-oriented hardware design, software-development tools as well as AI-inference serving system are key factors to deliver the high-quality AI services in data center.

Navigating in the Vast Research TerrainYa-Chin KingProfessor, National Tsing Hua University, Taiwan

BiographyYa-Chin King was born in Taiwan, Republic of China. She received the B.S. degree in electrical engineering from National Taiwan University in 1992, the M.S. and PhD degree from University of California, Berkeley, in 1994 and 1999, respectively. She since joined the faculty of National Tsing Hua University at Hsinchu, Taiwan, and received the “2003 NTHU New Researcher Award”, the “Outstanding Youth Electrical Engineer Award” by the Chinese Institute of Electrical Engineer in 2007, the “Ta-You Wu Memorial Award” in 2008 by Taiwan’s National Science Counsel. She has published over 200 journal papers and 100 conference papers, which include more than 20 papers in IEEE International Electron Devices Meeting on novel memories technologies and innovative CMOS devices. Her research interests include: VLSI device reliability, CMOS image sensors and embedded memory technologies. She is currently a Professor of National Tsing Hua University, Institute of Electronics Engineering and Department of Electrical Engineering and Chair of NTHU Advanced Flash Memory Center.

AbstractEver since I started my career as the independent researcher, how to maintain “independent”, and finding resources to achieve once goals has always been a joggling act. For the past 20 years, after engaging and leading many different research projects,




I’ve found that nurturing connections/ resources and defining one’s role before venturing into a new field are most critical to each success. In this talk, I will share some of that experience in interdisciplinary work as case-studies for those who are at the beginning of their own path-finding adventure.

Biodegradable materials and electronicsLan YinProfessor, Tsinghua University, China

BiographyLan Yin is currently an Associate Professor in School of Materials Science and Engineering at Tsinghua University. She received her Bachelor’s degree from Tsinghua University in 2007 and Ph.D. degree from Carnegie Mellon University in 2011, both in Materials Science and Engineering. She worked as a posdoctoral research associate in Massachusetts Institute of Technology in 2011-2012 and University of Illinois Urbana-Champaign in 2012-2015. In 2015, she joined Tsinghua University with Thousand-Talent award. Her research interests are focused on biodegradable materials and electronics. In 2021, she has received the Excellent Young Scholar Award from the National Natural Science Foundation of China (NSFC) and is honored with the Chinese Materials Research Society (CMRS) the first prize of Science and Technology Award.

AbstractBiodegradable electronics is a new category of devices that can be completely degradable in physiological environments and therefore eliminate secondary surgeries for device retrieval and minimize associated infection risks. These devices could play a critical role in many therapeutic and diagnostic processes, including promoting tissue regeneration, probing neurotransmitters, etc. Here, we propose novel materials strategies and fabrication schemes that enable a fully biodegradable and self-electrified conduit device for sciatic nerve regeneration. Successful nerve regrowth and motor functional recovery are achieved in rodents. In another example, real-time detection of nitric oxide in biological systems based on degradable materials integrating wireless modules is realized, which could offer essential information for monitoring inflammatory responses. These works provide new routes for modulating and probing important biological activities that can be beneficial for healthcare.

What is a processor architect?Sugako OtaniProcessor Architect, Renesas Electronics, Japan

BiographySugako Otani is a chief processor architect at Renesas Electronics Corporation. Her current research focuses on application specific architecture ranging from IoT devices to automobile. She joined Mitsubishi Electric Corporation, Japan, in 1995. From 2005 to 2006, she was a Visiting Scholar at Stanford University. She received a Ph.D. in engineering from Kanazawa University in 2015. She serves VLSI circuit symposium, ISSCC, ESSCIRC, and Coolchips.

AbstractOptimizing across systems, applications, and processors are becoming increasingly important to provide more powerful computing solutions. Processor architects can contribute to these technologies by having a deep understanding of both software and hardware. In addition, semiconductor development is a large-scale project and requires a collaborative team effort to be successful. Processor architects also play an essential role in the management of the project. What are the functions of a processor architect?




Next-generation biomedical interfaceHyunjoo Jenny LeeProfessor, KAIST, Korea

BiographyHyunjoo Jenny Lee received the B.S. degree in Electrical Engineering and Computer Science, and the M.Eng. degree in Electrical Engineering from the Massachusetts Institute of Technology (MIT), Cambridge, MA, in 2004 and 2005, respectively, and the Ph.D. degree in Electrical Engineering from Stanford University, Stanford, CA, in 2012. From 2013-2015, she was a Research Scientist at the Brain Science Institute, Korea Institute of Science and Technology, Seoul, Korea. In 2015, she joined the School of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST) where she is now an Associate Professor. Her current research focuses on Bio-MEMS including neural interface, ultrasound transducers, epidermal electronic, biosensors, and brain stimulation systems.

AbstractMiniaturized devices based on Microelectromechanical Systems (MEMS) offer competitive advantages over conventional bio/medical tools for neuroscience applications, such as small size, low cost due to batch fabrication, and CMOS compatibility. For example, miniaturized devices such as neural probes and ultrasound transducers have opened up new means for neuroscientists to observe and control our brain. This talk will discuss the use of ultrasound for neuromodulation with a focus on miniaturized ultrasound transducers. The functionalities and potential applications of these devices will be discussed.

My journey from Graduate Student, Professor, to C.E.O.Yu-Jiu WangChairman & CEO, Tron Future Tech. Inc., Taiwan

BiographyYu-Jiu Wang received B.S. degree in E.E. from National Taiwan University, and MS/Ph.D. degree also in E.E. from California Institute of Technology. Dr. Wang is an expert on very-large-scale radio frequency design and array radar/communication system design. He joined the Electronics Engineer Department in National Chiao Tung University (NCTU) after Ph.D., and was promoted to a tenure associate professor. Dr. Wang left NCTU in Feb. 2019 and become the chairman and C.E.O. of Tron Future Tech Inc., headquartered in Hsinchu, Taiwan.Tron Future Tech Inc. delivered total solutions based on state-of-the-art ultrathin radar and communication systems to aerospace and defense industries etc. Notably, Tron Future Tech Inc. is delivering various Gbps multibeam phased array (0.25~1m2 X~Ka-band aperture) communication satellite payloads and Satellite Phased-Array Synthetic Aperture Radar (5m2 X-band aperture) payloads for Taiwan’s Space Program Phase III. Dr. Wang is a two-time International Physics Olympiad silver medal winner. He received national industrial innovation award in 2015. He is also a member of IEEE Solid-State Society, Microwave Theory and Technique Society, Circuits and Systems society, Aerospace and Electronic Systems, Geoscience and Remote Sensing, Antenna and Propagation, and reviewers for various conference. He is a director of Taiwan Space Industry Development Association.

AbstractI will briefly present my career from graduate student in Caltech, professor of National Chiao Tung University, to the C.E.O. of Tron Future Tech Inc.




Session 18: C2L-A Clock Generation & Envelope TrackingCrystal Ballroom 1

Chair 1 Hyungil Chae (Konkuk University, Korea) Chair 2 Milin Zhang (Tsing Hua Univ, China)

18.1 (3242) A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE Over 10K Cycles and ±0.3% Thermal Stability Using Frequency-Error Feedback Loop14:00-14:25 Nandish Mehta, Stephen Tell, Walker Turner, Lamar Tatro, Giant Goh, Tom GrayNVIDIA, United States

18.2 (3039) A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS14:25-14:50 Yizhuo Wang, Tenghao Zou, Bowen Chen, Shujiang Ji, Chao Zhang, Na YanFudan University, China

18.3 (3166) A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement14:50-15:15 Dong-Hyun Yoon2, Dong-Kyu Jung1, Kiho Seong1, Tae-Hyeok Eom1, Jae-Soub Han1, Ju Eon Kim2, Tony Tae-Hyoung Kim2, Kwang-Hyun Baek1

1Chung-Ang University, Korea; 2Nanyang Technological University, Singapore

18.4 (3078) A 2.7W AC-Coupled Hybrid Supply Modulator Achieving 200MHz Envelope-Tracking Bandwidth for 5G New Radio Power Amplifier15:15-15:40 Peng Xu, Xueli Zhang, Peng Cao, Tingting Wei, Zhiguo Tong, Jiawei Xu, Zhiliang HongFudan University, China

Session 19: C2L-B FPGA Design for Emerging ApplicationsCrystal Ballroom 2

Chair 1 Ji-Hoon Kim (Ewha Womans University) Chair 2 Yong-Pan Liu (Tsinghua University)

19.1 (3149) A Computationally Efficient, Hardware Re-Configurable Architecture for QRS Detection and ECG Authentication14:00-14:25 Weihong Yan, Yuxin Ji, Ce Ma, Lining Hu, Yang Zhao, Yongfu Li, Guoxing Wang, Yong LianShanghai Jiao Tong University, China

19.2 (3191) FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks14:25-14:50 Changhyeon Kim2, Dongyoung Rim2, Jeongwon Choe2, Dongyun Kam2, Giyoon Park1, Seokki

Kim1, Youngjoo Lee2

1Electronics and Telecommunications Research Institute, Korea; 2Pohang University of Science and Technology, Korea




19.3 (3206) A 139 fps Pixel-Level Pipelined Binocular Stereo Vision Accelerator with Region-Optimized Semi-Global Matching14:50-15:15 Pingcheng Dong2, Zhuoao Li2, Zhuoyu Chen2, Ruoheng Yao2, Huanshihong Deng2, Wenyue Zhang2, Yangyi Zhang2, Lei Chen2, Chao Wang1, Fengwei An2

1}Huazhong University of Science and Technology, China; 2Southern University of Science and Technology, China

19.4 (3175) Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections with <0.83% Bit-Error Rate15:15-15:27 Chongyao Xu, Jieyun Zhang, Man-Kay Law, Yang Jiang, Xiaojin Zhao, Pui-In Mak, Rui Paulo MartinsUniversity of Macau, China; University of Macau, Macau

19.5 (3165) A 45.4x~221.2x Latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network15:27-15:39 Ya-Yun Hou, Shao-Peng Lai, Hung-Kun Chang, Yun-Wen Lu, Hsie-Chia ChangNational Yang Ming Chiao Tung University, Taiwan

Session 20: C2L-C Emerging Circuits & Systems for Biomedical ApplicationsCrystal Ballroom 3

Chair 1 Shuenn-Yuh Lee (National Cheng-Kung University) Chair 2 Joonsung Bae (Kangwon National University)

20.1 (3007) A 28.2µW Neuromorphic Sensing System Featuring SNN-Based Nearsensor Computation and Event-Driven Body-Channel Communication for Insertable Cardiac Monitoring14:00-14:25 Yuming He2, Federico Corradi2, Chengyao Shi1, Ming Ding2, Martijn Timmermans1, Jan Stuijt2, Pieter Harpe1, Ilja Ocket2, Yao-Hong Liu2

1Eindhoven University of Technology, Netherlands; 2IMEC, Netherlands; 2IMEC, Belgium

20.2 (3013) A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC Based on Continuous-Time Dynamic-Zoom ΔΣADC with Automatic AFE-Gain Control14:25-14:50 Yoontae Jung2, Soon-Jae Kweon3, Hyuntak Jeon1, Taeju Lee2, Injun Choi2, Kyeongwon Jeong2, Mi Kyung Kim2, Hyunjoo Jenny Lee2, Sohmyung Ha3, Minkyu Je2

1Agency for Defense Development, Korea; 2KAIST, Korea; 3New York University Abu Dhabi, U.A.E.

20.3 (3241) A Neural Stimulation IC Based on a Reconfigurable Current DAC with In-Situ Neural Recording Function for Cochlear Implant Systems14:50-15:15 Woojin Ahn4, Doohee Kim5, Jonghyeok Park3, Jeong Hoan Park2, Taeju Lee1, Kyeongwon Jeong1, Kyou Sik Min3, Hoseung Lee3, Minkyu Je1

1}KAIST, Korea; 2Samsung Electronics, Korea; 3TODOC Co. Ltd, Korea; 4TODOC Co. Ltd, KAIST, Korea; 5TODOC Co. Ltd, Seoul National Hospital, Korea




20.4 (3137) An 8.7µj/class. FFT Accelerator and DNN-Based Configurable SoC for Multi-Class Chronic Neurological Disorder Detection15:15-15:27 Zain Taufique2, Bingzhao Zhu1, Gianluca Coppola3, Mahsa Shoaran1, Wala Saadeh2, Muhammad Awais Bin Altaf2

1École Polytechnique Fédérale de Lausanne, Switzerland; 2Lahore University of Management Sciences, Pakistan; 3Sapienza University of Rome Polo Pontino, Italy

20.5 (3246) A Wirelessly-Powered 10Mbps 46-pJ/b Body Channel Communication System with 45% PCE Multi-Stage and Multi-Source Rectifier for Neural Interface Applications15:27-15:39 Byeongseol Kim, Beomjin Yuk, Joonsung BaeKangwon National University, Korea

Session 21: C2L-D Wireline Transceiver TechniquesPearl Room

Chair 1 liu peng (Zhejiang University) Chair 2 Jung-Hoon Chun (Sungkyunkwan University)

21.1 (3095) A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS14:00-14:25 Pen-Jui Peng1, Hsiang-En Huang3, Wei-Chien Huang3, Po-Lin Lee3, Ming-Wei Lin2, Ying-Zong

Juang2, Sheng-Hsiang Tseng2

1National Tsing Hua University, Taiwan; 2Taiwan Semiconductor Research Institute, Taiwan; 3Yuan Ze University, Taiwan

21.2 (3188) A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector14:25-14:50 Yu-Ping Huang, Yi-Wei Chang, Wei-Zen ChenNational Yang Ming Chiao Tung University, Taiwan

21.3 (3023) A 48 Gb/s PAM4 Receiver with Baud-Rate Phase-Detector for Multi-Level Signal Modulation in 40 nm CMOS14:50-15:15 Kwangho Lee2, Woosong Jung2, Haram Ju1, Jinhyung Lee3, Deog-Kyoon Jeong2

1Korea Electronics Technology Institute, Korea; 2Seoul National University, Korea; 3SK hynix Inc, Korea

21.4 (3153) A 64 Gb/s 2.09 pJ/B PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS15:15-15:40 Hyungrok Do, Jung-Woo Sull, Seunghyun Lee, Kwangho Lee, Deog-Kyoon JeongSeoul National University, Korea



A - SSCC 2021Latest New & Hot Issue Forum

Special Session 6 Latest New & Hot Issue Forum16:00-18:00 / Crystal Ballroom 1

On-Chip Generation and Detection of THz Waves with Orbital-Angular MomentumRuonan HanMIT

BiographyRuonan Han received his B.S. degree from Fudan University in 2007 and Ph.D. degree from Cornell University in 2014. He is now a tenured associate professor at MIT. His research group focuses on RF-to-photonics integrated systems for spectroscopy, metrology, imaging, quantum sensing/ processing, broadband/secure communication, etc. He is an associate editor of IEEE Trans. Very-Large-Scale Integration System and IEEE Trans. Quantum Engineering, and also serves on the Technical Program Committee of IEEE RFIC Symposium and the Steering Committee of IEEE International Microwave Symposium. He and his students have won three best student paper awards (2012, 2017 and 2021) in the RFIC symposium. He is the IEEE MTT-S Distinguished Microwave Lecturer in 2020-2022, and the winner of the Intel Outstanding Researcher Award in 2019 and the National Science Foundation CAREER Award in 2017.

AbstractInformation can be encoded into many different properties of an electromagnetic wave, including not only frequency, intensity, phase and polarization, but also certain helical phase distribution of its wavefront, namely the orbital angular momentum or OAM. Here we report the first chip-based demonstration (at any frequency) of a transceiver front-end that transmit and receives OAM waves. The CMOS chip consists of eight reconfigurable 0.31THz modulator/detector units, with integrated patch antennas placed in a uniform circular pattern. A full-silicon OAM link using a pair of such chips is demonstrated. The transmitted wave, controlled by an input data stream, can switch among the m=0 (plane wave), m=+1 (left handed), m=-1 (right handed) and superposition m=(+1)+(-1) states. Through such dynamic bit-to-OAM mode switching and the highly-angle sensitive OAM transmission, the link showcases the potential applications in the high-security, one-way transmission of encryption keys.

Cryogenic CMOS Controller for Large-Scale Quantum Computers: from Specifications to Implementation and Qubit TestingMasoud BabaieDelft University of Technology

BiographyMasoud Babaie is currently a tenured Assistant Professor at the Delft University of Technology, Delft, The Netherlands. His research interests include RF/millimeter-wave integrated circuits for wireless communications and cryogenic electronics for quantum computation.Dr. Babaie currently serves as a technical program committee (TPC) member of the ISSCC and ESSCIRC conferences. He was a co-recipient of the 2019 IEEE ISSCC Best Demo Award and the 2020 IEEE ISSCC Jan Van Vessem Award. In 2019, he received the Veni Award from the Netherlands organization for scientific research.

AbstractA fault-tolerant quantum computer operates at deep cryogenic temperatures (typically 20-100mK) and requires massive yet very precise control electronics for the manipulation and read-out of individual quantum bits (qubits). The most complex state-of-the-art quantum computer (with 53 qubits) requires tens of bulky custom-made electronic modules operating at room temperature and connected to cryogenic qubits via hundreds of coaxial cables. However, this approach is not practical




for implementing fault-tolerant quantum computers with millions of qubits due to the utter interconnect complexity, poor system scalability, and reliability. A better alternative would be to integrate the qubits and the control electronics on the same die or package and operate them at the same temperature. Toward this goal, electronics able to operate at cryogenic temperatures in close proximity to the qubits must be developed.In this presentation, the essential functionalities required to control spin qubits and system-level specifications of the electronics are firstly discussed. Then, we review the characteristics and behavior of CMOS active and passive components at cryogenic temperatures. By exploiting the developed CMOS and qubit models, we develop the block diagram and circuit schematic of a digitally-intensive wideband transmitter capable of operating at 3K and controlling 32 frequency-multiplexed qubits. It also offers waveform shaping flexibility, minimum execution latency, and straightforward integration in the existing quantum computing stack. Finally, the cryogenic controller is used to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

A CMOS Annealing Machine to Solve Combinatorial Optimization ProblemsMasanao YamaokaHitachi, Ltd.

BiographyMasanao Yamaoka received the B.E., M.E., and Ph. D degrees in electronics and communication engineering from Kyoto University, Kyoto, Japan, in 1996, 1998, and 2007, respectively.In 1998, he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, where he was engaged in the research and development on low-power embedded SRAM and CMOS circuits. Since 2012, he has been engaged in the research of new-paradigm computing using CMOS circuits.

AbstractTo achieve the SDGs by IT technologies, various data processing technologies to solve various problems are required. One of the important processes is optimization to decide control parameters. For the optimization processing, new computing technologies are necessary to efficiently handle combinatorial optimization problems. The dramatic development of a general-purpose computers such as processors will be saturated in the near future due to the slow-down of the semiconductor scaling, and domain specific computing is expected to be the promising technologies. The CMOS annealing machine we have proposed is a new computing technology whose function is specialized only to combinatorial optimization processing. In this talk, the outline of the CMOS annealing machine is presented. The CMOS annealing is now commercializing phase, and its use cases in the real applications are also presented.

A Fully Implanted BMI (Brain-Machine Interface)Dongjin SeoNeuralink Corporation

BiographyDJ Seo received his B.S in electrical engineering from California Institute of Technology (Caltech) with a focus on integrated circuit design for next-generation wireless communication systems and M.S. and Ph.D. from UC Berkeley for his work on ultrasonic wireless neural implant technology called neural dust. After his graduation, he helped start Neuralink, where he is currently VP of implant. His team works on all aspects of implant, from design and fabrication of electrode arrays that can be manipulated by surgical robot to on-chip neural signal processing engine, wireless data telemetry, powering, and hermetic packaging.




AbstractBrain-machine interfaces (BMIs) hold promise for the restoration of sensory and motor function and the treatment of neurological disorders. Neuralink is building a fully implantable, minimally invasive BMI to enable a wider adoption of such clinical BMIs. This talk will describe the components of this BMI (including micron-scale electrodes, integrated electronics with wireless power and data telemetry, and a robotic neurosurgical device), how they address the key engineering challenges in building a scalable BMI, and applications of this technology.



A - SSCC 2021Rising Star Express(RiSE) Forum

Special Session 7 Rising Star Express(RiSE) Forum16:00-18:00 / Crystal Ballroom 1

Analog to the Rescue? Analog Deep Learning Accelerator Aspects and ChallengesKentaro YoshiokaAssistant Professor, Keio University, Japan

BiographyKentaro Yoshioka received his BS, MS, Ph.D degrees from Keio University, Japan. Currently, he is an Assistant Professor at KeioUniversity. He worked with Toshiba during 2014-2021, developing circuitry for WiFi and LiDAR SoCs. During 2017-2018, he had been a visiting scholar at Stanford University, exploring efficient machine learning hardware and algorithms. He was the recipient of ASP-DAC 2013 Special Feature Award, the A-SSCC 2012 Best Design Award, and 1st place winner of Kaggle 2020 PANDA Challenge.

AbstractLow-powered Deep Learning Accelerators (DLAs) are required for battery driven IoT devices. Significant research efforts have been poured into digital-based DLAs, improving the efficiency in order of magnitude-but can we expect even more dramatic improvements? DNNs can tolerate low-precision operations; another 10x efficiency improvements are possible by leveraging analog-based approximate computing.In this talk, we will discuss the advantages and challenges of bit-serial analog DLAs, also known as computing in memory, and phase-based bit-parallel analog DLAs.

Circuit and System Innovations Towards Robust and Secure Millimeter-Scale Bioelectronic ImplantsKaiyuan YangAssistant Professor, Rice University

BiographyKaiyuan Yang received his B.S. in Electronic Engineering from Tsinghua University, China, in 2012, and his Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, MI, in 2017. His Ph.D. research was recognized with the 2016 IEEE Solid-State Circuits Society (SSCS) Predoctoral Achievement Award.He has been an Assistant Professor of ECE at Rice University, USA, since 2017. His research interests include digital and mixed-signal circuits for secure, intelligent and low-power microsystems, hardware security, and circuit/system design with emerging devices. Dr. Yang received a number of best paper awards from top-tier conferences in multiple fields, including the Best Paper Award at the 2021 IEEE Custom Integrated Circuit Conference (CICC), Distinguished Paper Award at the 2016 IEEE International Symposium on Security and Privacy (Oakland), Best Student Paper Award (1st place) at the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), and the Best Student Paper Award finalist at the 2019 IEEE Custom Integrated Circuit Conference (CICC).

AbstractMillimeter-scale bioelectronic implants promise transformative applications in medicine, health, and scientific research. This talk will overview our recent progress on unconventional hardware designs to enable several critical properties and functions for bio implants, satisfying the unprecedented power, volume, and wireless requirements. More specifically, we blur digital and analog domains in circuit and system designs, to push the frontier in safe and robust power delivery, low-power yet high-performance analog blocks, and hardware security primitives to protect these extremely miniaturized devices.




Power Management Integrated Circuits using Switched Inductor/Capacitor ConvertersSe-Un ShinAssistant Professor, UNIST, Korea

BiographySe-Un Shin received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, South Korea, in 2013, and the integrated master’s and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2018. From 2018 to 2019, he was a Postdoctoral Associate with the University of Michigan, Ann Arbor, MI, USA. From 2019 to 2020, he was a Faculty with the Department of Display Engineering, Dankook University, Cheonan, South Korea. Since 2021, he has been with Electrical Engineering in UNIST, where he is currently an Assistant Professor. His current research interests include analog integrated circuit design and power management IC design, energy harvesting, battery charger, wireless power transfer systems, switched capacitor/inductive converters, and hybrid converter topology. Prof. Shin was a recipient of the Bronze Prize and Silver Prize in the 22nd and 24th Human-Tech Thesis Prize Contest from Samsung Electronics, in 2016 and 2018, respectively, and the IEEE Solid-State Circuits Society Predoctoral Achievement Award in 2018.

AbstractIn this presentation, dual-path converters are presented for achieving high power efficiency in the mobile power management ICs (PMICs). Adopting a hybrid structure using one inductor and one flying capacitor, the proposed converters supply a load current via two parallel paths, relieved intrinsic problems of the conventional converter topology. The proposed converters can achieve a high power efficiency and thus also reduce the heating problem, which is another critical issue in the mobile set. Moreover, it can shrink the volume of the PMIC set with a low manufacturing cost.

Millimeter-wave and Terahertz Multifunctional CMOS Transceiver for Future Sensing/Communication Fusion-mode Wireless SystemWei DengAssociate Professor, Tsinghua University, Beijing, China

BiographyWei Deng received the B.S. and M.S. degrees from University of Electronic Science and Technology of China, China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. From 2013 to 2014, he was a Post-Doctoral Researcher with the Tokyo Institute of Technology. From 2015 to 2019, he was with Apple Inc., Cupertino, USA, working on mm-wave and mixed-signal IC design for wireless transceivers and A-series processors. Since 2019, he has been a faculty member with Tsinghua University, China. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and system. He currently serves as a TPC Member for ISSCC, VLSI, and ESSCIRC.

AbstractRecent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. In this talk, a D-band radar/communication fusion-mode transceiver in 28nm CMOS technology, which is suitable for performing high-resolution range measurement and high data rate wireless transmission on one single chip, is introduced for future radar-communication joint wireless system.




FPGA-based Energy-Efficient Reconfigurable Convolutional Neural Network AcceleratorKa-Fai UnAssistant Professor, University of Macau

BiographyKa-Fai Un received the B.Sc. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2007, and the M.Sc. degree in electrical and electronics engineering and the Ph.D. degree from the University of Macau (UM), Macau, in 2009 and 2014, respectively. Dr. Un was a Post-Doctoral Researcher and a Lecturer (Macao Fellow) in 2014 and 2015, respectively. He is an assistant professor since 2018 all with the State Key Laboratory of Analog and Mixed-Signal VLSI, UM. He was on leave from UM and was a visiting Post-Doctoral Researcher with the School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland, from 2017 to 2018. His research interests are analog and RF circuit design, analog artificial intelligence circuit design and digital neural network accelerator.

AbstractThe computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN) accelerator. The memory access power is as significant as the computational power in a neural network accelerator. Reducing repeated memory accesses to input activations/weights is crucial for designing energy- efficient accelerators. In this presentation, we summarize the considerations for designing energy-efficient FPGA-based accelerators. Recent accelerator research conducted by our research group is introduced to demonstrate the importance of the dataflow management for reducing memory accesses. Further methods which can increase the computational efficiency are also introduced.

a - sscc 2021

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