ˇ ˘ #)*) ˚)+ ,& · • all the calculations should be made in the observation book. specimen...

!"#$

%"&'(

#)*) )+,&

-)(.....................................

/-.....................................

%)01..................0 ...........

PDF processed with CutePDF evaluation edition www.CutePDF.com

http://www.cutepdf.com

#) (( 0) #)*

'

*)2

34)56() -)7))8)

'2)) 940)

1) ) 8)2)%

4)8 ):

;8)<

)14

1

=>)?

@""

!

"! ##

# ! " #

$%

## ! & # $#

! $&%

' ($# ! #!$$

!#%

$ ' ) *) +$

,%

!- ! $ ) , #!

"$."$%

/###$

$# $ ! % 0

1!$$)0,0 2%

! $#34$$3!!

#' $%

o $# "

$$ !! $ 5!

"$%

o

$$ '

o 5#5!! # &

#$%

o $$ ' !

%

!" # $!%

+)!

• , ' # $

$$ #! $%

• , !! 5 # !

%

• " ' # #

%

• 4$$ '& $

$%

$%

$+)!

• ##&'!$$!!

$$!!%

• 4 $ $

!$)))$)%

• * !! ! #$

$$$

• 6#!$) '3$ $ ,#

$%

• *## %

• 3$$)''%

• /&#)$$%

• 3!!(!(!&'!#!%

!"#$$

%&& '

!"

#$%!!&'()"* +!,'*

-!&$%!!&'$ +!, !"

./!,!!,0&!!&,/!12/3

!,0&$

./4%3!3!)5/&&!/0!,0$

./!6783&80!!3/30!&$

./4940:,0./!&!&/6/:!;0

,//&83!;/!//!&0/,:<$

./=/!!.!/0:,0$

./ !&!!& &6!/-,$

.,!%&!,0&/=&!0!,0&/!$

! ,0&,&!/!(>-?!!$

" >@;,&!/ * (<!,&!$

./7A-(>- +$

.7/!/7!&! &!<(<$

>@;;3/%$

()*+,

!"#

!"

# !$ !

%&##!'

$ # #(# )*

##! !+ #!" ,!" -" " "

$!!'

. $ ##! /// !+ ! !

! '

! !$!" ! %.

.'

-!.0#!#!$!##!$'

$%#

#!$!!"

1(2#!$!$.$ #

$!$!+'

1(2#3,3%"%..

1(2##!!##!$%

3+$$$ ##!'

-$!.0##!"&4,"54,"-

!!$!'

6##!&"$///

#$$!7#!'

• Student should come with thorough preparation for the experiment to be

conducted.

• Student should take prior permission from the concerned faculty before

availing the leave.

• Student should come with proper dress code and to be present on time

in the laboratory.

• Student will not be permitted to attend the laboratory unless they bring

the practical record fully completed in all respects pertaining to the

experiment conducted in the previous class.

• Student will not be permitted to attend the laboratory unless they bring

the observation book fully completed in all respects pertaining to the

experiment to be conducted in present class.

• Experiment should be started conducting only after the staff-in-charge

has checked the circuit diagram.

• All the calculations should be made in the observation book. Specimen

calculations for one set of readings have to be shown in the practical

record.

• Wherever graphs to be drawn, A-4 size graphs only should be used and

the same should be firmly attached in the practical record.

• Practical record and observation book should be neatly maintained.

• Student should obtain the signature of the staff-in-charge in the

observation book after completing each experiment.

• Theory related to each experiment should be written in the practical

record before procedure in your own words with appropriate references.

Question bank 59

Viva questions 60

Appendix

!

"#$" %

& ' # $"

% ( )

* +',

!(-

. ,(!! %

/0-(1 &

#+/+ / .% &

,23+3 &

( 4 &!

!"

# $

%

&

'

(

)

*

+

,

-.

!"

#!

#!

!" ##$##$#####

%&'!%(' )%*%!

$ % &'( )*+,+, +*&,+%

-*#*!

+,

-.

-*#* .!

+ *+ % #

/%&++

/*+%+ 0

%1+ /

-

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&' &*,,+4'"5( *& ,,167/'

6869,+/# **&' &*,,+4'"5(

*& %++)67'6869,+/#

-+)*1,+)**# 7*#9%-&&*

$)*+&%&& ++

*& ,6)& &)6

#!

,5(: 8

.;

#!

!" ##$##$#####

/!/%*0!%12%3!(%))(

4 (

$ %<)),&&+,+)%,+4',&&

+,

-.

-*#* .!

+ *+ % #

*+ =;

/*+%+ 0%

1+ /

-

,

)2)*34*,+)+1+2%

+ )1)+ %+#

>&*1+**&'1) -? )-*+*#,

*#*

@ ) ; 2 ++ 7>A6& ,+*9 %

)&&<+ ))*&,+%)& 8

-+)/1*%- +),+4'

6+,'),+4'1)) % &

#!

5

,"5(

.;

#!

24 (

$ %BCA+ %&&+,+)%,+4',&&

+,

-.

-*#* .!

+ *+ % #

*+ =;

/*+%+ 0%

1+ /

-

,

)2)*34*,+)+1+2%

+ )1)+ %+#

>&*1+**&'1) -? )-*+*#,

*#*

@ ) ; 2 ++ 7>A6& ,+*9 %

)&&<+ ))*&,+%)&

-+)/1*%- +),+4'

6+,'),+4'1)) % &

#!

6

: <A 79

#,,,+4' 5Hf KHz=

) 1

10

101.586 1 17.064

f

V

A

f

A

A

Ri A

R

Assume R K

KR K

R

= +

= Ω

Ω= + = Ω

1 1 2 2

1)

2Hii Thecutoff frequency f

R C R Cπ=

,

$),537π9

.;$)

( )3 6

1 1318 330

2 2 5 10 0.1 10H

R Use stdf C X X X Xπ π −

= = = Ω Ω

/ D0.;

#!

!"5 ##$##$#####

%%(!2&!0(/%7!/ ) *%)!

4 )8 *

$ E*+ '),+4'+*,+ +

+1+)&1*,&+,+)% %*,

+,

-.

-*#* =!

+0*+ *+ % #

-F<+ #

/%&++ #

/*+%+ F%

1+#

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&' 1 %& , *& 67<#<9 * &% ,+ %&

%++

6+' ) * ,+4' 1 ) ++* % *

*&

$&)+ % *&%+*),,75(93%7 A9

,

G% ) * %& *& : 1 ) *

*& ),,,+4',5 ,5$) ,,+)%

A,5 ,51&&%)+&&,,

#!

6HHHHHHHHHHHHHHH6

/9 77 :7$73,2:;)

3

3dB

-40dB/dec

Gain (dB)

FH f (Hz)

#!

,,,+4':,5$)+&HHHHHHHHH

,,,+4':,5<+&HHHHHHHHH

< %$)+&HHHHHHHHH

< %<+&HHHHHHHHH

&&,,$)+& HHHHHHHHH

&&,,<+& HHHHHHHHH

#!

<

: <A 79

#,,,+4', 25(

) 1

10

101.586 1 17.064

f

V

A

f

A

A

Ri A

R

Assume R K

KR K

R

= +

= Ω

Ω= + = Ω

5Lf KHz=

1 1 2 2

1)

2Lii Thecutoff frequency f

R C R Cπ=

,

$),37π9

.;$)

/: I

D0.;

#!

24 / *

$ E*+ '),+4'+*,+ +

+1+))%)*,&+,+)% %*,

+,

-.

-*#* =!

+0*+ *+ % #

-F<+ #

/%&++ #

/*+%+ F%

1+#

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&' 1 %& , *& 67<#<9 * &% ,+ %&

%++

6+' ) * ,+4' 1 ) ++* % *

*&

$&)+ % *&%+*),,75(93%7 A9

,

G% ) * %& *& : 1 ) *

*& ),,,+4', ,$) ,,+)%

A, ,1&&%)+&&,,

#!

6HHHHHHHHHHHHH6

/9 77 :7$73,2:;)

3

3dB

+40dB/dec Gain(dB)

fL f (Hz)

#!

,,,+4':,$)+&HHHHHHHHH

,,,+4':,<+&HHHHHHHHH

< %$)+&HHHHHHHHH

< %<+&HHHHHHHHH

&&,,$)+& HHHHHHHHH

&&,,<+& HHHHHHHHH

#!

,=

Design 4 bit R-2R DAC for an output voltage, V0 = 5V,

when the input is (10)d [i.e., (1010)b].

D3 D2 D1 D0

( 10 )10 = ( 1 0 1 0 ) 2

#!

!"6 ##$##$#####

62%%3%)()(3(7!!

4 3%8

$ % ) ,+# > % *#* ,+ %%& 1) % )

*&%,++&,+'

+,

-.

.!

+ *+ % #

G&+ #

A+ F%1+ # /

,

)2)*34*,+)+1+2%

+ )1)+ %+#

>%&* %> :>:>:> ++* %&%*

&%6+ %&+

$&)+ %0*&)%+*),636

>>>0> ++'*

6)&%*

A+'*>7 9 JC'%)3*%+

JC'%K6

%6

%F6

#!

(

7

2.% ($

7>4

($

7>4

5 ;

!

8

,?

Design 4 bit R-2R DAC for an

when the input is (10)

D3 D2

( 10 )10 = ( 1 0 1 0 )

2R DAC for an output voltage, V0 = 5V,

when the input is (10)d [i.e., (1010)b].

D1 D0

= ( 1 0 1 0 ) 2

#!

#!

24 3%%8@, =

$ % ) ,+# > % *#* ,+ %%& 1) % )

*&%,++&,+'

+,

-.

.!

+ *+ % #

G&+ #

A+ F%1+ # /

,

)2)*34*,+)+1+2%

+ )1)+ %+#!

>%& * % > : >: >: > ++* % &%

*&%6+ %&+

$&)+ %0*&)%+*),636

#!

(

7

2.% ($

7>4

($

7>4

5 ;

!

8

#!

A

2I

;2I

7 7

#!

!"< ##$##$#####

!B%!3(%**!!%(

4 ,,

$ ')* %,+% +%*#*

+,

-.

-*#* µ!

+ *+ % #

G&+

/*+%+ F%1+ /

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&'*,+</#7'669 </#7/'6 69

-+)*,+&#+*#***#

C

2I

#3

L

2I

0

3

L

I

#!

#!

24 %

$ ')* %,%++%*#*

+,

-.

-*#* µ!

+ *+ *+ % #

- /%&++ /

/*+%+ F%1+ /

,

)2)*34*,+)+1+2%

+ )1)+ %+#8

**&' 4+ 1 * % / 7' *& 67<#<9

;+4'25(9

-+)*,+-*#***#

C

2I

#3

L

2I

0

3

L

I

#!

#!

4

$ ')* %, ,,++%*#*

+,

-.

-*#* µ!

+ *+ *+ % #

- /%&++ /

/*+%+ F%1+ /

,

)2)*34*,+)+1+2%

+ )1)+ %+#8

**&' $+%&+ 1 * % / 7' *& 67<#<9

;+4'25(9

-+)*,+-*#***#

#!

;

:,"5(: ''&>M

)+%%$8 ########################79

>)+%%$8 A#####################79

3

0

1

1 10.66 0.66

1.5 10

0.66 0.66 0.66

0.435

0.66 0.435

0.22

on on

n off

on

off

T TD T ms

T T T f X

T X T X ms

ms

T T T

ms

= = = = = =+

= =

=

= −

= −

=

;+79079

0.01C Fµ=

3

6

3

6

0.435 1062.77

0.693 0.693 0.01 10

0.22 1031.7

0.693 0.693 0.01 10

onA

off

B

T XR K

X C X X

T XR K

X C X X

−

−

−

−

= = = Ω

= = = Ω

0

VC

Vo

#!

!"= ##$##$#####

2)!'((2)!'&)%7%2(

4

$ ')*+,&+%+

+,

-.

+

+0*+ *+ % #

> AN!

/*+%+ F%1+ #

-

,

)2)*34*,+)+1+2%

+ )1)+ %+#

/1))*1+**&' +)*1,+-

G+$0$:$&)+ %

> $54D7 >$54D7

&G&++

-

-* &'

"Ω $)

1.1

d

A

TC F Use F capacito

R= =

5+) T T dR C T<<

/&10

dT T

TR C <<

$=; $

0

-**&1 )>&'

-* &': 1.1d AT R C=

(0.045 0.047 standard rC F Use F capacitoµ µ= =

10

dT

=; $ /:/$"I

#!

)0.045 0.047 standard rC F Use F capacito

#!

4

$ ')*+,&+%+

+,

-.

+

+0*+ *+ % #

> AN!

/*+%+ F%1+ #

-F/%&++ /

,

)2)*34*,+)+1+2%

+ )1)+ %+#

/1))*1+**&' +)*1,+-

G+$ & +,'1)) % &

-+)1,+ ,,+*)1)1,+

> $54D7 >$54D7

G&G&++

2

679F6

6796*2F 6>),6*2

$)2Ω

679AAF6A

6796*2K*276*290

AµF!

∴A "Ω

*

,,,+4',),&+,OO,

),5(:,3

µ

67*#*

,

P +/*&%

7,Q,9

?4

,,

-+/*&%

,O,

::),:6 6:

6A!6:,5(

679F6

6796*2F 6>),6*2%&

Ω

A

*276*290A3),µ

F!

,,,+4',),&+,OO,

),5(:,3π

µ,:) 2Ω

*9HHHHHHH667*#*9HHHHHHHH6

/9

/9

7

,,,

7

,,,

/9

P +/*&%

-+/*&%

#!

6:

,,,

/9

#!

!"? ##$##$#####

&)!' )%3B*)( ' )%3!(&%(

4 ,

$ E*+ %+ *& *&% &

)

+,

-.

$++/ #

+0*+ *+ % #

/*+%+ F%

1+#

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&')4+1+++%&,6*2*2*& ,

,+4'5(

**&'1 &%%&, ,+4' ,5(1)6

*2*2*& 6 ),

-+)<G1,+

-+) & %&)*,)&1*,&+

, 6

! *)*,+,, ,Q,

#!

5

+,:++/:++:*+*+

%

6*&6:6A79!6:679 6 :

), 6A67*2*& ,7991)++ +

+

6*&F679

F6798Ω≅"Ω

6A#AA#6A79

A3

AGE 2Ω)A2Ω

1*,&+ %

,537π9R +

),,,+4',,&+:,55( µ,:)

2Ω

#!

24 *,

$ %+ ,+%+% ,& **& +,'/*&%

)+

+,

-.

#3 #

+0*+ *+ % #

/*+%+ F%

1+#

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&')4+1+++%&,6*2*2*& ,

,+4'5(

**&'1 &%%&,,+4',5(1)6

*2*2*& ),

-+)*1,+

-+) & %&)*,)&1*,&+

, 6

! *)*,+,, ,Q,

)*& * * ) &+ *

++)+%&%%&

#!

0

67*#*9HHHHHHH667*#*9HHHHHHHH6

,

/9

/9

7

,,,

7

,,,

/9

P +/*&%

7,Q,9

?4

,,

-+/*&%

,O,

6

/*,,;$25(

OO$1)+$3,;$

$

µ,)8!2

!

3,O O3, 3,

µ,:) 2

0

% m

% m

;$25(

OO$1)+$3,;$

,)8!2Ω

3,O O3, 3,

,:) 2Ω

#!

Vm

#!

m(t) c(t) AM

wave Vmin

t !"A ##$##$####

' )%&!'(&)%(&%3%(

$ E*+ %+G%& & )

G%&

+,

-.

$++ /

+0*+ *+ % #

> -!8

;$:;$ # )

<+ #

,

)2)*34*,+)+1+2%

+ )1)+ %+#

A'1)%,,) &%%&:, ) ,+4',;$

'+'%,+4',79

"*%)+++,+4') ,+4',);$1)

) &%%& +)G%&

; ) & E:)*& ,)+++%&6

)*& ,)%%&6'++ %)6E 6

76E 6 )& + ,+ ) G %&

$+*( &1,+9

*)*'+'%)*& , &%%&

<&%+*),66M

! ) &* + + + ) &

%&

$)$+*( &1,+:, ) &%%&)&

79 G1)&79:*+S#N2

#!

Vc

',

7"

7

7

7

minmax

minmax

VV

VVm

+

−= 2

minmax VVVm

−=

7

2

minmax VVVc

+=

7

,

77 /9

6E 6

#!

<

/*,+++,+4', 25(

, 379B)+

2Ω)µ;

)2Ω:2Ω:µ;

0

#!

!"C ##$##$#####

*!-&!E'(&)%(&%3A;5A

$ E*+%+;+4'G & 1

, ,+4' & E

+,

-.

#

+0*+ *+ % )

-<+ #

,

)2)*34*,+)+1+2%

+ )1)+ %+#

A'1)%,,) &%%&79),+4',)

+++1<?,#

**&' ) &% %& 1) & *& % ) ;G

%&

?)E7,E9 7,9,+4',)+++

1;G%&

&&),+4' : & E 1 )

#!

,HHHHHHHHHHH5(:,HHHHHHHHHHH5(

7

7

"

%

/9

%/9

δδδδ

/9

δδδδ

/9

δδδδ

/9

ββββ:

δδδδ$

2

:δδδδF

%/9

1 max 2 min,C C C CWhere f f f f∂ = − ∂ = −

#!

G & EHHHHHHHHH

GE;+4'>HHHHH5(

A 1 ),-*+HHHHHHHHHHH5(

=

#!

:7!:<7 %:ββββ: ;;

76S ;7

6M66

637FA9

A3β3µ

37Fµ98Ω

)!:6?;ΩΩΩΩ

**&'"6&&+&*

6KK6K6

76K6K6937KK93

2Ω):@ΩΩΩΩ

ASµµ

66AF6

F67/++&26A69

637KA937µ#µ9

2Ω): ;@ΩΩΩΩ

76K6937K93µ

"Ω) :6?@ΩΩΩΩ

SQQ

S3

37π,9!3 ,5(

µ;)!:6?µµµµ*

!" ; ##$##$#####

#!

2G'%H!

$ %E+%AT$3;$%+ + %&

+,

-.

$++ /#

+ *+ <+>% )

/*+%+ F%

1+#

,

)2)*34*,+)+1+2%

+ )1)+ %+#

**&')*%& )+ %+

-+)*1,+

G+)*,+4':)4&,,#,5(

:#####/9B:#####/9

;:##########/9

#!

!" ##$##$#####

232',% 6C=

$%+G#>&/ A /**+ +++7>/A#/9%&%

8

+,

-.

!"#$

%

&'()()*+&()()*()

,-+-

&./

0 1% !2 3$

4()

%5

/6

,

7%83 9

4+:*"

,

)2)*34*,+)+1+2%

+ )1)+ %+#!

**&')+++%&,6*#**& ,+4', "5(

**& +++*

**&')%%&,6*#**& ,+4',"5(

%%%&*

-+)>/A/*1,+

#!

A

,25(

:1 1

)@: II

#!

!" ##$##$#####

*!-&!EE/!%&%3 ))

$ E*+ % +&(,+4'')%

<

+,

-.

< #

!/8 #

++ /

+ *+ *+ %

-:/:G&+ # )

,

$, 2 *++%

+ )1)+>%+#

>% )&, ,+ ,+4' , '"5(

/1))F6 #6*1+**&'

$) 6 3* * ? )& 4+ 1 , ,+4' ,7,+

+%,+4'9

?1 1) ) / ,+4' * 7*& *2

*269

+ )/,+4' ,+ &1 ,+4'7'5(9& )<

%&2 ',CB))<%&2 )6,+4',1&&

4&)*,+4',)*,+4'+ )6

,+4',+:,)*,+4' + )6,+4'

, +:))6-+2)*,+4'

+ ) * ,+4' ,+)+ & ) < , &2 '

,U

?1 +)*,+4',+E&&)<%&2

',C

! >+)*,+4',+)+&)<,&2'

,U

#!

,

$')(,+4'&*& ',+?

+ )1)+>%+#8

>%)&, ,+,+4','"5(

/1))F6 #6*1+**&'

?11))/ @)*& ,)4+16

*2*2

6+'),+4',)4+17/9&,?L,7;+E*&

?9

#!

'J

0%,<<<

$21+&& %&+%$+

-.

$+

+ "I

A((+ #6

%1+ #

, %*)+)1)+ %+#

**&'F6**&'67*9

"*)*+31+ )1++

-+)*

0@

$)++&&' & %& &'1))*+

) ) 1+ $) 1 ) *+ )& & ) ,1

+ + ) ) 1 ) *+ 1&& 2 *&

1)1+) )*+B))1+&&+))%)

,)*+:))+1&&%& )*%)

& *2+3A((+1)))*

#!

-2@

>% + *&,+ + ,+ ) % & ,

HHHH

>%## & +>'%% * ,+ #+

% &% * &% , HHHH 61) ) %& * &%

HHHH6

>%##& +>'%%*,+%%&1)%

&%*&%,HHHH61)) %&*&%HHHH6

E*+%+),+4'HHHHHH5(,*)/),

-&&+%-*#*

E*+%+),+4'HHHHHH5(,BCA+ %

-&&+%-*#*

>% + + +1+) &1* ,&+ ,+ % ,,

,+4',HHHHHHH"5(7Q"5(9 E*+ +1)

,+4'+* +,')+&&,,

! >% + ++1+))%)* ,&+ ,+%,,

,+4' ,HHHHHH"5(7Q"5(9 E*+ +1)

,+4'+* +,')+&&,,

>% ++%-*#*,+)%HHHHHHHH

8 >%%+++%-*#*,+)%HHHHHHHH

>% >,,++ + % -*#* ,+ ) %

HHHHHHHH

>% & &++ ,+ % ,+4' HHHHHH 0 '

'&HHHHHHH

>%G&&++,+%*&1 )HHHHHHHHH

E*+%+<&*&% & %+

&) <&/*&%%& +,'*&%)+

<&)+&1,+7/*,:);:679!6:

,5(9

E*+ %+ ;&#$* *&% & %

+ & ) ;&#$* /*&% %& +,'

*&%)+<&)+&1,+

E*+%+G%&%&&+ &

<& ) + , &% %& *& 6 & E &

&)G1%&* +

>% &E*+ %+;G1%

; ) & E ) 1 ),*+

! >% &E*+%+>/A/1%

8

>% &E*+%+GE++%

AT$

8 &E*+'),+4'%<)4

#!

B)-*#*VB)+) &)++,**

)*+&&,&%%:W:W,*#*

B)'GVB)%,

B)'%,*#*)& ,

B)&1+:*,,&%

B)'E*&%1%

! B)'+%*&,+

B)'#+%*&,+

8 B)&%,&&1+V51 '+&(&%,&&1+

B)*++V

B)')*,*++&1'4+1

B))+&& +%+*++ 1)'

B)+***++V

B)+)&,*++V

B)) ,+)+1+2%++ ,,++

B)W> %,**&V

! B)+

B)/)$+%%+

8 E*&)1+2%,/)+%%+

B)'P$< $<

>,> +> (

G)**&,/)$+%%+

>,,+

?)'*,,+

B)<+,+

&()+,++%

! G'*,*++,+

E*&)1+2%,;&&B<+,+

8 >,+

>,,+'*,>3++

B+2%,#>3++

B) ' + '> >VB)+

B) %,#>+)+'*>

B)+&7*(9>

B),,+++>

B)+) ,,+'*,>

! B))),>VB)+&

#!

B)))&' >

8 B),&+

>%)1 *,&+

>%)1&% %&,&+

B)+) %,,&++*,&+

E*&)&,,,&+

>,&1*,&+

>,)%)*,&+

B)' ++, ,&+

! B)+)**&,,&+

>+*& &

8 >+,+4' &

>, & E

B)*+% &

B)*+#*)V1)'

B)>#*)V1)'

E*&)1+2%&* +

*++'*,,+4' &+

>,&1&& )%)&& &

! B)V? ,,&&,,( :

@,'

>,,%+,+

8 E*&)*+,&* ++

>,+ &

E*&<&*& &

E*&*&1 ) &

*+<G1)<BG

E*&*&* &

B)+) %,<<G+<G

%!'K!' !*!

IN +

IN –

OUT

+

–

OFFSET N1

OFFSET N2

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

uA741

SLOS094E –NOVEMBER 1970–REVISED JANUARY 2015

µA741 General-Purpose Operational Amplifiers

1 Features 3 DescriptionThe µA741 device is a general-purpose operational

1• Short-Circuit Protectionamplifier featuring offset-voltage null capability.

• Offset-Voltage Null CapabilityThe high common-mode input voltage range and the• Large Common-Mode and Differential Voltageabsence of latch-up make the amplifier ideal forRangesvoltage-follower applications. The device is short-

• No Frequency Compensation Required circuit protected and the internal frequency• No Latch-Up compensation ensures stability without external

components. A low value potentiometer may beconnected between the offset null inputs to null out2 Applicationsthe offset voltage as shown in Figure 11.

• DVD Recorders and PlayersThe µA741C device is characterized for operation• Pro Audio Mixersfrom 0°C to 70°C. The µA741M device (obsolete) ischaracterized for operation over the full militarytemperature range of –55°C to 125°C.

Device Information(1)

PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)

SOIC (8) 4.90 mm × 3.91 mm

µA741x PDIP (8) 9.81 mm × 6.35 mm

SO (8) 6.20 mm × 5.30 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

uA741

SLOS094E –NOVEMBER 1970–REVISED JANUARY 2015 www.ti.com

Table of Contents

8.2 Functional Block Diagram ......................................... 91 Features .................................................................. 18.3 Feature Description................................................. 102 Applications ........................................................... 18.4 Device Functional Modes........................................ 103 Description ............................................................. 18.5 µA741Y Chip Information........................................ 104 Simplified Schematic............................................. 1

9 Application and Implementation ........................ 115 Revision History..................................................... 29.1 Application Information............................................ 11

6 Pin Configurations and Functions ....................... 39.2 Typical Application .................................................. 11

7 Specifications......................................................... 410 Power Supply Recommendations ..................... 13

7.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 13

7.2 Recommended Operating Conditions....................... 411.1 Layout Guidelines ................................................. 13

7.3 Electrical Characteristics A741C, A741M ............. 511.2 Layout Example .................................................... 13

7.4 Electrical Characteristics A741Y............................. 612 Device and Documentation Support ................. 157.5 Switching Characteristics A741C, A741M ............ 6

12.1 Trademarks ........................................................... 157.6 Switching Characteristics A741Y ............................ 612.2 Electrostatic Discharge Caution............................ 157.7 Typical Characteristics .............................................. 712.3 Glossary ................................................................ 158 Detailed Description .............................................. 9

13 Mechanical, Packaging, and Orderable8.1 Overview ................................................................... 9Information ........................................................... 15

5 Revision History

Changes from Revision D (February 2014) to Revision E Page

• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,

Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply

Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section. ..................................................................................................................... 1

• Moved Typical Characteristics into Specifications section. ................................................................................................... 7

Changes from Revision C (January 2014) to Revision D Page

• Fixed Typical Characteristics graphs to remove extra lines. ................................................................................................. 7

Changes from Revision B (September 2000) to Revision C Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 1970–2015, Texas Instruments Incorporated

Product Folder Links: uA741

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC

VCC+

NC

OUT

NC

NC

IN–

NC

IN+

NC

µA741M . . . FK PACKAGE

(TOP VIEW)

NC

OF

FS

ET

N1

NC

OF

FS

ET

N2

NC

NC

NC

NC

V

NC

CC

–

NC – No internal connection

1

2

3

4

5

10

9

8

7

6

NC

OFFSET N1

IN–

IN+

VCC–

NC

NC

VCC+

OUT

OFFSET N2

µA741M . . . U PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC

NC

OFFSET N1

IN–

IN+

VCC–

NC

NC

NC

NC

VCC+

OUT

OFFSET N2

NC

µA741M . . . J PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

OFFSET N1

IN–

IN+

VCC–

NC

VCC+

OUT

OFFSET N2

µA741M . . . JG PACKAGE

µ µA741C, A741I . . . D, P, OR PW PACKAGE

(TOP VIEW)

uA741

www.ti.com SLOS094E –NOVEMBER 1970–REVISED JANUARY 2015

6 Pin Configurations and Functions

Pin Functions

PIN

NAME TYPE DESCRIPTIONJG, D, P, orJ U FK

PW

IN+ 5 3 4 7 I Noninverting input

IN– 4 2 3 5 I Inverting input

1, 2, 8,1,3,4,6,8,9,11,13,1

NC 12, 13, 8 1, 9, 10 — Do not connect4,16,18,19,20

14

OFFSET3 1 2 2 I External input offset voltage adjustment

N1

OFFSET9 5 6 12 I External input offset voltage adjustment

N2

OUT 10 6 7 15 O Output

VCC+ 11 7 8 17 — Positive supply

VCC– 6 4 5 10 — Negative supply

Copyright © 1970–2015, Texas Instruments Incorporated Submit Documentation Feedback 3


uA741


7 Specifications

7.1 Absolute Maximum Ratings

over virtual junction temperature range (unless otherwise noted) (1)

µA741C µA741MUNIT

MIN MAX MIN MAX

VCC Supply voltage (2) –18 18 –22 22 C

VID Differential input voltage (3) –15 15 –30 30 V

VI Input voltage, any input (2) (4) –15 15 –15 15 V

Voltage between offset null (either OFFSET N1 or OFFSET N2) and VCC– –15 15 –0.5 0.5 V

Duration of output short circuit (5) Unlimited

Continuous total power dissipation See Table 1

TA Operating free-air temperature range 0 70 –55 125 °C

Case temperature for 60 seconds FK package N/A N/A 260 °C

Lead temperature 1.6 mm (1/16 inch) from case forJ, JG, or U package N/A N/A 300 °C

60 seconds

Lead temperature 1.6 mm (1/16 inch) from case forD, P, or PS package 260 N/A N/A °C

10 seconds

Tstg Storage temperature range –65 150 –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.(3) Differential voltages are at IN+ with respect to IN –.(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.(5) The output may be shorted to ground or either power supply. For the µA741M only, the unlimited duration of the short circuit applies at

(or below) 125°C case temperature or 75°C free-air temperature.

7.2 Recommended Operating Conditions

MIN MAX UNIT

VCC+ 5 15Supply voltage V

VCC– –5 –15

µA741C 0 70TA Operating free-air temperature °C

µA741M –55 125

Table 1. Dissipation Ratings Table

TA 25°C TA = 70°CDERATING DERATE TA = 85°C TA = 125°C

PACKAGE POWER POWERFACTOR ABOVE TA POWER RATING POWER RATING

RATING RATING

D 500 mW 5.8 mW/°C 64°C 464 mW 377 mW N/A

FK 500 mW 11.0 mW/°C 105°C 500 mW 500 mW 275 mW

J 500 mW 11.0 mW/°C 105°C 500 mW 500 mW 275 mW

JG 500 mW 8.4 mW/°C 90°C 500 mW 500 mW 210 mW

P 500 mW N/A N/A 500 mW 500 mW N/A

PS 525 mW 4.2 mW/°C 25°C 336 mW N/A N/A

U 500 mW 5.4 mW/°C 57°C 432 mW 351 mW 135 mW



uA741


7.3 Electrical Characteristics !A741C, !A741M

at specified virtual junction temperature, VCC± = ±15 V (unless otherwise noted)

!A741C !A741MPARAMETER TEST CONDITIONS TA

(1) UNITMIN TYP MAX MIN TYP MAX

25°C 1 6 1 5VIO Input offset voltage VO = 0 mV

Full range 7.5 ±15 6

!VIO(adj) Offset voltage adjust range VO = 0 25°C ±15 20 200 mV

25°C 20 200 500IIO Input offset current VO = 0 nA

Full range 300 500

25°C 80 500 80 500IIB Input bias current VO = 0 nA

Full range 800 1500

25°C ±12 ±13 ±12 ±13VICR Common-mode input voltage range V

Full range ±12 ±12

RL = 10 k" 25°C ±12 ±14 ±12 ±14

RL # 10 k" Full range ±12 ±12VOM Maximum peak output voltage swing V

RL = 2 k" 25°C ±10 ±10 ±13

RL # 2k" Full range ±10 ±10

RL # 2k" 25°C 20 200 50 200Large-signal differential voltageAVD V/mV

amplification VO = ±10 V Full range 15 25

ri Input resistance 25°C 0.3 2 0.3 2 M"

ro Output resistance VO = 0, See (2) 25°C 75 75 "

Ci Input capacitance 25°C 1.4 1.4 pF

25°C 70 90 70 90CMRR Common-mode rejection ratio VIC = VICRmin dB

Full range 70 70

25°C 30 150 30 150kSVS Supply voltage sensitivity (!VIO/!VCC) VCC = ±9 V to ±15 V µV/V

Full range 150 150

IOS Short-circuit output current 25°C ±25 ±40 ±25 ±40 mA

25°C 1.7 2.8 1.7 2.8ICC Supply current VO = 0, No load mA

Full range 3.3 3.3

25°C 50 85 50 85PD Total power dissipation VO = 0, No load mW

Full range 100 100

(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Fullrange for the µA741C is 0°C to 70°C and the µA741M is –55°C to 125°C.

(2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.



uA741


7.4 Electrical Characteristics !A741Y

at specified virtual junction temperature, VCC± = ±15 V, TA = 25°C (unless otherwise noted) (1)

!A741YPARAMETER TEST CONDITIONS UNIT

MIN TYP MAX

VIO Input offset voltage VO = 0 1 5 mV

!VIO(adj) Offset voltage adjust range VO = 0 ±15 mV

IIO Input offset current VO = 0 20 200 nA

IIB Input bias current VO = 0 80 500 nA

VICR Common-mode input voltage range ±12 ±13 V

RL = 10 k" ±12 ±14VOM Maximum peak output voltage swing V

RL = 2 k" ±10 ±13

AVD Large-signal differential voltage amplification RL # 2k" 20 200 V/mV

ri Input resistance 0.3 2 M"

ro Output resistance VO = 0, See (1) 75 "

Ci Input capacitance 1.4 pF

CMRR Common-mode rejection ratio VIC = VICRmin 70 90 dB

kSVS Supply voltage sensitivity (!VIO/!VCC) VCC = ±9 V to ±15 V 30 150 µV/V

IOS Short-circuit output current ±25 ±40 mA

ICC Supply current VO = 0, No load 1.7 2.8 mA

PD Total power dissipation VO = 0, No load 50 85 mW

(1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.

7.5 Switching Characteristics !A741C, !A741M

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)

µA741C µA741MPARAMETER TEST CONDITIONS UNIT

MIN TYP MAX MIN TYP MAX

tr Rise time 0.3 0.3 µsVI = 20 mV, RL = 2 k",CL = 100 pF, See Figure 1Overshoot factor 5% 5% —

VI = 10 V, RL = 2 k",SR Slew rate at unity gain 0.5 0.5 V/µs

CL = 100 pF, See Figure 1

7.6 Switching Characteristics !A741Y

over operating free-air temperature range, VCC± = ±15 V, TA = 25°C (unless otherwise noted)

µA741YPARAMETER TEST CONDITIONS UNIT

MIN TYP MAX

tr Rise time 0.3 µsVI = 20 mV, RL = 2 k",CL = 100 pF, See Figure 1Overshoot factor 5% —

VI = 10 V, RL = 2 k",SR Slew rate at unity gain 0.5 V/µs

CL = 100 pF, See Figure 1



V

±20

f – Frequency – Hz

1M100k10k1k

OM

–M

axim

um

Peak

Ou

tpu

tV

olt

ag

e–

V ±18

±16

±14

±12

±10

±8

±6

±4

±2

0

VCC+ = 15 V

VCC– = –15 V

RL = 10 kΩ

TA = 25°C

100

V

RL – Load Resistance – kΩ

1074210.70.40.20.1±4

±5

±6

±7

±8

±9

±10

±11

±12

±13

±14

VCC+ = 15 V

VCC– = –15 V

TA = 25°C

OM

–M

ax

imu

mP

ea

kO

utp

ut

Vo

lta

ge

–V

400

300

200

100

00 40 80 120

TA – Free-Air Temperature – °C

I IB

–In

pu

tB

ias

Cu

rren

t–

nA

VCC– = –15 V

VCC+ = 15 V

350

250

150

50

–40–60 –20 20 60 100 140

I

TA – Free-Air Temperature – °C

12080400–40

20

IO–

Inp

ut

Off

se

tC

urr

en

t–

nA

VCC– = –15 V

VCC+ = 15 V90

70

50

30

10

0

40

60

80

100

–60 –20 20 60 100 140

INPUT VOLTAGE

WAVEFDORM

TEST CIRCUIT

RL = 2 kΩCL = 100 pF

OUT

IN

+

–

0 V

VI

uA741


7.7 Typical Characteristics

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various

devices.

Figure 1. Rise Time, Overshoot, and Slew Rate

Figure 2. Input Offset Current vs Free-Air Temperature Figure 3. Input Bias Current vs Free-Air Temperature

Figure 4. Maximum Output Voltage vs Load Resistance Figure 5. Maximum Peak Output Voltage vs Frequency



8

6

4

2

0

–2

–4

–6

9080706050403020100

Inp

ut

an

dO

utp

ut

Vo

lta

ge

–V

t – Time – ms

–8

VO

VI

VCC+ = 15 V

VCC– = –15 V

RL = 2 kΩ

CL = 100 pF

TA = 25°C

CM

RR

–C

om

mo

n-M

od

eR

eje

cti

on

Ra

tio

–d

B


10k 1M 100M1001

0

10

20

30

40

50

60

70

80

90

100

VCC+ = 15 V

VCC– = –15 V

BS = 10 kΩ

TA = 25°C

10%

tr

2.521.510.50

28

24

20

16

12

8

4

0

–O

utp

ut

Vo

ltag

e–

mV

t – Time - µs

–4

VO

90%

VCC+ = 15 V

VCC– = –15 V

RL = 2 kΩ

CL = 100 pF

TA = 25°C


10M1M10k1001–10

0

10

20

70

80

90

100

110

VO = ±10 V

RL = 2 kΩ

TA = 25°C

AV

D–

Op

en

-Lo

op

Sig

nalD

iffe

ren

tial

Vo

ltag

eA

mp

lifi

cati

on

–d

B

10 1k 100k

60

50

30

40

VCC+ = 15 V

VCC– = –15 V

2018161412108642

400

200

100

40

20

10

0

VCC± – Supply Voltage – V

VO = ±10 V

RL = 2 kΩ

TA = 25°C

AV

D–

Op

en

-Lo

op

Sig

na

lD

iffe

ren

tia

l

Vo

lta

ge

Am

pli

fic

ati

on

–V

/mV

uA741


Typical Characteristics (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various

devices.

Figure 6. Open-Loop Signal Differential Figure 7. Open-Loop Large-Signal Differential

Voltage Amplification Voltage Amplification

vs vs

Supply Voltage Frequency

Figure 8. Common-Mode Rejection Ratio vs Frequency Figure 9. Output Voltage vs Elapsed Time

Figure 10. Voltage-Follower Large-Signal Pulse Response



IN–

IN+

VCC+

VCC–

OUT

OFFSET N1

OFFSET N2

Transistors 22

Resistors 11

Diode 1

Capacitor 1

Component Count

uA741


8 Detailed Description

8.1 Overview

The µA741 device is a general-purpose operational amplifier featuring offset-voltage null capability.

The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltage-follower applications. The device is short-circuit protected and the internal frequency compensation ensuresstability without external components. A low value potentiometer may be connected between the offset nullinputs to null out the offset voltage as shown in Figure 11.

The µA741C device is characterized for operation from 0°C to 70°C. The µA741M device (obsolete) ischaracterized for operation over the full military temperature range of –55°C to 125°C.

8.2 Functional Block Diagram



BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 TYPICAL

BONDING PADS: 4 × 4 MINIMUM

TJmax = 150°C.

TOLERANCES ARE ±10%.

ALL DIMENSIONS ARE IN MILS.

+

–

OUT

IN+

IN–

VCC+

(7)(3)

(2)

(6)

(4)

VCC–(5)

(1)

OFFSET N2

OFFSET N1

45

36

(1)

(8)

(7) (6)

(5)

(4)

(3)(2)

uA741


8.3 Feature Description

8.3.1 Offset-Voltage Null Capability

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in thedifferential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-gain betas ($), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for thesemismatches by external circuitry. See the Application and Implementation section for more details on designtechniques.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on theinput. The µA741 has a 0.5-V/ s slew rate. Parameters that vary significantly with operating voltages ortemperature are shown in the Typical Characteristics graphs.

8.4 Device Functional Modes

The µA741 is powered on when the supply is connected. It can be operated as a single supply operationalamplifier or dual supply amplifier depending on the application.

8.5 µA741Y Chip Information

This chip, when properly assembled, displays characteristics similar to the µA741C. Thermal compression orultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductiveepoxy or a gold-silicon preform.



12 V

+

VIN

VOUT

10 k

To VCC–

OFFSET N1

10 kΩ

OFFSET N2

+

–

OUT

IN+

IN–

uA741


9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in thedifferential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-gain betas ( ), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for thesemismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometerbetween the inputs as shown in Figure 13. A potentiometer can be used to fine tune the circuit during testing orfor applications which require precision offset control. More information about designing using the input-offsetpins, see the application note Nulling Input Offset Voltage of Operational Amplifiers, SLOA045.

Figure 11. Input Offset Voltage Null Circuit

9.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal isused to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. Theinputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltagesource. The output resistance of the operational amplifier is almost negligible, so it can provide as much currentas necessary to the output load.

Figure 12. Voltage Follower Schematic

9.2.1 Design Requirements

• Output range of 2 V to 11.5 V

• Input range of 2 V to 11.5 V



0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0 2 4 6 8 10 12

ICC

(m

A)

VIN (V) C003

0

2

4

6

8

10

12

0 2 4 6 8 10 12

VO

UT

(V

)

VIN (V) C001

±0.005

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0 2 4 6 8 10 12

IIO

(m

A)

VIN (V) C002

uA741


Typical Application (continued)

• Resistive feedback to negative input

9.2.2 Detailed Design Procedure

9.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supplyrails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and outputvoltage requirements.

9.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply railvoltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able tooperate at the supply voltage that accommodates the inputs. Because the input for this application goes up to11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows theamplifier to maintain linearity for inputs below 2 V.

9.2.3 Application Curves for Output Characteristics

Figure 13. Output Voltage vs Input Voltage Figure 14. Current Drawn Input of Voltage Follower (IIO)

vs Input Voltage

Figure 15. Current Drawn from Supply (ICC)

vs Input Voltage



+RIN

RGRF

VOUTVIN

uA741


10 Power Supply Recommendations

The !A741 is specified for operation from ±5 to ±15 V; many specifications apply from 0°C to 70°C. The TypicalCharacteristics section presents parameters that can exhibit significant variance with regard to operating voltageor temperature.

CAUTION

Supply voltages larger than ±18 V can permanently damage the device (see theAbsolute Maximum Ratings).

Place 0.1-!F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the LayoutGuidelines.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operationalamplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance powersources local to the analog circuitry.

– Connect low-ESR, 0.1-!F ceramic bypass capacitors between each supply pin and ground, placed asclose to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effectivemethods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digitaland analog grounds, paying attention to the flow of the ground current. For more detailed information, refer toCircuit Board Layout Techniques, SLOA089.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. Ifit is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular asopposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the invertinginput minimizes parasitic capacitance, as shown in Layout Example.

• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 16. Operational Amplifier Schematic for Noninverting Configuration



NC

VCC+IN1í

IN1+

VCCí

NC

OUT

NC

RG

RIN

RF

GND

VIN

VS-GND

VS+

GND

Run the input traces as far

away from the supply lines

as possible

Only needed for

dual-supply

operation

Place components close to

device and to each other to

reduce parasitic errors

Use low-ESR, ceramic

bypass capacitor

(or GND for single supply) Ground (GND) plane on another layerVOUT

uA741


Layout Example (continued)

Figure 17. Operational Amplifier Board Layout for Noninverting Configuration



uA741


12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser based versions of this data sheet, refer to the left hand navigation.



PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

10-J

un-2

014

Addendum

-Page 1

PA

CK

AG

ING

IN

FO

RM

AT

ION

Ord

era

ble

Devic

eS

tatu

s

(1)

Packag

e T

yp

eP

ackag

e

Dra

win

g

Pin

sP

ackag

e

Qty

Eco

Pla

n

(2)

Lead

/Ball F

inis

h

(6)

MS

L P

eak T

em

p

(3)

Op

Tem

p (

°C)

Devic

e M

ark

ing

(4/5

)

Sam

ple

s

UA

741C

DA

CT

IVE

SO

ICD

875

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

A741C

UA

741C

DG

4A

CT

IVE

SO

ICD

875

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

A741C

UA

741C

DR

AC

TIV

ES

OIC

D8

2500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

A741C

UA

741C

DR

G4

AC

TIV

ES

OIC

D8

2500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

A741C

UA

741C

JG

OB

SO

LE

TE

CD

IPJG

8T

BD

Call

TI

Call

TI

0 to 7

0

UA

741C

JG

4O

BS

OLE

TE

CD

IPJG

8T

BD

Call

TI

Call

TI

0 to 7

0

UA

741C

PA

CT

IVE

PD

IPP

850

Pb-F

ree

(RoH

S)

CU

NIP

DA

UN

/ A

for

Pkg T

ype

0 to 7

0U

A741C

P

UA

741C

PE

4A

CT

IVE

PD

IPP

850

Pb-F

ree

(RoH

S)

CU

NIP

DA

UN

/ A

for

Pkg T

ype

0 to 7

0U

A741C

P

UA

741C

PS

RA

CT

IVE

SO

PS

82000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

741

UA

741C

PS

RE

4A

CT

IVE

SO

PS

82000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

0 to 7

0U

741

UA

741M

FK

BO

BS

OLE

TE

LC

CC

FK

20

TB

DC

all

TI

Call

TI

-55 to 1

25

UA

741M

JO

BS

OLE

TE

CD

IPJ

14

TB

DC

all

TI

Call

TI

-55 to 1

25

UA

741M

JB

OB

SO

LE

TE

CD

IPJ

14

TB

DC

all

TI

Call

TI

-55 to 1

25

UA

741M

JG

OB

SO

LE

TE

CD

IPJG

8T

BD

Call

TI

Call

TI

-55 to 1

25

UA

741M

JG

BO

BS

OLE

TE

CD

IPJG

8T

BD

Call

TI

Call

TI

-55 to 1

25

(1) T

he m

ark

eting s

tatu

s v

alu

es a

re d

efined a

s follo

ws:

AC

TIV

E:

Pro

duct devic

e r

ecom

mended for

new

desig

ns.

LIF

EB

UY

: T

I has a

nnounced that th

e d

evic

e w

ill b

e d

iscontinued, and a

lifetim

e-b

uy p

eriod is in e

ffect.

NR

ND

: N

ot re

com

mended for

new

desig

ns. D

evic

e is in p

roduction to s

upport

exis

ting c

usto

mers

, but T

I does n

ot re

com

mend u

sin

g this

part

in a

new

desig

n.

PR

EV

IEW

: D

evic

e h

as b

een a

nnounced b

ut is

not in

pro

duction. S

am

ple

s m

ay o

r m

ay n

ot be a

vaila

ble

.

OB

SO

LE

TE

: T

I has d

iscontinued the p

roduction o

f th

e d

evic

e.

(2) E

co P

lan - T

he p

lanned e

co-f

riendly

cla

ssific

ation: P

b-F

ree (R

oH

S),

Pb-F

ree (R

oH

S E

xem

pt)

, or G

reen (R

oH

S &

no S

b/B

r) - p

lease c

heck h

ttp://w

ww

.ti.com

/pro

ductc

onte

nt fo

r th

e la

test availa

bili

ty

info

rmation a

nd a

dditio

nal pro

duct conte

nt deta

ils.

TB

D:

The P

b-F

ree/G

reen c

onvers

ion p

lan h

as n

ot been d

efined.

PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

10-J

un-2

014

Addendum

-Page 2

Pb

-Fre

e (

Ro

HS

): T

I's t

erm

s "

Lead-F

ree"

or

"Pb-F

ree"

mean s

em

iconducto

r pro

ducts

that

are

com

patible

with t

he c

urr

ent

RoH

S r

equirem

ents

for

all

6 s

ubsta

nces,

inclu

din

g t

he r

equirem

ent

that

lead n

ot exceed 0

.1%

by w

eig

ht in

hom

ogeneous m

ate

rials

. W

here

desig

ned to b

e s

old

ere

d a

t hig

h tem

pera

ture

s,

TI P

b-F

ree p

roducts

are

suitable

for

use in s

pecifie

d lead-f

ree p

rocesses.

Pb

-Fre

e (

Ro

HS

Exem

pt)

: T

his

com

ponent has a

RoH

S e

xem

ption for

either

1)

lead-b

ased flip

-chip

sold

er

bum

ps u

sed b

etw

een the d

ie a

nd p

ackage, or

2)

lead-b

ased die

adhesiv

e u

sed b

etw

een

the d

ie a

nd leadfr

am

e. T

he c

om

ponent is

oth

erw

ise c

onsid

ere

d P

b-F

ree (

RoH

S c

om

patible

) as d

efined a

bove.

Gre

en

(R

oH

S &

no

Sb

/Br)

: T

I defines "

Gre

en"

to m

ean P

b-F

ree (

RoH

S c

om

patible

), a

nd f

ree o

f B

rom

ine (

Br)

and A

ntim

ony (

Sb)

based f

lam

e r

eta

rdants

(B

r or

Sb d

o n

ot

exceed 0

.1%

by w

eig

ht

in h

om

ogeneous m

ate

rial)

(3) M

SL, P

eak T

em

p. -

The M

ois

ture

Sensitiv

ity L

evel ra

ting a

ccord

ing to the J

ED

EC

industr

y s

tandard

cla

ssific

ations, and p

eak s

old

er

tem

pera

ture

.

(4) T

here

may b

e a

dditio

nal m

ark

ing, w

hic

h r

ela

tes to the logo, th

e lot tr

ace c

ode info

rmation, or

the e

nvironm

enta

l cate

gory

on the d

evic

e.

(5) M

ultip

le D

evic

e M

ark

ings w

ill b

e in

sid

e p

are

nth

eses. O

nly

one D

evic

e M

ark

ing c

onta

ined in

pare

nth

eses a

nd s

epara

ted b

y a

"~

" w

ill a

ppear

on a

devic

e. If a

line is

indente

d then it

is a

continuation

of th

e p

revio

us lin

e a

nd the tw

o c

om

bin

ed r

epre

sent th

e e

ntire

Devic

e M

ark

ing for

that devic

e.

(6) L

ead/B

all

Fin

ish -

Ord

era

ble

Devic

es m

ay h

ave m

ultip

le m

ate

rial finis

h o

ptions.

Fin

ish o

ptions a

re s

epara

ted b

y a

vert

ical ru

led lin

e.

Lead/B

all

Fin

ish v

alu

es m

ay w

rap t

o t

wo lin

es if

the f

inis

h

valu

e e

xceeds the m

axim

um

colu

mn w

idth

.

Imp

ort

an

t In

form

ati

on

an

d D

iscla

imer:

The in

form

ation p

rovid

ed o

n this

page r

epre

sents

TI's

know

ledge a

nd b

elie

f as o

f th

e d

ate

that it is

pro

vid

ed. T

I bases it

s k

now

ledge a

nd b

elie

f on in

form

ation

pro

vid

ed b

y t

hird p

art

ies,

and m

akes n

o r

epre

senta

tion o

r w

arr

anty

as t

o t

he a

ccura

cy o

f such info

rmation.

Effort

s a

re u

nderw

ay t

o b

etter

inte

gra

te info

rmation f

rom

third p

art

ies.

TI

has t

aken a

nd

continues t

o t

ake r

easonable

ste

ps t

o p

rovid

e r

epre

senta

tive a

nd a

ccura

te info

rmation b

ut

may n

ot

have c

onducte

d d

estr

uctive t

esting o

r chem

ical analy

sis

on incom

ing m

ate

rials

and c

hem

icals

.

TI and T

I supplie

rs c

onsid

er

cert

ain

info

rmation to b

e p

roprieta

ry, and thus C

AS

num

bers

and o

ther

limited info

rmation m

ay n

ot be a

vaila

ble

for

rele

ase.

In n

o e

vent shall

TI's

lia

bili

ty a

risin

g o

ut of such info

rmation e

xceed t

he tota

l purc

hase p

rice o

f th

e T

I part

(s)

at is

sue in this

docum

ent sold

by T

I to

Custo

mer

on a

n a

nnual basis

.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

UA741CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UA741CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Feb-2014

Pack Materials-Page 1


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UA741CDR SOIC D 8 2500 340.5 338.1 20.6

UA741CPSR SO PS 8 2000 367.0 367.0 38.0


www.ti.com 17-Feb-2014


MECHANICAL DATAMCER001A – JANUARY 1995 – REVISED JANUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

5

4

0.065 (1,65)

0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,16)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2015, Texas Instruments Incorporated

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

LM555

SNAS548D –FEBRUARY 2000–REVISED JANUARY 2015

LM555 Timer

1 Features 3 DescriptionThe LM555 is a highly stable device for generating

1• Direct Replacement for SE555/NE555accurate time delays or oscillation. Additional

• Timing from Microseconds through Hoursterminals are provided for triggering or resetting if

• Operates in Both Astable and Monostable Modes desired. In the time delay mode of operation, the timeis precisely controlled by one external resistor and• Adjustable Duty Cyclecapacitor. For a stable operation as an oscillator, the

• Output Can Source or Sink 200 mAfree running frequency and duty cycle are accurately

• Output and Supply TTL Compatible controlled with two external resistors and onecapacitor. The circuit may be triggered and reset on• Temperature Stability Better than 0.005% per °Cfalling waveforms, and the output circuit can source• Normally On and Normally Off Outputor sink up to 200 mA or drive TTL circuits.

• Available in 8-pin VSSOP Package

Device Information(1)

2 ApplicationsPART NUMBER PACKAGE BODY SIZE (NOM)

• Precision Timing SOIC (8) 4.90 mm × 3.91 mm

• Pulse Generation LM555 PDIP (8) 9.81 mm × 6.35 mm

VSSOP (8) 3.00 mm × 3.00 mm• Sequential Timing

• Time Delay Generation (1) For all available packages, see the orderable addendum atthe end of the datasheet.• Pulse Width Modulation

• Pulse Position Modulation

• Linear Ramp Generator

Schematic Diagram

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM555

SNAS548D –FEBRUARY 2000–REVISED JANUARY 2015 www.ti.com

Table of Contents

7.3 Feature Description................................................... 81 Features .................................................................. 17.4 Device Functional Modes.......................................... 92 Applications ........................................................... 1

8 Application and Implementation ........................ 123 Description ............................................................. 18.1 Application Information............................................ 124 Revision History..................................................... 28.2 Typical Application ................................................. 125 Pin Configuration and Functions ......................... 3

9 Power Supply Recommendations ...................... 156 Specifications......................................................... 410 Layout................................................................... 156.1 Absolute Maximum Ratings ...................................... 4

10.1 Layout Guidelines ................................................. 156.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 156.3 Recommended Operating Conditions....................... 4

11 Device and Documentation Support ................. 166.4 Thermal Information ................................................. 411.1 Trademarks ........................................................... 166.5 Electrical Characteristics .......................................... 511.2 Electrostatic Discharge Caution............................ 166.6 Typical Characteristics .............................................. 611.3 Glossary ................................................................ 167 Detailed Description .............................................. 8

12 Mechanical, Packaging, and Orderable7.1 Overview ................................................................... 8Information ........................................................... 167.2 Functional Block Diagram ......................................... 8

4 Revision History

Changes from Revision C (March 2013) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 13


Product Folder Links: LM555

R

R

R

GND

TRIGGER

OUTPUT

RESET

1

2

3

4

+VCC

DISCHARGE

THRESHOLD

CONTROL

VOLTAGE

8

7

6

5

COMPAR-

ATOR

COMPAR-

ATOR

FLIP FLOP

OUTPUT

STAGE

VREF (INT)

LM555

www.ti.com SNAS548D –FEBRUARY 2000–REVISED JANUARY 2015

5 Pin Configuration and Functions

D, P, and DGK Packages8-Pin PDIP, SOIC, and VSSOP

Top View

Pin Functions

PINI/O DESCRIPTION

NO. NAME

Control Controls the threshold and trigger levels. It determines the pulse width of the output5 Voltage I waveform. An external voltage applied to this pin can also be used to modulate the output

waveform

Discharge Open collector output which discharges a capacitor between intervals (in phase with output).7 I

It toggles the output from high to low when voltage reaches 2/3 of the supply voltage

1 GND O Ground reference voltage

3 Output O Output driven waveform

Reset Negative pulse applied to this pin to disable or reset the timer. When not used for reset4 I

purposes, it should be connected to VCC to avoid false triggering

Threshold Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The6 I

amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop

Trigger Responsible for transition of the flip-flop from set to reset. The output of the timer depends2 I

on the amplitude of the external trigger pulse applied to this pin

8 V+ I Supply voltage with respect to GND



LM555


6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2)

MIN MAX UNIT

LM555CM, LM555CN (4) 1180 mWPower Dissipation (3)

LM555CMM 613 mW

PDIP Package Soldering (10 Seconds) 260 °CSoldering

Vapor Phase (60 Seconds) 215 °CSmall Outline Packages (SOIC andInformationVSSOP) Infrared (15 Seconds) 220 °C

Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.(3) For operating at elevated temperatures the device must be derated above 25°C based on a 150°C maximum junction temperature and a

thermal resistance of 106°C/W (PDIP), 170°C/W (S0IC-8), and 204°C/W (VSSOP) junction to ambient.(4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500 (2) V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) The ESD information listed is for the SOIC package.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply Voltage 18 V

Temperature, TA 0 70 °C

Operating junction temperature, TJ 70 °C

6.4 Thermal Information

LM555

THERMAL METRIC (1) PDIP SOIC VSSOP UNIT

8 PINS

R JA Junction-to-ambient thermal resistance 106 170 204 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.



LM555


6.5 Electrical Characteristics

(TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified) (1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Voltage 4.5 16 V

Supply Current VCC = 5 V, RL = ! 3 6

mAVCC = 15 V, RL = ! 10 15(Low State) (3)

Timing Error, Monostable

Initial Accuracy 1 %

Drift with Temperature RA = 1 k to 100 k", 50 ppm/°C

C = 0.1 #F, (4)

Accuracy over Temperature 1.5 %

Drift with Supply 0.1 % V

Timing Error, Astable

Initial Accuracy 2.25

Drift with Temperature RA, RB =1 k to 100 k", 150 ppm/°C

C = 0.1 #F, (4)

Accuracy over Temperature 3.0%

Drift with Supply 0.30 % /V

Threshold Voltage 0.667 x VCC

Trigger Voltage VCC = 15 V 5 V

VCC = 5 V 1.67 V

Trigger Current 0.5 0.9 #A

Reset Voltage 0.4 0.5 1 V

Reset Current 0.1 0.4 mA

Threshold Current (5) 0.1 0.25 #A

Control Voltage Level VCC = 15 V 9 10 11V

VCC = 5 V 2.6 3.33 4

Pin 7 Leakage Output High 1 100 nA

Pin 7 Sat (6)

Output Low VCC = 15 V, I7 = 15 mA 180 mV

Output Low VCC = 4.5 V, I7 = 4.5 mA 80 200 mV

Output Voltage Drop (Low) VCC = 15 V

ISINK = 10 mA 0.1 0.25 V

ISINK = 50 mA 0.4 0.75 V

ISINK = 100 mA 2 2.5 V

ISINK = 200 mA 2.5 V

VCC = 5 V

ISINK = 8 mA V

ISINK = 5 mA 0.25 0.35 V

(1) All voltages are measured with respect to the ground pin, unless otherwise specified.(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate

conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and ACelectrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is withinthe Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the typicalvalue is a good indication of device performance.

(3) Supply current when output high typically 1 mA less at VCC = 5 V.(4) Tested at VCC = 5 V and VCC = 15 V.(5) This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 M".(6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.



LM555


Electrical Characteristics (continued)

(TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified)(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Voltage Drop (High) ISOURCE = 200 mA, VCC = 15 V 12.5 V

ISOURCE = 100 mA, VCC = 15 V 12.75 13.3 V

VCC = 5 V 2.75 3.3 V

Rise Time of Output 100 ns

Fall Time of Output 100 ns

6.6 Typical Characteristics

Figure 2. Supply Current vs. Supply VoltageFigure 1. Minimum Pulse Width Required For Triggering

Figure 4. Low Output Voltage vs. Output Sink CurrentFigure 3. High Output Voltage vs. Output Source Current



LM555


Typical Characteristics (continued)

Figure 6. Low Output Voltage vs. Output Sink CurrentFigure 5. Low Output Voltage vs. Output Sink Current

Figure 8. Output Propagation Delay vs. Voltage Level ofFigure 7. Output Propagation Delay vs. Voltage Level ofTrigger PulseTrigger Pulse

Figure 10. Discharge Transistor (Pin 7) Voltage vs. SinkFigure 9. Discharge Transistor (Pin 7) Voltage vs. SinkCurrentCurrent



COMPARATOR

TRIGGERFLIP FLOP COMPARATOR

RESET

+Vcc

DISCHARGE

THRESHOLD

Vref (int)

OUTPUT

STAGE

CONTROL

VOLTAGE

OUTPUT

LM555


7 Detailed Description

7.1 Overview

The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals areprovided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlledby one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and dutycycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered andreset on falling waveforms, and the output circuit can source or sink up to 200mA or driver TTL circuits. TheLM555 are available in 8-pin PDIP, SOIC, and VSSOP packages and is a direct replacement for SE555/NE555.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Direct Replacement for SE555/NE555

The LM555 timer is a direct replacement for SE555 and NE555. It is pin-to-pin compatible so that no schematicor layout changes are necessary. The LM555 come in an 8-pin PDIP, SOIC, and VSSOP package.

7.3.2 Timing From Microseconds Through Hours

The LM555 has the ability to have timing parameters from the microseconds range to hours. The time delay ofthe system can be determined by the time constant of the R and C value used for either the monostable orastable configuration. A nomograph is available for easy determination of R and C values for various time delays.

7.3.3 Operates in Both Astable and Monostable Mode

The LM555 can operate in both astable and monostable mode depending on the application requirements.

• Monostable mode: The LM555 timer acts as a “one-shot” pulse generator. The pulse beings when the LM555timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the outputpulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the



LM555


Feature Description (continued)

capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened dependingon the application by adjusting the R and C values.

• Astable (free-running) mode: The LM555 timer can operate as an oscillator and puts out a continuous streamof rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the valuesof RA, RB, and C.

7.4 Device Functional Modes

7.4.1 Monostable Operation

In this mode of operation, the timer functions as a one-shot (Figure 11). The external capacitor is initially helddischarged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC topin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

Figure 11. Monostable

The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of whichtime the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitorand drives the output to its low state. Figure 12 shows the waveforms generated in this mode of operation. Sincethe charge and the threshold level of the comparator are both directly proportional to supply voltage, the timinginterval is independent of supply.

VCC = 5 V Top Trace: Input 5V/Div.

TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div.

RA = 9.1 k" Bottom Trace: Capacitor Voltage 2V/Div.

C = 0.01 #F

Figure 12. Monostable Waveforms

During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuitso long as the trigger input is returned high at least 10 #s before the end of the timing interval. However thecircuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The outputwill then remain in the low state until a trigger pulse is again applied.

When the reset function is not in use, TI recommends connecting the Reset pin to VCC to avoid any possibility offalse triggering.



LM555


Device Functional Modes (continued)

Figure 13 is a nomograph for easy determination of R, C values for various time delays.

Figure 13. Time Delay

7.4.2 Astable Operation

If the circuit is connected as shown in Figure 14 (pins 2 and 6 connected) it will trigger itself and free run as amultivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cyclemay be precisely set by the ratio of these two resistors.

Figure 14. Astable

In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in thetriggered mode, the charge and discharge times, and therefore the frequency are independent of the supplyvoltage.

Figure 15 shows the waveforms generated in this mode of operation.



LM555


Device Functional Modes (continued)

VCC = 5 V Top Trace: Output 5V/Div.

TIME = 20#s/DIV. Bottom Trace: Capacitor Voltage 1V/Div.

RA = 3.9 k"

RB = 3 k"

C = 0.01 #F

Figure 15. Astable Waveforms

The charge time (output high) is given by:

t1 = 0.693 (RA + RB) C (1)

And the discharge time (output low) by:

t2 = 0.693 (RB) C (2)

Thus the total period is:

T = t1 + t2 = 0.693 (RA +2RB) C (3)

The frequency of oscillation is:

(4)

Figure 16 may be used for quick determination of these RC values.

The duty cycle is:

(5)

Figure 16. Free Running Frequency



LM555


8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM555 timer can be used a various configurations, but the most commonly used configuration is inmonostable mode. A typical application for the LM555 timer in monostable mode is to turn on an LED for aspecific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low.This simple application can be modified to fit any application requirement.

8.2 Typical Application

Figure 17 shows the schematic of the LM555 that flashes an LED in monostable mode.

Figure 17. Schematic of Monostable Mode to Flash an LED

8.2.1 Design Requirements

The main design requirement for this application requires calculating the duration of time for which the outputstays high. The duration of time is dependent on the R and C values (as shown in Figure 17) and can becalculated by:

t = 1.1 × R × C seconds (6)

8.2.2 Detailed Design Procedure

To allow the LED to flash on for a noticeable amount of time, a 5 second time delay was chosen for thisapplication. By using Equation 6, RC equals 4.545. If R is selected as 100 k", C = 45.4 µF. The values of R =100 k" and C = 47 µF was selected based on standard values of resistors and capacitors. A momentary pushbutton switch connected to ground is connected to the trigger input with a 10-K current limiting resistor pullup tothe supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to theoutput pin with a current limiting resistor in series from the output of the LM555 to GND. The reset pin is not usedand was connected to the supply voltage.

8.2.2.1 Frequency Divider

The monostable circuit of Figure 11 can be used as a frequency divider by adjusting the length of the timingcycle. Figure 18 shows the waveforms generated in a divide by three circuit.



LM555



VCC = 5 V Top Trace: Input 4 V/Div.

TIME = 20 #s/DIV. Middle Trace: Output 2V/Div.

RA = 9.1 k" Bottom Trace: Capa citor 2V/Div.

C = 0.01 #F

Figure 18. Frequency Divider

8.2.2.2 Additional Information

Lower comparator storage time can be as long as 10 #s when pin 2 is driven fully to ground for triggering. Thislimits the monostable pulse width to 10 #s minimum.

Delay time reset to output is 0.47 #s typical. Minimum reset pulse width must be 0.3 #s, typical.

Pin 7 current switches within 30 ns of the output (pin 3) voltage.

8.2.3 Application Curves

The data shown below was collected with the circuit used in the typical applications section. The LM555 wasconfigured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:

• Top Waveform (Yellow) – Capacitor voltage

• Middle Waveform (Green) – Trigger

• Bottom Waveform (Purple) – Output

As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes lowas soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and Cvalue. For this example, the time delay is 5.17 s.



LM555



Figure 19. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode



LM555


9 Power Supply Recommendations

The LM555 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary toprotect associated circuitry. The minimum recommended capacitor value is 0.1 #F in parallel with a 1-#Felectrolytic capacitor. Place the bypass capacitors as close as possible to the LM555 and minimize the tracelength.

10 Layout

10.1 Layout Guidelines

Standard PCB rules apply to routing the LM555. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitorshould be as close as possible to the LM555. The capacitor used for the time delay should also be placed asclose to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity andsignal integrity.

Figure 20 is the basic layout for various applications.

• C1 – based on time delay calculations

• C2 – 0.01-µF bypass capacitor for control voltage pin

• C3 – 0.1-µF bypass ceramic capacitor

• C4 – 1-µF electrolytic bypass capacitor

• R1 – based on time delay calculations

• U1 – LMC555

10.2 Layout Example

Figure 20. Layout Example



LM555


11 Device and Documentation Support

11.1 Trademarks

All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution


11.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.



PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

27-J

ul-2016

Addendum

-Page 1

PA

CK

AG

ING

IN

FO

RM

AT

ION

Ord

era

ble

Devic

eS

tatu

s

(1)

Packag

e T

yp

eP

ackag

e

Dra

win

g

Pin

sP

ackag

e

Qty

Eco

Pla

n

(2)

Lead

/Ball F

inis

h

(6)

MS

L P

eak T

em

p

(3)

Op

Tem

p (

°C)

Devic

e M

ark

ing

(4/5

)

Sam

ple

s

LM

555-M

WC

AC

TIV

EW

AF

ER

SA

LE

YS

01

Gre

en (

RoH

S

& n

o S

b/B

r)

Call

TI

Level-1-N

A-U

NLIM

-40 to 8

5

LM

555C

MN

RN

DS

OIC

D8

95

TB

DC

all

TI

Call

TI

0 to 7

0LM

555C

M

LM

555C

M/N

OP

BA

CT

IVE

SO

ICD

895

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

SN

Level-1-2

60C

-UN

LIM

0 to 7

0LM

555C

M

LM

555C

MM

NR

ND

VS

SO

PD

GK

81000

TB

DC

all

TI

Call

TI

0 to 7

0Z

55

LM

555C

MM

/NO

PB

AC

TIV

EV

SS

OP

DG

K8

1000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

SN

Level-1-2

60C

-UN

LIM

0 to 7

0Z

55

LM

555C

MM

X/N

OP

BA

CT

IVE

VS

SO

PD

GK

83500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

SN

Level-1-2

60C

-UN

LIM

0 to 7

0Z

55

LM

555C

MX

NR

ND

SO

ICD

82500

TB

DC

all

TI

Call

TI

0 to 7

0LM

555C

M

LM

555C

MX

/NO

PB

AC

TIV

ES

OIC

D8

2500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

SN

Level-1-2

60C

-UN

LIM

0 to 7

0LM

555C

M

LM

555C

N/N

OP

BA

CT

IVE

PD

IPP

840

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

SN

Level-1-N

A-U

NLIM

0 to 7

0LM

555C

N

MC

1455P

1O

BS

OLE

TE

PD

IPP

8T

BD

Call

TI

Call

TI

0 to 7

0LM

555C

N

NE

555V

OB

SO

LE

TE

PD

IPP

8T

BD

Call

TI

Call

TI

0 to 7

0LM

555C

N

(1) T

he m

ark

eting s

tatu

s v

alu

es a

re d

efined a

s follo

ws:

AC

TIV

E:

Pro

duct devic

e r

ecom

mended for

new

desig

ns.

LIF

EB

UY

: T

I has a

nnounced that th

e d

evic

e w

ill b

e d

iscontinued, and a

lifetim

e-b

uy p

eriod is in e

ffect.

NR

ND

: N

ot re

com

mended for

new

desig

ns. D

evic

e is in p

roduction to s

upport

exis

ting c

usto

mers

, but T

I does n

ot re

com

mend u

sin

g this

part

in a

new

desig

n.

PR

EV

IEW

: D

evic

e h

as b

een a

nnounced b

ut is

not in

pro

duction. S

am

ple

s m

ay o

r m

ay n

ot be a

vaila

ble

.

OB

SO

LE

TE

: T

I has d

iscontinued the p

roduction o

f th

e d

evic

e.

(2) E

co P

lan - T

he p

lanned e

co-f

riendly

cla

ssific

ation: P

b-F

ree (R

oH

S),

Pb-F

ree (R

oH

S E

xem

pt)

, or G

reen (R

oH

S &

no S

b/B

r) - p

lease c

heck h

ttp://w

ww

.ti.com

/pro

ductc

onte

nt fo

r th

e la

test availa

bili

ty

info

rmation a

nd a

dditio

nal pro

duct conte

nt deta

ils.

TB

D:

The P

b-F

ree/G

reen c

onvers

ion p

lan h

as n

ot been d

efined.

Pb

-Fre

e (

Ro

HS

): T

I's t

erm

s "

Lead-F

ree"

or

"Pb-F

ree"

mean s

em

iconducto

r pro

ducts

that

are

com

patible

with t

he c

urr

ent

RoH

S r

equirem

ents

for

all

6 s

ubsta

nces,

inclu

din

g t

he r

equirem

ent

that

lead n

ot exceed 0

.1%

by w

eig

ht in

hom

ogeneous m

ate

rials

. W

here

desig

ned to b

e s

old

ere

d a

t hig

h tem

pera

ture

s,

TI P

b-F

ree p

roducts

are

suitable

for

use in s

pecifie

d lead-f

ree p

rocesses.

Pb

-Fre

e (

Ro

HS

Exem

pt)

: T

his

com

ponent has a

RoH

S e

xem

ption for

either

1)

lead-b

ased flip

-chip

sold

er

bum

ps u

sed b

etw

een the d

ie a

nd p

ackage, or

2)

lead-b

ased die

adhesiv

e u

sed b

etw

een

the d

ie a

nd leadfr

am

e. T

he c

om

ponent is

oth

erw

ise c

onsid

ere

d P

b-F

ree (

RoH

S c

om

patible

) as d

efined a

bove.

PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

27-J

ul-2016

Addendum

-Page 2

Gre

en

(R

oH

S &

no

Sb

/Br)

: T

I defines "

Gre

en"

to m

ean P

b-F

ree (

RoH

S c

om

patible

), a

nd f

ree o

f B

rom

ine (

Br)

and A

ntim

ony (

Sb)

based f

lam

e r

eta

rdants

(B

r or

Sb d

o n

ot

exceed 0

.1%

by w

eig

ht

in h

om

ogeneous m

ate

rial)

(3) M

SL, P

eak T

em

p. -

The M

ois

ture

Sensitiv

ity L

evel ra

ting a

ccord

ing to the J

ED

EC

industr

y s

tandard

cla

ssific

ations, and p

eak s

old

er

tem

pera

ture

.

(4) T

here

may b

e a

dditio

nal m

ark

ing, w

hic

h r

ela

tes to the logo, th

e lot tr

ace c

ode info

rmation, or

the e

nvironm

enta

l cate

gory

on the d

evic

e.

(5) M

ultip

le D

evic

e M

ark

ings w

ill b

e in

sid

e p

are

nth

eses. O

nly

one D

evic

e M

ark

ing c

onta

ined in

pare

nth

eses a

nd s

epara

ted b

y a

"~

" w

ill a

ppear

on a

devic

e. If a

line is

indente

d then it

is a

continuation

of th

e p

revio

us lin

e a

nd the tw

o c

om

bin

ed r

epre

sent th

e e

ntire

Devic

e M

ark

ing for

that devic

e.

(6) L

ead/B

all

Fin

ish -

Ord

era

ble

Devic

es m

ay h

ave m

ultip

le m

ate

rial finis

h o

ptions.

Fin

ish o

ptions a

re s

epara

ted b

y a

vert

ical ru

led lin

e.

Lead/B

all

Fin

ish v

alu

es m

ay w

rap t

o t

wo lin

es if

the f

inis

h

valu

e e

xceeds the m

axim

um

colu

mn w

idth

.

Imp

ort

an

t In

form

ati

on

an

d D

iscla

imer:

The in

form

ation p

rovid

ed o

n this

page r

epre

sents

TI's

know

ledge a

nd b

elie

f as o

f th

e d

ate

that it is

pro

vid

ed. T

I bases it

s k

now

ledge a

nd b

elie

f on in

form

ation

pro

vid

ed b

y t

hird p

art

ies,

and m

akes n

o r

epre

senta

tion o

r w

arr

anty

as t

o t

he a

ccura

cy o

f such info

rmation.

Effort

s a

re u

nderw

ay t

o b

etter

inte

gra

te info

rmation f

rom

third p

art

ies.

TI

has t

aken a

nd

continues t

o t

ake r

easonable

ste

ps t

o p

rovid

e r

epre

senta

tive a

nd a

ccura

te info

rmation b

ut

may n

ot

have c

onducte

d d

estr

uctive t

esting o

r chem

ical analy

sis

on incom

ing m

ate

rials

and c

hem

icals

.

TI and T

I supplie

rs c

onsid

er

cert

ain

info

rmation to b

e p

roprieta

ry, and thus C

AS

num

bers

and o

ther

limited info

rmation m

ay n

ot be a

vaila

ble

for

rele

ase.

In n

o e

vent shall

TI's

lia

bili

ty a

risin

g o

ut of such info

rmation e

xceed t

he tota

l purc

hase p

rice o

f th

e T

I part

(s)

at is

sue in this

docum

ent sold

by T

I to

Custo

mer

on a

n a

nnual basis

.



Device PackageType

PackageDrawing


(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1


www.ti.com 21-Oct-2014




LM555CMM VSSOP DGK 8 1000 210.0 185.0 35.0

LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LM555CMX SOIC D 8 2500 367.0 367.0 35.0

LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0


www.ti.com 21-Oct-2014


IMPORTANT NOTICE



























OBSOLETE

LM565, LM565C

www.ti.com SNOSBU1B –MAY 1999–REVISED APRIL 2013

LM565/LM565C Phase Locked LoopCheck for Samples: LM565, LM565C

1FEATURES DESCRIPTIONThe LM565 and LM565C are general purpose phase

2• 200 ppm/°C Frequency Stability of the VCOlocked loops containing a stable, highly linear voltage

• Power Supply Range of ±5 to ±12 Volts withcontrolled oscillator for low distortion FM

100 ppm/% Typical demodulation, and a double balanced phase detector• 0.2% Linearity of Demodulated Output with good carrier suppression. The VCO frequency is

set with an external resistor and capacitor, and a• Linear Triangle Wave with in Phase Zerotuning range of 10:1 can be obtained with the sameCrossings Availablecapacitor. The characteristics of the closed loop

• TTL and DTL Compatible Phase Detector Input system—bandwidth, response speed, capture andand Square Wave Output pull in range—may be adjusted over a wide range

with an external resistor and capacitor. The loop may• Adjustable Hold in Range from ±1% to > ±60%be broken between the VCO and the phase detectorfor insertion of a digital frequency divider to obtainAPPLICATIONSfrequency multiplication.

• Data and Tape ZynchronizationThe LM565H is specified for operation over the

• Modems 55°C to +125°C military temperature range. The

• FSK Demodulation LM565CN is specified for operation over the 0°C to+70°C temperature range.• FM Demodulation

• Frequency Synthesizer

• Tone Decoding

• Frequency Multiplication and Division

• SCA Demodulators

• Telemetry Receivers

• Signal Regeneration

• Coherent Demodulators

Connection Diagram

TO-100 PackageSee Package Number LME

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

OBSOLETE

LM565, LM565C

SNOSBU1B –MAY 1999–REVISED APRIL 2013 www.ti.com

Dual-in-Line PackagePDIP

See Package Number NFF



Product Folder Links: LM565 LM565C

OBSOLETE

LM565, LM565C


Absolute Maximum Ratings (1) (2)

Supply Voltage ±12V

Power Dissipation (3) 1400 mW

Differential Input Voltage ±1V

Operating Temperature Range LM565H 55°C to +125°C

LM565CN 0°C to +70°C

Storage Temperature Range 65°C to +150°C

Lead Temperature (Soldering, 10 sec.) 260°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions forwhich the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electricalspecifications under particular test conditions which ensure specific performance limits. This assumes that the device is within theOperating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indicationof device performance.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability andspecifications.

(3) The maximum junction temperature of the LM565 and LM565C is +150°C. For operation at elevated temperatures, devices in the TO-5package must be derated based on a thermal resistance of +150°C/W junction to ambient or +45°C/W junction to case. Thermalresistance of the dual-in-line package is +85°C/W.

Electrical Characteristics

AC Test Circuit, TA = 25°C, VCC = ±6V

LM565 LM565CParameter Conditions Units

Min Typ Max Min Typ Max

Power Supply Current 8.0 12.5 8.0 12.5 mA

Input Impedance (Pins 2, 3) 4V < V2, V3 < 0V 7 10 5 k!

VCO Maximum Operating Frequency Co = 2.7 pF 300 500 250 500 kHz

VCO Free-Running Frequency Co = 1.5 nFRo = 20 k! 10 0 +10 30 0 +30 %fo = 10 kHz

Operating Frequency 100 200 ppm/°C

Temperature Coefficient

Frequency Drift with0.1 1.0 0.2 1.5 %/V

Supply Voltage

Triangle Wave Output Voltage 2 2.4 3 2 2.4 3 Vp-p

Triangle Wave Output Linearity 0.2 0.5 %

Square Wave Output Level 4.7 5.4 4.7 5.4 Vp-p

Output Impedance (Pin 4) 5 5 k!

Square Wave Duty Cycle 45 50 55 40 50 60 %

Square Wave Rise Time 20 20 ns

Square Wave Fall Time 50 50 ns

Output Current Sink (Pin 4) 0.6 1 0.6 1 mA

VCO Sensitivity fo = 10 kHz 6600 6600 Hz/V

Demodulated Output Voltage (Pin 7) ±10% Frequency Deviation 250 300 400 200 300 450 mVp-p

Total Harmonic Distortion ±10% Frequency Deviation 0.2 0.75 0.2 1.5 %

Output Impedance (Pin 7) 3.5 3.5 k!

DC Level (Pin 7) 4.25 4.5 4.75 4.0 4.5 5.0 V

Output Offset Voltage30 100 50 200 mV

|V7 V6|

Temperature Drift of |V7 V6| 500 500 "V/°C

AM Rejection 30 40 40 dB

Phase Detector Sensitivity KD 0.68 0.68 V/radian



OBSOLETE

LM565, LM565C


Typical Performance Characteristics

Power Supply Current as a Lock Range as a FunctionFunction of Supply Voltage of Input Voltage

Figure 1. Figure 2.

Oscillator OutputVCO Frequency Waveforms

Figure 3. Figure 4.

Phase Shiftvs VCO Frequency as a

Frequency Function of Temperature

Figure 5. Figure 6.



OBSOLETE

LM565, LM565C


Typical Performance Characteristics (continued)Loop Gain

vsLoad Hold in Range as a

Resistance Function of R6–7

Figure 7. Figure 8.



OBSOLETE

LM565, LM565C


Schematic Diagram

Figure 9. Schematic Diagram



OBSOLETE

LM565, LM565C


AC Test Circuit

Note: S1 open for output offset voltage (V7 V6) measurement.

Figure 10. AC Test Circuit



OBSOLETE

LM565, LM565C


Typical Applications

Figure 11. 2400 Hz Synchronous AM Demodulator



OBSOLETE

LM565, LM565C


Figure 12. FSK Demodulator (2025–2225 cps)

Figure 13. FSK Demodulator with DC Restoration



OBSOLETE

LM565, LM565C


Figure 14. Frequency Multiplier (×10)

Figure 15. IRIG Channel 13 Demodulator



OBSOLETE

LM565, LM565C


APPLICATIONS INFORMATION

In designing with phase locked loops such as the LM565, the important parameters of interest are:

FREE RUNNING FREQUENCY

(1)

LOOP GAIN: relates the amount of phase change between the input signal and the VCO signal for a shift in inputsignal frequency (assuming the loop remains in lock). In servo theory, this is called the “velocity error coefficient.”

(2)

The loop gain of the LM565 is dependent on supply voltage, and may be found from:

(3)

fo = VCO frequency in Hz

Vc = total supply voltage to circuit

Loop gain may be reduced by connecting a resistor between pins 6 and 7; this reduces the load impedance onthe output amplifier and hence the loop gain.

HOLD IN RANGE: the range of frequencies that the loop will remain in lock after initially being locked.

where

• fo= free running frequency of VCO

• Vc= total supply voltage to the circuit (4)

THE LOOP FILTER

In almost all applications, it will be desirable to filter the signal at the output of the phase detector (pin 7); thisfilter may take one of two forms:

Figure 16. Simple Lead Filter

Figure 17. Lag-Lead Filter



OBSOLETE

LM565, LM565C


A simple lag filter may be used for wide closed loop bandwidth applications such as modulation following wherethe frequency deviation of the carrier is fairly high (greater than 10%), or where wideband modulating signalsmust be followed.

The natural bandwidth of the closed loop response may be found from:

(5)

Associated with this is a damping factor:

(6)

For narrow band applications where a narrow noise bandwidth is desired, such as applications involving trackinga slowly varying carrier, a lead lag filter should be used. In general, if 1/R1C1 < Ko KD, the damping factor for theloop becomes quite small resulting in large overshoot and possible instability in the transient response of theloop. In this case, the natural frequency of the loop may be found from

(7)

R2 is selected to produce a desired damping factor #, usually between 0.5 and 1.0. The damping factor is foundfrom the approximation:

# $ %2fn (8)

These two equations are plotted for convenience.

Figure 18. Filter Time Constant vs Natural Frequency

Figure 19. Damping Time Constant vs Natural Frequency

Capacitor C2 should be much smaller than C1 since its function is to provide filtering of carrier. In general C2 &0.1 C1.



OBSOLETE

LM565, LM565C


REVISION HISTORY

Changes from Revision A (April 2013) to Revision B Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12



IMPORTANT NOTICE



























Semiconductor Components Industries, LLC, 2006

October, 2006 Rev. 101 Publication Order Number:

MC1496/D

MC1496, MC1496B

Balanced Modulators/Demodulators

These devices were designed for use where the output voltage is a

product of an input voltage (signal) and a switching function (carrier).

Typical applications include suppressed carrier and amplitude

modulation, synchronous detection, FM detection, phase detection,

and chopper applications. See ON Semiconductor Application Note

AN531 for additional design information.

Features

! Excellent Carrier Suppression 65 dB typ @ 0.5 MHz

50 dB typ @ 10 MHz

! Adjustable Gain and Signal Handling

! Balanced Inputs and Outputs

! High Common Mode Rejection 85 dB Typical

! This Device Contains 8 Active Transistors

! Pb Free Package is Available*

http://onsemi.com

SOIC 14

D SUFFIX

CASE 751A14

1

14

1

PDIP 14

P SUFFIX

CASE 646

PIN CONNECTIONS

Signal Input 1

2

3

4

5

6

7

10

11

14

13

12

9

N/C

Output

Bias

Signal Input

Gain Adjust

Gain Adjust

Input Carrier8

VEE

N/C

Output

N/C

Carrier Input

N/C

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

See general marking information in the device marking

section on page 12 of this data sheet.

DEVICE MARKING INFORMATION

MC1496, MC1496B

http://onsemi.com2

IC = 500 kHz, IS = 1.0 kHz

IC = 500 kHzIS = 1.0 kHz

60

40

20

0

Log

Sca

le Id

499 kHz 500 kHz 501 kHz



499 kHz 500 kHz 501 kHz

Line

ar S

cale

10

8.0

6.0

4.0

2.0

0

Figure 1. Suppressed Carrier Output

Waveform

Figure 2. Suppressed Carrier Spectrum

Figure 3. Amplitude Modulation

Output Waveform

Figure 4. Amplitude Modulation Spectrum

MAXIMUM RATINGS (TA = 25"C, unless otherwise noted.)

Rating Symbol Value Unit

Applied Voltage(V6 V8, V10 V1, V12 V8, V12 V10, V8 V4, V8 V1, V10 V4, V6 V10, V2 V5, V3 V5)

V 30 Vdc

Differential Input Signal V8 V10

V4 V1

+5.0

#(5+ I5Re)

Vdc

Maximum Bias Current I5 10 mA

Thermal Resistance, Junction to AirPlastic Dual In Line Package

RJA 100 "C/W

Operating Ambient Temperature Range MC1496MC1496B

TA 0 to +70 40 to +125

"C

Storage Temperature Range Tstg 65 to +150 "C

Electrostatic Discharge Sensitivity (ESD)Human Body Model (HBM)Machine Model (MM)

ESD2000400

V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

MC1496, MC1496B

http://onsemi.com3

ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = 8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh,all input and output characteristics are single ended, unless otherwise noted.) (Note 1)

Characteristic Fig. Note Symbol Min Typ Max Unit

Carrier FeedthroughVC = 60 mVrms sine wave and

offset adjusted to zeroVC = 300 mVpp square wave:

offset adjusted to zerooffset not adjusted

fC = 1.0 kHzfC = 10 MHz

fC = 1.0 kHzfC = 1.0 kHz

5 1 VCFT

40140

0.0420

0.4200

Vrms

mVrms

Carrier SuppressionfS = 10 kHz, 300 mVrms

fC = 500 kHz, 60 mVrms sine wavefC = 10 MHz, 60 mVrms sine wave

5 2 VCS

40

6550

dB

k

Transadmittance Bandwidth (Magnitude) (RL = 50 )Carrier Input Port, VC = 60 mVrms sine wave

fS = 1.0 kHz, 300 mVrms sine waveSignal Input Port, VS = 300 mVrms sine wave|VC| = 0.5 Vdc

8 8 BW3dB

300

80

MHz

Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 V/V

Single Ended Input Impedance, Signal Port, f = 5.0 MHzParallel Input ResistanceParallel Input Capacitance

6

ripcip

2002.0

kpF

Single Ended Output Impedance, f = 10 MHzParallel Output ResistanceParallel Output Capacitance

6

ropcoo

405.0

kpF

Input Bias Current 7

IbSIbC

1212

3030

A

IbS

I1 I42

; IbC

I8 I102

Input Offset CurrentIioS = I1 I4; IioC = I8 I10

7 $ IioS$IioC$

0.70.7

7.07.0

A

Average Temperature Coefficient of Input Offset Current(TA = 55"C to +125"C)

7 $TCIio$ 2.0 nA/"C

Output Offset Current (I6 I9) 7 $ Ioo$ 14 80 A

Average Temperature Coefficient of Output Offset Current(TA = 55"C to +125"C)

7 $TCIoo$ 90 nA/"C

Common Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV 5.0 Vpp

Common Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 ACM 85 dB

Common Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 Vout 8.0 Vpp

Differential Output Voltage Swing Capability 10 Vout 8.0 Vpp

Power Supply Current I6 +I12Power Supply Current I14

7 6 ICCIEE

2.03.0

4.05.0

mAdc

DC Power Dissipation 7 5 PD 33 mW

1. Tlow = 0"C for MC1496 Thigh = +70"C for MC1496= 40"C for MC1496B = +125"C for MC1496B

MC1496, MC1496B

http://onsemi.com4

GENERAL OPERATING INFORMATION

Carrier Feedthrough

Carrier feedthrough is defined as the output voltage at

carrier frequency with only the carrier applied

(signal voltage = 0).

Carrier null is achieved by balancing the currents in the

differential amplifier by means of a bias trim potentiometer

(R1 of Figure 5).

Carrier Suppression

Carrier suppression is defined as the ratio of each

sideband output to carrier output for the carrier and signal

voltage levels specified.

Carrier suppression is very dependent on carrier input

level, as shown in Figure 22. A low value of the carrier does

not fully switch the upper switching devices, and results in

lower signal gain, hence lower carrier suppression. A higher

than optimum carrier level results in unnecessary device and

circuit carrier feedthrough, which again degenerates the

suppression figure. The MC1496 has been characterized

with a 60 mVrms sinewave carrier input signal. This level

provides optimum carrier suppression at carrier frequencies

in the vicinity of 500 kHz, and is generally recommended for

balanced modulator applications.

Carrier feedthrough is independent of signal level, VS.

Thus carrier suppression can be maximized by operating

with large signal levels. However, a linear operating mode

must be maintained in the signal input transistor pair % or

harmonics of the modulating signal will be generated and

appear in the device output as spurious sidebands of the

suppressed carrier. This requirement places an upper limit

on input signal amplitude (see Figure 20). Note also that an

optimum carrier level is recommended in Figure 22 for good

carrier suppression and minimum spurious sideband

generation.

At higher frequencies circuit layout is very important in

order to minimize carrier feedthrough. Shielding may be

necessary in order to prevent capacitive coupling between

the carrier input leads and the output leads.

Signal Gain and Maximum Input Level

Signal gain (single ended) at low frequencies is defined

as the voltage gain,

AVS

VoV

S

RLRe2re

where re 26 mVI5(mA)

A constant dc potential is applied to the carrier input

terminals to fully switch two of the upper transistors “on”

and two transistors “off” (VC = 0.5 Vdc). This in effect

forms a cascode differential amplifier.

Linear operation requires that the signal input be below a

critical value determined by RE and the bias current I5.

VS I5 RE (Volts peak)

Note that in the test circuit of Figure 10, VS corresponds to

a maximum value of 1.0 V peak.

Common Mode Swing

The common mode swing is the voltage which may be

applied to both bases of the signal differential amplifier,

without saturating the current sources or without saturating

the differential amplifier itself by swinging it into the upper

switching devices. This swing is variable depending on the

particular circuit and biasing conditions chosen.

Power Dissipation

Power dissipation, PD, within the integrated circuit

package should be calculated as the summation of the

voltage current products at each port, i.e. assuming

V12 = V6, I5 = I6 = I12 and ignoring base current,

PD = 2 I5 (V6 V14) + I5)V5 V14 where subscripts refer

to pin numbers.

Design Equations

The following is a partial list of design equations needed

to operate the circuit with other supply voltages and input

conditions.

A. Operating Current

The internal bias currents are set by the conditions at Pin 5.

Assume:

I5 = I6 = I12,

IB IC for all transistors

then :

R5V

I5500

where: R5 is the resistor betweenwhere: Pin 5 and groundwhere: = 0.75 at TA = +25"C

The MC1496 has been characterized for the condition

I5 = 1.0 mA and is the generally recommended value.

B. Common Mode Quiescent Output Voltage

V6 = V12 = V+ I5 RL

Biasing

The MC1496 requires three dc bias voltage levels which

must be set externally. Guidelines for setting up these three

levels include maintaining at least 2.0 V collector base bias

on all transistors while not exceeding the voltages given in

the absolute maximum rating table;

30 Vdc [(V6, V12) (V8, V10)] % 2 Vdc

30 Vdc [(V8, V10) (V1, V4)] % 2.7 Vdc

30 Vdc [(V1, V4) (V5)] % 2.7 Vdc

The foregoing conditions are based on the following

approximations:

V6 = V12, V8 = V10, V1 = V4

MC1496, MC1496B

http://onsemi.com5

Bias currents flowing into Pins 1, 4, 8 and 10 are transistor

base currents and can normally be neglected if external bias

dividers are designed to carry 1.0 mA or more.

Transadmittance Bandwidth

Carrier transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

21Cio (each sideband)

vs (signal) $ Vo 0

Signal transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

21Sio (signal)

vs (signal)$Vc 0.5 Vdc, Vo 0

Coupling and Bypass Capacitors

Capacitors C1 and C2 (Figure 5) should be selected for a

reactance of less than 5.0 at the carrier frequency.

Output Signal

The output signal is taken from Pins 6 and 12 either

balanced or single ended. Figure 11 shows the output levels

of each of the two output sidebands resulting from variations

in both the carrier and modulating signal inputs with a

single ended output connection.

Negative Supply

VEE should be dc only. The insertion of an RF choke in

series with VEE can enhance the stability of the internal

current sources.

Signal Port Stability

Under certain values of driving source impedance,

oscillation may occur. In this event, an RC suppression

network should be connected directly to each input using

short leads. This will reduce the Q of the source tuned

circuits that cause the oscillation.

Signal Input(Pins 1 and 4)

510

10 pF

An alternate method for low frequency applications is to

insert a 1.0 k resistor in series with the input (Pins 1, 4). In

this case input current drift may cause serious degradation

of carrier suppression.

NOTE: Shielding of input and output leads may be neededto properly perform these tests.

Figure 5. Carrier Rejection and Suppression Figure 6. Input Output Impedance

Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth

0.01F2.0 k

−8.0 Vdc

I6

I9

1.0 k

I7I8

6.8 k

Zout

+Vo+

+VoI9

3

RL3.9 k

VCC12 Vdc

8

C10.1 F

MC1496

1.0 k2

Re

1.0 k

C20.1 F

51

10 k

ModulatingSignal Input

CarrierInput

VC

Carrier Null

515110 k

50 k

R1

VS −V o

RL3.9 k

I6

I4

6

14 5

12

−

2

Re = 1.0 k

3

Zin

0.5 V 810

I1

41

−V o101 6

4

14 5

12

6.8 k

V−I10

I5

−8.0 VdcVEE

1.0 k

MC1496

MC1496MC1496 6

14 5

12

I106.8 k

−8.0 VdcVEE

VCC12 Vdc

2

Re = 1.0 k

3

1.0 k

ModulatingSignal Input

CarrierInput

VC

VS

0.1 F

0.1 F

1.0 k

51

1.0 k

14 5

6

12

1.0 k2 3

Re

VCC12 Vdc

2.0 k

+Vo

−V o

6.8 k

10 k

Carrier Null

5110 k

50 k

V−

−8.0 VdcVEE

50 50810

41

810

41

51

TEST CIRCUITS

MC1496, MC1496B

http://onsemi.com6

+Vo

33.9 k

VCC12 Vdc

8

MC1496

2

Re = 1.0 k1.0 k

0.5 V

1.0 k

50

+

VS−V o

101 6

4

14 5

12

6.8 k

−8.0 VdcVEE

3.9 k

−

ACM 20 log$ Vo$

VS

Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing

V

, OU

TPU

T A

MP

LITU

DE

OF

EA

CH

SID

EB

AN

D (

Vrm

s)O

r ,

PAR

ALL

EL

INP

UT

RE

SIS

TAN

CE

(k

ip

Figure 11. Sideband Output versus

Carrier Levels

Figure 12. Signal Port Parallel Equivalent

Input Resistance versus Frequency

c ,

PA

RA

LLE

L IN

PU

T C

APA

CIT

AN

CE

(pF

)ip

c

, PA

RA

LLE

L O

UTP

UT

CA

PAC

ITA

NC

E (

pF)

o p

Figure 13. Signal Port Parallel Equivalent

Input Capacitance versus Frequency

Figure 14. Single Ended Output Impedance

versus Frequency

TYPICAL CHARACTERISTICS

Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25"C, unless otherwise noted.

I5 =1.0 mA

+Vo

33.9 k

VCC12 Vdc

2

Re = 1.0 k

−V o

6

14 5

12

6.8 k

−8.0 VdcVEE

3.9 k0.5 V

+ −

1.0 k

1.0 k

VS

50

1.0

2.0

0

140

−rip

+rip

14

12

10

8.0

6.0

4.0

010010

120

0

101.0

20

5.0 100

40

50

1.0

1.0f, FREQUENCY (MHz)

80

200

2.0

5.0

10

100

100

500

1.0 M

60

50

100102.0

3.0

2.0

1.0

0

5.0

400 mV

Signal Input = 600 mV

4.0

VC, CARRIER LEVEL (mVrms)

1.6

0

0.8

0

0.4

1.2

10050 150

5.0

100 mV

200 mV

300 mV

5020

f, FREQUENCY (MHz)f, FREQUENCY (MHz)

MC1496

8

1014

rop

&)

r ,

PA

RA

LLE

L O

UTP

UT

RE

SIS

TAN

CE

(k

op&

)

cop

MC1496, MC1496B

http://onsemi.com7

−30

f, FREQUENCY (MHz)

20

10

0

−10

−20

0.1 1.0 10 1000.01

RL = 3.9 kRe = 500

RL = 3.9 kRe = 2.0 k

|VC| = 0.5 VdcRL = 500 Re = 1.0 k

RL = 3.9 k (StandardRe = 1.0 k Test Circuit)

A

, S

ING

LEE

ND

ED

VO

LTA

GE

GA

IN (

dB)

V S

1001.0

Side Band

0.3

0.4

01000

fC, CARRIER FREQUENCY (MHz)

0.6

0.9

1.0

10

0.8

0.7

0.1

0.2

0.5

0.1

21, T

RA

NS

AD

MIT

TA

NC

E (

mm

ho)

800

fC #% 3fS

800600400200

VS, INPUT SIGNAL AMPLITUDE (mVrms)

fC #% 2fS

0

60

50

40

30

20

10

70

SU

PP

RE

SS

ION

BE

LOW

EA

CH

FU

ND

AM

EN

TAL

CA

RR

IER

SID

EB

AN

D (

dB)

fC

2fC

505.00.05 0.1 0.5 1.0 10

3fC

0

60

50

40

30

20

10

70


SU

PP

RE

SS

ION

BE

LOW

EA

CH

FU

ND

AM

EN

TAL

CA

RR

IER

SID

EB

AN

D (

dB)

TA, AMBIENT TEMPERATURE ("C)

MC1496(70"C)

−75 −50

60

7550250−25

50

40

30

20

10

100 125 150 17570

CS

V

, C

AR

RIE

R S

UP

PR

ES

ION

(dB

)

AV RL

Re 2re

TYPICAL CHARACTERISTICS (continued)

Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25"C, unless otherwise noted.

0.1

5010

10

1.0

0.011.0 5.00.05 0.1 0.5


V

,

CA

RR

IER

OU

TPU

T V

OLT

AG

E (

mV

rms)

CFT

Signal Port

0

Figure 15. Sideband and Signal Port

Transadmittances versus Frequency

Figure 16. Carrier Suppression

versus Temperature

Figure 17. Signal Port Frequency Response Figure 18. Carrier Suppression

versus Frequency

Figure 19. Carrier Feedthrough

versus Frequency

Figure 20. Sideband Harmonic Suppression

versus Input Signal Level

'

21 IoutVin$Vout 0|VC| 0.5Vdc

21 Iout(EachSideband)

Vin(Signal) $Vout 0

Sideband Transadmittance

Signal Port Transadmittance

MC1496, MC1496B

http://onsemi.com8

500100 4003000 200VC, CARRIER INPUT LEVEL (mVrms)

fC = 10 MHz

0

60

50

40

30

20

10

70

CS

V

, C

AR

RIE

R S

UP

PR

ES

SIO

N (

dB)

2fC #% fS

2fC #% 2fS

3fC #% fS

fC, CARRIER FREQUENCY (MHz)50101.0 5.00.05 0.1 0.5

0

60

50

40

30

20

10

70

SU

PP

RE

SS

ION

BE

LOW

EA

CH

FU

ND

AM

EN

TAL

CA

RR

IER

SID

EB

AN

D (

dB)

Figure 21. Suppression of Carrier Harmonic

Sidebands versus Carrier Frequency

Figure 22. Carrier Suppression versus

Carrier Input Level

fC = 500 kHz

OPERATIONS INFORMATION

The MC1496, a monolithic balanced modulator circuit, is

shown in Figure 23.

This circuit consists of an upper quad differential amplifier

driven by a standard differential amplifier with dual current

sources. The output collectors are cross coupled so that

full wave balanced multiplication of the two input voltages

occurs. That is, the output signal is a constant times the

product of the two input signals.

Mathematical analysis of linear ac signal multiplication

indicates that the output spectrum will consist of only the sum

and difference of the two input frequencies. Thus, the device

may be used as a balanced modulator, doubly balanced mixer,

product detector, frequency doubler, and other applications

requiring these particular output signal characteristics.

The lower differential amplifier has its emitters connected

to the package pins so that an external emitter resistance may

be used. Also, external load resistors are employed at the

device output.

Signal Levels

The upper quad differential amplifier may be operated

either in a linear or a saturated mode. The lower differential

amplifier is operated in a linear mode for most applications.

For low level operation at both input ports, the output

signal will contain sum and difference frequency

components and have an amplitude which is a function of the

product of the input signal amplitudes.

For high level operation at the carrier input port and

linear operation at the modulating signal port, the output

signal will contain sum and difference frequency

components of the modulating signal frequency and the

fundamental and odd harmonics of the carrier frequency.

The output amplitude will be a constant times the

modulating signal amplitude. Any amplitude variations in

the carrier signal will not appear in the output.

The linear signal handling capabilities of a differential

amplifier are well defined. With no emitter degeneration, the

maximum input voltage for linear operation is

approximately 25 mV peak. Since the upper differential

amplifier has its emitters internally connected, this voltage

applies to the carrier input port for all conditions.

Since the lower differential amplifier has provisions for an

external emitter resistance, its linear signal handling range

may be adjusted by the user. The maximum input voltage for

linear operation may be approximated from the following

expression:

V = (I5) (RE) volts peak.

This expression may be used to compute the minimum

value of RE for a given input voltage amplitude.

SignalInput

CarrierInput

8 (+)

500500 50014VEE

Bias

VC

(Pin numbersper G package)

Vo,Output

(−) 12

2GainAdjust

3

(+) 6

VS

10 (−)

4 (−)

1 (+)

5

−Vo

Re 1.0 k2

12 Vdc

RL3.9 k

+Vo

VEE

−8.0 Vdc

6.8 kI5

14

0.1 F

12

MC14966

8

1.0 k1.0 k

50 k

51

10 k10 k

0.1 FCarrierInput

ModulatingSignalInput

VS

VC

Carrier Null

51

3

51

4

1

10

5

RL3.9 k

Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit

MC1496, MC1496B

http://onsemi.com9

Table 1. Voltage Gain and Output Frequencies

Carrier Input Signal (VC) Approximate Voltage Gain Output Signal Frequency(s)

Low level dc

RL VC

2(RE 2re) KTq fM

High level dcRL

RE 2re

fM

Low level ac

RL VC

(rms)

2 2 KTq (RE 2re)

fC #% fM

High level ac0.637 RLR

E 2re

fC #% fM, 3fC #% fM, 5fC #% fM, . . .

2. Low level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs,

fC + fM and fC fM.4. All gain expressions are for a single ended output. For a differential output connection, multiply each expression by two.5. RL = Load resistance.6. RE = Emitter resistance between Pins 2 and 3.7. re = Transistor dynamic emitter resistance, at 25"C;

re 26 mV

I5 (mA)

8. K = Boltzmann(s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.

The gain from the modulating signal input port to the

output is the MC1496 gain parameter which is most often of

interest to the designer. This gain has significance only when

the lower differential amplifier is operated in a linear mode,

but this includes most applications of the device.

As previously mentioned, the upper quad differential

amplifier may be operated either in a linear or a saturated

mode. Approximate gain expressions have been developed

for the MC1496 for a low level modulating signal input and

the following carrier input conditions:

1) Low level dc

2) High level dc

3) Low level ac

4) High level ac

These gains are summarized in Table 1, along with the

frequency components contained in the output signal.

APPLICATIONS INFORMATIONDouble sideband suppressed carrier modulation is the

basic application of the MC1496. The suggested circuit for

this application is shown on the front page of this data sheet.

In some applications, it may be necessary to operate the

MC1496 with a single dc supply voltage instead of dual

supplies. Figure 25 shows a balanced modulator designed

for operation with a single 12 Vdc supply. Performance of

this circuit is similar to that of the dual supply modulator.

AM Modulator

The circuit shown in Figure 26 may be used as an

amplitude modulator with a minor modification.

All that is required to shift from suppressed carrier to AM

operation is to adjust the carrier null potentiometer for the

proper amount of carrier insertion in the output signal.

However, the suppressed carrier null circuitry as shown in

Figure 26 does not have sufficient adjustment range.

Therefore, the modulator may be modified for AM

operation by changing two resistor values in the null circuit

as shown in Figure 27.

Product Detector

The MC1496 makes an excellent SSB product detector

(see Figure 28).

This product detector has a sensitivity of 3.0 V and a

dynamic range of 90 dB when operating at an intermediate

frequency of 9.0 MHz.

The detector is broadband for the entire high frequency

range. For operation at very low intermediate frequencies

down to 50 kHz the 0.1 F capacitors on Pins 8 and 10 should

be increased to 1.0 F. Also, the output filter at Pin 12 can

be tailored to a specific intermediate frequency and audio

amplifier input impedance.

As in all applications of the MC1496, the emitter

resistance between Pins 2 and 3 may be increased or

decreased to adjust circuit gain, sensitivity, and dynamic

range.

This circuit may also be used as an AM detector by

introducing carrier signal at the carrier input and an AM

signal at the SSB input.

The carrier signal may be derived from the intermediate

frequency signal or generated locally. The carrier signal may

MC1496, MC1496B

http://onsemi.com10

be introduced with or without modulation, provided its level

is sufficiently high to saturate the upper quad differential

amplifier. If the carrier signal is modulated, a 300 mVrms

input level is recommended.

Doubly Balanced Mixer

The MC1496 may be used as a doubly balanced mixer

with either broadband or tuned narrow band input and output

networks.

The local oscillator signal is introduced at the carrier input

port with a recommended amplitude of 100 mVrms.

Figure 29 shows a mixer with a broadband input and a

tuned output.

Frequency Doubler

The MC1496 will operate as a frequency doubler by

introducing the same frequency at both input ports.

Figures 30 and 31 show a broadband frequency doubler

and a tuned output very high frequency (VHF) doubler,

respectively.

Phase Detection and FM Detection

The MC1496 will function as a phase detector. High level

input signals are introduced at both inputs. When both inputs

are at the same frequency the MC1496 will deliver an output

which is a function of the phase difference between the two

input signals.

An FM detector may be constructed by using the phase

detector principle. A tuned circuit is added at one of the

inputs to cause the two input signals to vary in phase as a

function of frequency. The MC1496 will then provide an

output which is a function of the input signal frequency.

VS

DSB

MC1496

VCC12 Vd

−

R1

+

Carrier Input60 mVrms

CarrierInput

1.0 k1.0 k

Carrier Null

Carrier Adjust

1.0 k

Re 1.0 k2RL

3.9 k3 RL3.9

−

+

12

6

6.8 kI5VEE−8.0 Vdc

10 k10 k 51 51Modulating

SignalInput

VC

14 5

0.1 F

0.1 F

50 k+ −

MC1496

Output

0.1 F

0.1 F0.1 F

VCC12 Vdc

10 k 100 100

10 k

3.0 k 3.0 k1.0 k

1.3 k820

50 k10 k

10 F15 V

Signal Input300 mVrms

Modulating

CarrierNull

+25 F

15 V51

25 F15 V

2 3

14 5

ModulatingSignalInput

VS

VC

1.0 F

CarrierInput

50 k

750 51 51750

VEE−8.0 Vdc

15 6.8 k

RL3.9 k

Re 1.0 k2 3

14 5

0.1 F

−Vo

+Vo

VCC12 Vdc

51

51

1.0 k1.0 k

MC1496

2 3

14 5

MC1496

1.3 k820

1.0 k

Carrier Input300 mVrms

SSB Input

51

100 3.0 k 3.0 k

0.005F

10 k

0.1F

1.0 k

0.1 F0.1 F

0.1 F

0.1 F

VCC12 Vdc

AFOutp

RL 10

0.005F

TYPICAL APPLICATIONS

1.0 k

8

4

1

10

12

6

12

6

12

6

RL3.9 k

8

4

110

8

41

108

4

1

10

Figure 25. Balanced Modulator

(12 Vdc Single Supply)

Figure 26. Balanced Modulator Demodulator

Figure 27. AM Modulator Circuit Figure 28. Product Detector

(12 Vdc Single Supply)

1.0 k

0.005F

MC1496, MC1496B

http://onsemi.com11

(f

+ 2

f )

C

S

C

S

C

S

RFC100 H

(2f

− 2

f )

fCfS

fC #% fS

fC #% nfSnfC

nfC #% nfS

DEFINITIONS

Figure 29. Doubly Balanced Mixer

(Broadband Inputs, 9.0 MHz Tuned Output)

Figure 30. Low Frequency Doubler

Frequency Balanced Modulator Spectrum

L1 = 44 Turns AWG No. 28 Enameled Wire, Woundon Micrometals Type 44 6 Toroid Core.

VCC+8.0 Vdc1.0 k1.0 k

Null Adjust

0.001 F

512 3

5

6.8 k

VEE−8.0 Vdc

10 k 5151

10 k

MC1496

0.001 F

LocalOscillator

Input

RF Input

100 mVrms

50 k

0.001 F9.5 F

L1

5.0−80pF 90−480 pF

9.0 MHzOutputRL = 50

0.01F

VCC12 Vdc

3.9 k

3.9 k

5

2 3

MC1496

6.8 k

I5VEE−8.0 Vdc

1.0 k

10 k 10 k

100

100

100 F 15 Vdc

100 F25 Vdc

+−

−+

100C2

100 F15 Vdc Max

1.0 k

1.0 k

C2

50 k

Balance

Input15 mVrms

L1 = 1 Turn AWGNo. 18 Wire, 7/32) IDBalance

MC1496

300 MHzOutputRL = 50

1.0−10 pF

L118 nH

RFC0.68 H

0.001F

0.001F

1.0 k1.0 k

VCC+8.0 Vdc

Outp

100

0.001 F

150 MHz Input

10 k10 k 100

50 k

2 3

18 pF

6.8 k

AM

PLI

TUD

E

(f ) C

C

S

100

V+

VEE−8.0 Vdc

(f

− 2

f )

C

S

(f

− f

)

(f

+ f

)

(2f

−

2f

)

(2f

+ 2

f )

(2f

+

2f

)

(3f

−

2f

)

(3f

−

f )

(3f

)

(3f

+

f )

(3f

+

2f

)

C

C

S

C

S

C

S

C

S

C

S C

S

C

S

(2f

) C

8

4

1

10

12

68

4

1

10

8

4

1

10

12

6

14 5

1414

12

6

Figure 31. 150 to 300 MHz Doubler

Carrier FundamentalModulating SignalFundamental Carrier Sidebands

Fundamental Carrier Sideband HarmonicsCarrier HarmonicsCarrier Harmonic Sidebands

1.0−10 pF

MC1496, MC1496B

http://onsemi.com12

ORDERING INFORMATION

Device Package Shipping†

MC1496D SOIC 14

55 Units/RailMC1496DG SOIC 14(Pb Free)

MC1496DR2 SOIC 14

2500 Tape & ReelMC1496DR2G SOIC 14(Pb Free)

MC1496P PDIP 14

25 Units/Rail

MC1496PG PDIP 14(Pb Free)

MC1496P1 PDIP 14

MC1496P1G PDIP 14(Pb Free)

MC1496BD SOIC 14

55 Units/RailMC1496BDG SOIC 14(Pb Free)

MC1496BDR2 SOIC 14

2500 Tape & ReelMC1496BDR2G SOIC 14(Pb Free)

MC1496BP PDIP 14

25 Units/RailMC1496BPG PDIP 14(Pb Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

PDIP 14

P SUFFIX

CASE 646

SOIC 14

D SUFFIX

CASE 751A

MARKING DIAGRAMS

A = Assembly LocationWL = Wafer LotYY, Y = YearWW = Work WeekG = Pb Free Package

1

14

MC1496DGAWLYWW

1

14

MC1496BDGAWLYWW

1

14

MC1496BPAWLYYWWG

1

14

MC1496PAWLYYWWG

MC1496, MC1496B

http://onsemi.com13

PACKAGE DIMENSIONS

SOIC 14CASE 751A 03

ISSUE H

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.127(0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIALCONDITION.

A

B

G

P 7 PL

14 8

71

M0.25 (0.010) B M

SBM0.25 (0.010) A ST

T

FR X 45

SEATINGPLANE

D 14 PL K

C

JM

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

7X

*For additional information on our Pb Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

MC1496, MC1496B

http://onsemi.com14

PDIP 14CASE 646 06

ISSUE P

1 7

14 8

B

A DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56B 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53F 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43L

M 10 10 N 0.015 0.039 0.38 1.01

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

F

H G DK

C

SEATINGPLANE

N

T

14 PL

M0.13 (0.005)

L

M

J0.290 0.310 7.37 7.87

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800 282 9855 Toll FreeUSA/Canada

Japan: ON Semiconductor, Japan Customer Focus Center2 9 1 Kamimeguro, Meguro ku, Tokyo, Japan 153 0051Phone: 81 3 5773 3850

MC1496/D

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303 675 2175 or 800 344 3860 Toll Free USA/CanadaFax: 303 675 2176 or 800 344 3867 Toll Free USA/CanadaEmail: [email protected]

ON Semiconductor Website: http://onsemi.com

Order Literature: http://www.onsemi.com/litorder

For additional information, please contact yourlocal Sales Representative.

Data sheet acquired from Harris SemiconductorSCHS026C Revised September 2003

The CD4016 “B” Series types are supplied in

14-lead hermetic dual-in-line ceramic packages

(F3A suffix), 14-lead dual-in-line plastic

packages (E suffix), 14-lead small-outline

packages (M, MT, M96, and NSR suffixes), and

14-lead thin shrink small-outline packages (PW

and PWR suffixes).

Copyright 2003, Texas Instruments Incorporated

PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

10-J

un-2

014

Addendum

-Page 1

PA

CK

AG

ING

IN

FO

RM

AT

ION

Ord

era

ble

Devic

eS

tatu

s

(1)

Packag

e T

yp

eP

ackag

e

Dra

win

g

Pin

sP

ackag

e

Qty

Eco

Pla

n

(2)

Lead

/Ball F

inis

h

(6)

MS

L P

eak T

em

p

(3)

Op

Tem

p (

°C)

Devic

e M

ark

ing

(4/5

)

Sam

ple

s

5962-9

064001C

AA

CT

IVE

CD

IPJ

14

1T

BD

A42

N / A

for

Pkg T

ype

-55 to 1

25

5962-9

064001C

A

CD

4016B

F3A

CD

4016B

EA

CT

IVE

PD

IPN

14

25

Pb-F

ree

(RoH

S)

CU

NIP

DA

UN

/ A

for

Pkg T

ype

-55 to 1

25

CD

4016B

E

CD

4016B

EE

4A

CT

IVE

PD

IPN

14

25

Pb-F

ree

(RoH

S)

CU

NIP

DA

UN

/ A

for

Pkg T

ype

-55 to 1

25

CD

4016B

E

CD

4016B

FA

CT

IVE

CD

IPJ

14

1T

BD

A42

N / A

for

Pkg T

ype

-55 to 1

25

CD

4016B

F

CD

4016B

F3A

AC

TIV

EC

DIP

J14

1T

BD

A42

N / A

for

Pkg T

ype

-55 to 1

25

5962-9

064001C

A

CD

4016B

F3A

CD

4016B

MA

CT

IVE

SO

ICD

14

50

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

M

CD

4016B

M96

AC

TIV

ES

OIC

D14

2500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

M

CD

4016B

M96G

4A

CT

IVE

SO

ICD

14

2500

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

M

CD

4016B

MG

4A

CT

IVE

SO

ICD

14

50

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

M

CD

4016B

MT

AC

TIV

ES

OIC

D14

250

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

M

CD

4016B

NS

RA

CT

IVE

SO

NS

14

2000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CD

4016B

CD

4016B

PW

AC

TIV

ET

SS

OP

PW

14

90

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CM

016B

CD

4016B

PW

RA

CT

IVE

TS

SO

PP

W14

2000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CM

016B

CD

4016B

PW

RG

4A

CT

IVE

TS

SO

PP

W14

2000

Gre

en (

RoH

S

& n

o S

b/B

r)

CU

NIP

DA

ULevel-1-2

60C

-UN

LIM

-55 to 1

25

CM

016B

(1) T

he m

ark

eting s

tatu

s v

alu

es a

re d

efined a

s follo

ws:

AC

TIV

E:

Pro

duct devic

e r

ecom

mended for

new

desig

ns.

LIF

EB

UY

: T

I has a

nnounced that th

e d

evic

e w

ill b

e d

iscontinued, and a

lifetim

e-b

uy p

eriod is in e

ffect.

NR

ND

: N

ot re

com

mended for

new

desig

ns. D

evic

e is in p

roduction to s

upport

exis

ting c

usto

mers

, but T

I does n

ot re

com

mend u

sin

g this

part

in a

new

desig

n.

PR

EV

IEW

: D

evic

e h

as b

een a

nnounced b

ut is

not in

pro

duction. S

am

ple

s m

ay o

r m

ay n

ot be a

vaila

ble

.

OB

SO

LE

TE

: T

I has d

iscontinued the p

roduction o

f th

e d

evic

e.

PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

10-J

un-2

014

Addendum

-Page 2

(2) E

co P

lan - T

he p

lanned e

co-f

riendly

cla

ssific

ation: P

b-F

ree (R

oH

S),

Pb-F

ree (R

oH

S E

xem

pt)

, or G

reen (R

oH

S &

no S

b/B

r) - p

lease c

heck h

ttp://w

ww

.ti.com

/pro

ductc

onte

nt fo

r th

e la

test availa

bili

ty

info

rmation a

nd a

dditio

nal pro

duct conte

nt deta

ils.

TB

D:

The P

b-F

ree/G

reen c

onvers

ion p

lan h

as n

ot been d

efined.

Pb

-Fre

e (

Ro

HS

): T

I's t

erm

s "

Lead-F

ree"

or

"Pb-F

ree"

mean s

em

iconducto

r pro

ducts

that

are

com

patible

with t

he c

urr

ent

RoH

S r

equirem

ents

for

all

6 s

ubsta

nces,

inclu

din

g t

he r

equirem

ent

that

lead n

ot exceed 0

.1%

by w

eig

ht in

hom

ogeneous m

ate

rials

. W

here

desig

ned to b

e s

old

ere

d a

t hig

h tem

pera

ture

s,

TI P

b-F

ree p

roducts

are

suitable

for

use in s

pecifie

d lead-f

ree p

rocesses.

Pb

-Fre

e (

Ro

HS

Exem

pt)

: T

his

com

ponent has a

RoH

S e

xem

ption for

either

1)

lead-b

ased flip

-chip

sold

er

bum

ps u

sed b

etw

een the d

ie a

nd p

ackage, or

2)

lead-b

ased die

adhesiv

e u

sed b

etw

een

the d

ie a

nd leadfr

am

e. T

he c

om

ponent is

oth

erw

ise c

onsid

ere

d P

b-F

ree (

RoH

S c

om

patible

) as d

efined a

bove.

Gre

en

(R

oH

S &

no

Sb

/Br)

: T

I defines "

Gre

en"

to m

ean P

b-F

ree (

RoH

S c

om

patible

), a

nd f

ree o

f B

rom

ine (

Br)

and A

ntim

ony (

Sb)

based f

lam

e r

eta

rdants

(B

r or

Sb d

o n

ot

exceed 0

.1%

by w

eig

ht

in h

om

ogeneous m

ate

rial)

(3) M

SL, P

eak T

em

p. -

The M

ois

ture

Sensitiv

ity L

evel ra

ting a

ccord

ing to the J

ED

EC

industr

y s

tandard

cla

ssific

ations, and p

eak s

old

er

tem

pera

ture

.

(4) T

here

may b

e a

dditio

nal m

ark

ing, w

hic

h r

ela

tes to the logo, th

e lot tr

ace c

ode info

rmation, or

the e

nvironm

enta

l cate

gory

on the d

evic

e.

(5) M

ultip

le D

evic

e M

ark

ings w

ill b

e in

sid

e p

are

nth

eses. O

nly

one D

evic

e M

ark

ing c

onta

ined in

pare

nth

eses a

nd s

epara

ted b

y a

"~

" w

ill a

ppear

on a

devic

e. If a

line is

indente

d then it

is a

continuation

of th

e p

revio

us lin

e a

nd the tw

o c

om

bin

ed r

epre

sent th

e e

ntire

Devic

e M

ark

ing for

that devic

e.

(6) L

ead/B

all

Fin

ish -

Ord

era

ble

Devic

es m

ay h

ave m

ultip

le m

ate

rial finis

h o

ptions.

Fin

ish o

ptions a

re s

epara

ted b

y a

vert

ical ru

led lin

e.

Lead/B

all

Fin

ish v

alu

es m

ay w

rap t

o t

wo lin

es if

the f

inis

h

valu

e e

xceeds the m

axim

um

colu

mn w

idth

.

Imp

ort

an

t In

form

ati

on

an

d D

iscla

imer:

The in

form

ation p

rovid

ed o

n this

page r

epre

sents

TI's

know

ledge a

nd b

elie

f as o

f th

e d

ate

that it is

pro

vid

ed. T

I bases it

s k

now

ledge a

nd b

elie

f on in

form

ation

pro

vid

ed b

y t

hird p

art

ies,

and m

akes n

o r

epre

senta

tion o

r w

arr

anty

as t

o t

he a

ccura

cy o

f such info

rmation.

Effort

s a

re u

nderw

ay t

o b

etter

inte

gra

te info

rmation f

rom

third p

art

ies.

TI

has t

aken a

nd

continues t

o t

ake r

easonable

ste

ps t

o p

rovid

e r

epre

senta

tive a

nd a

ccura

te info

rmation b

ut

may n

ot

have c

onducte

d d

estr

uctive t

esting o

r chem

ical analy

sis

on incom

ing m

ate

rials

and c

hem

icals

.

TI and T

I supplie

rs c

onsid

er

cert

ain

info

rmation to b

e p

roprieta

ry, and thus C

AS

num

bers

and o

ther

limited info

rmation m

ay n

ot be a

vaila

ble

for

rele

ase.

In n

o e

vent shall

TI's

lia

bili

ty a

risin

g o

ut of such info

rmation e

xceed t

he tota

l purc

hase p

rice o

f th

e T

I part

(s)

at is

sue in this

docum

ent sold

by T

I to

Custo

mer

on a

n a

nnual basis

.

OT

HE

R Q

UA

LIF

IED

VE

RS

ION

S O

F C

D4016B

, C

D4016B

-MIL

:

•C

ata

log:

CD

4016B

•M

ilita

ry: C

D4016B

-MIL

NO

TE

: Q

ualif

ied V

ers

ion D

efinitio

ns:

•C

ata

log -

TI's s

tandard

cata

log p

roduct

PA

CK

AG

E O

PT

ION

AD

DE

ND

UM

ww

w.ti.com

10-J

un-2

014

Addendum

-Page 3

•M

ilita

ry -

QM

L c

ert

ifie

d for

Mili

tary

and D

efe

nse A

pplic

ations



Device PackageType

PackageDrawing


(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

CD4016BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD4016BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD4016BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD4016BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1


www.ti.com 22-Jan-2015




CD4016BM96 SOIC D 14 2500 367.0 367.0 38.0

CD4016BMT SOIC D 14 250 367.0 367.0 38.0

CD4016BNSR SO NS 14 2000 367.0 367.0 38.0

CD4016BPWR TSSOP PW 14 2000 367.0 367.0 35.0


www.ti.com 22-Jan-2015


IMPORTANT NOTICE



























TL/F/6533

DM

5490/D

M7490A

,D

M7493A

Decade

and

Bin

ary

Counte

rs

July 1992

DM5490/DM7490A, DM7493ADecade and Binary Counters

General DescriptionEach of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the 90A and divide-

by-eight for the 93A.

All of these counters have a gated zero reset and the 90A

also has gated set-to-nine inputs for use in BCD nine’s com-

plement applications.

To use their maximum count length (decade or four-bit bina-

ry), the B input is connected to the QA output. The input

count pulses are applied to input A and the outputs are as

described in the appropriate truth table. A symmetrical di-

vide-by-ten count can be obtained from the 90A counters by

connecting the QD output to the A input and applying the

input count to the B input which gives a divide-by-ten square

wave at output QA.

FeaturesY Typical power dissipation

Ð 90A 145 mW

Ð 93A 130 mWY Count frequency 42 MHz

Connection Diagrams

Dual-In-Line Package

TL/F/6533–1

Order Number DM5490J, DM5490W or DM7490AN

See NS Package Number J14A, N14A or W14B

Dual-In-Line Package

TL/F/6533–2

Order Number DM7493AN

See NS Package Number N14A

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

DM54 b55§C to a125§CDM74 0§C to a70§C

Storage Temperature Range b65§C to a150§C

Note: The ‘‘Absolute Maximum Ratings’’ are those valuesbeyond which the safety of the device cannot be guaran-teed. The device should not be operated at these limits. Theparametric values defined in the ‘‘Electrical Characteristics’’table are not guaranteed at the absolute maximum ratings.The ‘‘Recommended Operating Conditions’’ table will definethe conditions for actual device operation.

Recommended Operating Conditions

Symbol ParameterDM5490 DM7490A

UnitsMin Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current b0.8 b0.8 mA

IOL Low Level Output Current 16 16 mA

fCLK Clock Frequency A 0 32 0 32MHz

(Note 5)B 0 16 0 16

tW Pulse Width A 15 15(Note 5)

B 30 30 ns

Reset 15 15

tREL Reset Release Time (Note 5) 25 25 ns

TA Free Air Operating Temperature b55 125 0 70 §C

’90A Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions MinTyp

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min, II e b12 mA b1.5 V

VOH High Level Output VCC e Min, IOH e Max2.4 3.4 V

Voltage VIL e Max, VIH e Min

VOL Low Level Output VCC e Min, IOL e Max0.2 0.4 V

Voltage VIH e Min, VIL e Max (Note 4)

II Input Current @ Max VCC e Max, VI e 5.5V1 mA

Input Voltage

IIH High Level Input VCC e Max A 80

Current VI e 2.7VReset 40 mA

B 120

IIL Low Level Input VCC e Max A b3.2

Current VI e 0.4VReset b1.6 mA

B b4.8

IOS Short Circuit VCC e Max DM54 b20 b57mA

Output Current (Note 2)DM74 b18 b57

ICC Supply Current VCC e Max (Note 3) 29 42 mA

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time.

Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.

Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

Note 5: TA e 25§C and VCC e 5V.

2

’90A Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)RL e 400X

Symbol ParameterTo (Output)

CL e 15 pF Units

Min Max

fMAX Maximum Clock A to QA 32MHz

FrequencyB to QB 16

tPLH Propagation Delay TimeA to QA 16 ns

Low to High Level Output

tPHL Propagation Delay TimeA to QA 18 ns

High to Low Level Output

tPLH Propagation Delay TimeA to QD 48 ns


tPHL Propagation Delay TimeA to QD 50 ns


tPLH Propagation Delay TimeB to QB 16 ns


tPHL Propagation Delay TimeB to QB 21 ns


tPLH Propagation Delay TimeB to QC 32 ns


tPHL Propagation Delay TimeB to QC 35 ns


tPLH Propagation Delay TimeB to QD 32 ns


tPHL Propagation Delay TimeB to QD 35 ns


tPLH Propagation Delay Time SET-9 to30 ns

Low to High Level Output QA, QD

tPHL Propagation Delay Time SET-9 to40 ns

High to Low Level Output QB, QC

tPHL Propagation Delay Time SET-040 ns

High to Low Level Output Any Q

3

Recommended Operating Conditions

Symbol ParameterDM7493A

UnitsMin Nom Max

VCC Supply Voltage 4.75 5 5.25 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage 0.8 V

IOH High Level Output Current b0.8 mA

IOL Low Level Output Current 16 mA

fCLK Clock Frequency A 0 32MHz

(Note 5)B 0 16

tW Pulse Width A 15

(Note 5)B 30 ns

Reset 15

tREL Reset Release Time (Note 5) 25 ns

TA Free Air Operating Temperature 0 70 §C

’93A Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions MinTyp

Max Units(Note 1)

VI Input Clamp Voltage VCC e Min, II e b12 mA b1.5 V

VOH High Level Output VCC e Min, IOH e Max2.4 3.4 V

Voltage VIL e Max, VIH e Min

VOL Low Level Output VCC e Min, IOL e Max0.2 0.4 V

Voltage VIH e Min, VIL e Max (Note 4)

II Input Current @ Max VCC e Max, VI e 5.5V1 mA

Input Voltage

IIH High Level Input VCC e Max Reset 40

Current VI e 2.4VA 80 mA

B 80

IIL Low Level Input VCC e Max Reset b1.6

Current VI e 0.4VA b3.2 mA

B b3.2

IOS Short Circuit VCC e Maxb18 b57 mA

Output Current (Note 2)

ICC Supply Current VCC e Max (Note 3) 26 39 mA

Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time.

Note 3: ICC is measured with all outputs open, both R0 inputs grounded following momentary connection to 4.5V and all other inputs grounded.

Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

Note 5: TA e 25§C and VCC e 5V.

4

’93A Switching Characteristicsat VCC e 5V and TA e 25§C (See Section 1 for Test Waveforms and Output Load)

From (Input)RL e 400X

Symbol ParameterTo (Output)

CL e 15 pF Units

Min Max

fMAX Maximum Clock A to QA 32 MHz

FrequencyB to QB 16

tPLH Propagation Delay Time A to16 ns

Low to High Level Output QA

tPHL Propagation Delay Time A to18 ns

High to Low Level Output QA

tPLH Propagation Delay Time A to70 ns

Low to High Level Output QD

tPHL Propagation Delay Time A to70 ns

High to Low Level Output QD

tPLH Propagation Delay Time B to16 ns

Low to High Level Output QB

tPHL Propagation Delay Time B to21 ns

High to Low Level Output QB


Low to High Level Output QC


High to Low Level Output QC


Low to High Level Output QD


High to Low Level Output QD

tPHL Propagation Delay Time SET-0

High to Low Level Output to 40 ns

Any Q

5

Function Tables (Note D)

90A

BCD Count Sequence

(See Note A)

CountOutputs

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

90A

BCD Bi-Quinary (5-2)

(See Note B)

CountOutputs

QA QD QC QB

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 H L L L

6 H L L H

7 H L H L

8 H L H H

9 H H L L

93A

Count Sequence

(See Note C)

CountOutputs

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

90A

Reset/Count Function Table

Reset Inputs Outputs

R0(1) R0(2) R9(1) R9(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L X L COUNT

L X L X COUNT

L X X L COUNT

X L L X COUNT

93A

Reset/Count Function Table

Reset Inputs Outputs

R0(1) R0(2) QD QC QB QA

H H L L L L

L X COUNT

X L COUNT

Note A: Output QA is connected to input B for BCD count.

Note B: Output QD is connected to input A for bi-quinary count.

Note C: Output QA is connected to input B.

Note D: H e High Level, L e Low Level, X e Don’t Care.

6

Logic Diagrams

90A

TL/F/6533–3

93A

TL/F/6533–4

The J and K inputs shown without connection are for reference only and are functionally at a high level.

7

Physical Dimensions inches (millimeters)

14-Lead Ceramic Dual-In-Line Package (J)

Order Number DM5490J

NS Package Number J14A

14-Lead Molded Dual-In-Line Package (N)

Order Number DM7490AN or DM7493AN

NS Package Number N14A

9

DM

5490/D

M7490A

,D

M7493A

Decade

and

Bin

ary

Counte

rsPhysical Dimensions inches (millimeters) (Continued)

14-Lead Ceramic Flat Package (W)

Order Number DM5490W

NS Package Number W14B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.