© 2008 altera corporation—public high-performance embedded computing workshop 23-25 september...
TRANSCRIPT
© 2008 Altera Corporation—Public
High-Performance Embedded Computing Workshop
23-25 September 2008
Impact on High-Performance Applications: FPGA Chip Bandwidth at 40 nmJ. Ryan Kenny Altera Corporation101 Innovation DriveSan Jose, CA 95134
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation2
Best-in-Class Transceiver LineageBest-in-Class Transceiver Lineage
Stratix GX3.125 Gbps*
Stratix II GX6.375 Gbps*
Stratix IV GX8.5 and 10 Gbps*
Building on a solid foundation lowers risk
The same analog design team improving the transceiver block through successive generations
Quad architectureXAUI and GbE state machine
Pre-emphasis and equalization
Adaptive equalizerDynamic reconfiguration
PCI Express Gen1 and Gen2
PMATransmit/CDR
8.5 and 10 GbpsPCI Express hard IP
HyperTransport support
Quad architectureXAUI and GbE state machine
Pre-emphasis and equalization
Adaptive equalizerDynamic reconfiguration
PCI Express Gen1 and Gen2
PMATransmit/CDR
Quad architectureXAUI and GbE state machine
Pre-emphasis and equalization
PMATransmit/CDR
* All transceivers operate down to 640 Mbps
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Item Parameters
Transceiver VOD = 0.6 V
Conditions
Nominal voltages: VCCHX = 3.0 V, VCCHTX = 1.4 V VCCLX = 1.1 VTemperature: 25°C
Data rates/pattern 6.375 Gbps, 8.5 Gbps, and 10 Gbps/on chip PRBS7
Agilent 81134APattern Generator
CLK
3.0V 1.5 1.2V
ATB Data
Rx
Tx
SIITC1
Tx
HP 6642APower Supply
refclk
Agilent 86100C DCA-JEquivalent-time Scope
trigger
40-nm Transceiver Eye and Jitter Test Set Up40-nm Transceiver Eye and Jitter Test Set Up
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
40-nm Transceiver Eye Diagram at 8.5 and 10 Gbps40-nm Transceiver Eye Diagram at 8.5 and 10 Gbps
Extraordinary jitter performance
8.5 Gbps 10 Gbps
Pattern
Pattern
PRBS 7PRBS 7
VOD
VOD
600 mV 600 mV
DJDJ
RJ (RMS)
RJ (RMS)
1.23 ps1.23 ps
RJ (RMS)
RJ (RMS)
1.35 ps1.35 ps10.3 ps10.3 ps
8.5 Gbps8.5 Gbps 10 Gbps10 Gbps
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Jitter Tolerance at 8.5 GbpsJitter Tolerance at 8.5 Gbps
Jitter tolerance, 8.5 Gbps, PRBS31
40-nm PQV CEI 6-Gbps short-reach jitter mask
0.01
0.1
1
10
100
1,000
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Jitter frequency (Hz)
Jitt
er a
mp
litu
de
(UI)
8.5-Gbps jitter tolerance curve
CEI 6G short-reach jitter mask
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
High-Performance ApplicationsHigh-Performance Applications
Chip-to-chipbandwidth
Chip-to-chipbandwidth Chip-to-backplaneChip-to-backplane
Soon: Drive optical
Soon: Drive optical
In excess of 100 Gbps (Mixture of 8.5 Gbps
and 3.125 Gbps)
As many as 48 lanes 24 up to 8.5 Gbps
10G optical (Future)