2000 m. ciesielskiptl synthesis1 synthesis for pass transistor logic maciej ciesielski dept. of...

2000 M. Ciesielski PTL Synthesis 1

Synthesis forPass Transistor Logic

Maciej CiesielskiDept. of Electrical & Computer Engineering

University of Massachusetts, Amherst, [email protected]


Overview• Introduction

– Pass transistor basics– Electrical considerations: margin, delay, power– Pass transistor logic (PTL)

• Pass transistor logic synthesis– Based on conventional (CMOS) synthesis

• Logic gates implemented in PTL

– BDD-based synthesis• BDD mapping onto Y cells [Yano 96]• BDD decomposition + mapping onto CMOS and PTL

(BDS system, [Yang 99]


Pass Transistor - Basics

• Works as a switch: on / off

• Noise margin problem– nMOS: passes clear 0, degrades 1

– pMOS: passes clear 1, degrades 0

Vdd Vdd

0 0 VddVdd-Vth

- Vdd- Vdd

0 Vth VddVdd

• Need restoring logic (buffers), pass transmission gates


Pass Transistor Electrical Characteristics

• Delay through a chain of pass transistors:

Rn Rn RnRn

Cg Cg Cg Cg

del = RnCg + 2 RnCg + … + n RnCg = RnCg(1 + 2 + … n)

= RnCg (n + 1) n / 2

• Remedy: limit number of pass transistors to 3


Pass Transistor - Applications

• Specialty, custom circuits– XOR, etc.

• Arithmetic logic– Custom designed arithmetic circuits– Regularity, low area, low power

• Control logic ?– No working methodology for logic synthesis, yet


Conventional (CMOS) Logic Synthesis- Review -

• Targeting only CMOS logic gates– Static: no dynamic logic, no pass transistors

• Optimization metrics based on literal *count• Minimize the number of literals

• One-to-one correspondence with transistor signals: n literals => 2n CMOS transistors

F = (A B C)’ = A’+B’+C’ F

B

A

C * Literal = variable or its complement


Conventional Logic Synthesis - Review

• Boolean expressions mapped on CMOS standard cells– AND, OR, NAND, NOR, complex gates– Logic functions expressed in terms of those by logic

optimization tools (SIS, Synopsys DC, etc.)– No MUXes, no XORs

• Large standard cell libraries– 200-300+ elements (different # of inputs, power capability)– Difficult to maintain, upgrade with technology change

• Algebraic manipulation of Boolean expressions– Algebraic factorization (simple): ab + ac = a(b + c)– Boolean factorization (better): (a + b)(a + c) = a + bc


PTL-based Logic Synthesis: a Simple-minded Approach

• Based on mapping AND/OR gates onto PTL cells– use conventional multi-level logic optimization– generate Boolean expressions– map onto AND/OR gates implemented as PTL (MUXes)

B = 1: F = A

B = 0: F = Z

A

B F = A B ?

F

B

A

F = A B


Example: Conventional CMOS design

F = A’B’ + BC’ + A’C C

B

A

NAND NAND

F

• Conventional logic synthesis• Results mapped onto CMOS gates

[ ( A’(B’ + C) )’ · (B’ + C) ]’ = A’B’ + BC’ + A’C


Example: Conventional design + PTL

C

B

A

NAND NAND

F

F = A’B’ + BC’ + A’C

• Conventional logic synthesis• Gates mapped onto PTL gates

[ ( A’(B’ + C) )’ · (B’ + C) ]’ = A’B’ + BC’ + A’C


Comparison: CMOS vs. PTL

C

B

A

NAND NAND

F

F = A’B’ + BC’ + A’C

Transistor count:Cell count:

Area:Delay:

Power:

16 (1)4

(1)852 m2 (1)652 ps

(1)1.81 W/MHz (1)

30 (1.88)4

(1)1158 m2 (1.36)877 ps

(1.35)2.17 W/MHz (1.20)

C

B

A

FNAND PTL NAND PTL


Conventional design with PTL- Problems -

• Simple-minded approach– Literal count (good for CMOS), does not work for PTL– Algebraic methods not compatible with MUX-based design

• Inefficient– Large area, delay, power

• Need better approach, compatible with MUX concept


PTL-based Logic Synthesis: a MUX-based Approach

• Approach based on Shannon expansion– Represent Boolean logic as a BDD– Map BDD nodes onto PTL gates

• MUXes: simple and multiple-input (Y cells)

PTL treeBDD

Review Binary Decision Diagrams (BDD)


Binary Decision Diagrams (BDD)• Convenient data structure for Boolean logic

representation and manipulation– Decision graph, derived from Shannon expansion

• each node represents Shannon expansion along a variable: f = x fx + x’ fx’

– Represent sets of objects (states, product terms, etc.) encoded as Boolean functions

– Each path represents an implicant (product term) – Reduced BDD - irredundant– Ordered BDD - canonical

• Application to logic synthesis and verification– Canonicity property (reduced ordered BDDs)


BDD - Construction

• Construction of a Reduced Ordered BDD

a b c f

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Truth table

f = ac + bc 1 edge (fx)0 edge (fx’)

Decision tree

10 0 0 1 0 10

a

b

c

b

c c c

f


BDD Construction – cont’d

f

10

a

b

c

b

c

2. Remove duplicate nodes

10

a

b

c

b

c c c

f

1. Remove duplicate terminals

10

a

b

c

f = (a+b)c

3. Remove redundant nodes


Application to Verification

• Equivalence of combinational circuits• Canonicity property of BDDs:

– if F and G are equivalent, their BDDs are identical (for the same ordering of variables)

10

a

b

c

G = ac +bcF = a’bc + abc +ab’c

10

a

b

c


Application to Verification, cont’d

• Functional test generation– SAT, Boolean satisfiability analysis

– to test for H = 1 (0), find a path in the

BDD to terminal 1 (0)

– the path, expressed in function

variables, gives a satisfying solution

(test vector)

ab

ab’c

H

0 1

a

b

c


Application to Synthesis

• BDD node = simple multiplexer (MUX)

x

Fx’ Fx

F

x

Fx’ Fx

x’

F

F = x Fx + x’ Fx’


Application to Synthesis (simple-minded approach)

• Represent each BDD node as a MUX, implemented in PTL

10

a

b

c

F = ac +bc

c

bc

b

a

0

c

1

F = ac +bc


PTL-based Logic Synthesis- Problems -

• Ineffective for larger circuits– too large, too slow, too many MUXes– pass transistor chains are too long– need separating buffers– need methodology for synthesizing circuits from

their BDDs


Logic Synthesis based on Pass Transistor Logic

• Introduce a few PTL cells– easy to maintain cell library

A B

C C’

Y1 cell

D’

E’

A B

E

D

C

Y2 cell

A B

C C’

Y3 cell

D D’

E F

G G’


Basic CMOS and PTL cells

F = (A B C)’ = A’+B’+C’

F

NAND

B

A

C

CMOS cell PTL cell

B A

E

FY2

D

C

F’ = E(A D + B D’) + E’ C


Characteristics - PTL vs. CMOS cell

F = (A B C)’ = A’+B’+C’


Area:Delay:

Power:

6 (1)1 (1)329 m2 (1)295 ps (1)0.91 W/MHz (1)

13 (2.17)3 (3)579 m2 (1.75)465 ps (1.58)0.96 W/MHz (1.05)

B

A

C

FPTL

F

CMOS

B

A

C


PTL-based Logic Synthesis: a multi-input MUX-based Approach

• Based on multi-input MUXes (Y cells)

C

B

A

Y2 cellY2 cell

F = (ACB + AB’)’ = A’B’ + BC’ + A’C


MUX-based Approach• Compare to conventional approach with PTL gates

(numbers relative to CMOS)

C

B

A

NAND NAND

C

B

A

Y2cell


Area:Delay:

Power:

30 (1.88)4

(1)1158 m2 (1.36)877 ps

(1.35)2.17 W/MHz (1.20)

13 (0.81)3 (0.75)579 m2 (0.68)465 ps (0.71)0.96 W/MHz (0.53)


PTL Synthesis Flow [Yano 96]

• Express Boolean logic as shared, multi-output BDD

• Partition BDD into smaller sub-trees, isomorphic with Y

cells

• Map each sub-tree onto a Y cell

• Insert buffers at the Y-cell boundaries• this keeps pass transistor chains limited to 2 (Y tree height)

• Fix circuit polarity by propagating inverters

• Adjust inverter power (P2,4,etc) according to cell load


Y-cell based PTL Synthesis - Example

• Create shared BDDf = w + x + (y z + y’z’)

0

w

x

y

1

z

f

z

g

w

Y1

Y1

Y2• Partition BDD into sub-trees and

map each sub-trees to a Y cell

• Note: Cell type depends on the logic implemented, not just on the number of variables/inputs

g = w (y z + y’z’)


Example: PTL mapping

f

y

z

w

w

x

g

f = w + x + (y z + y’ z’)g = w (y z + y’ z’)

Y1

Y2

Y1

0

w

x

y

1

z

f

z

g

w

g = [w’ + w (y z + y’ z’)’]’ =w (y z + y’ z’)

f = [w’ x’ (y z + y’ z’)’] ’ =

w + x + (y z + y’ z’)


PTL Synthesis - Results

• Impressive results for control logic and arithmetic circuits – improvement in area, delay and power !– need BDD synthesis & partitioning methodology– use CMOS gates as natural buffers?

• New research (BDS) – mixing CMOS with PTL

2000 m. ciesielskiptl synthesis1 synthesis for pass transistor logic maciej ciesielski dept. of...

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