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Maze Routing

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Improving Lee’s Algorithm• The choice of the starting pin can affect the speed of

the algorithm, – one guideline is to start on the pin farthest from the center

of the chip

• Use double fan out- begin at both pins and continue until a point of contact is

made

• Use framing, – an artificial rectangular boundary 10 to 20% larger than

the boundary formed by the pins

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Schemes to Reduce Run Time

1. Starting Point Selection:

2. Double Fan-Out: 3. Framing:

S

T

T

S

S

T TS

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Multi-Terminal Nets

• For a k-terminal net, connect the k terminals using a rectilinear Steiner tree with the least wire length on the maze.

• This problem is NP-Complete!• So, just want to find some good heuristic.• This problem can be solved by extending the

Lee’s algorithm. Any idea …..

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Connecting Multipoint Nets

• One point is selected as the source and all the other points are the target– propagate from the source until one target is

reached

– find the path from the source to that target

– all the cells on the path are labeled as source cells and the remaining unconnected pins are targets

– repeat the steps

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Example

Start at the source and run the maze router until you hit a targetStart at the source and run the maze router until you hit a target

S

T

T

1

1

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2 2

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44

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4 5

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Every cell on the path is a source – run the maze routerEvery cell on the path is a source – run the maze router

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1 1 1

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Hadlock’s Algorithm to Reduce Run Time

“A Shortest Path Algorithm for Grid Graphs”, F.O. Hadlock, Networks, 7:323-334, 1977.

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Hadlock’s Algorithm Detour Number: For a path P from S to T, d(P) = # of grids directed away from T, then

L(P) = MD(S,T) + 2d(P)

So minimizing L(P) and d(P) are the same.

Length Manhattan Distance

S

T

DDD D: Detour

d(P) = 3MD(S,T) = 6L(P) = 6+2x3 = 12

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Hadlock’s Algorithm

• Label vertices with detour numbers instead of distance.

• Vertices with smaller detour number are expanded first.

• Therefore, favor paths without detour.

S

T0

000011

111

1 1

22 2

22 2

2 2 22 22

3

3

3

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Hadlock’s Algorithm

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Multilayer Routing

• Give a system with multiple wire layers– Parallel grids vertically stacked, one for each layer

– Use vias to access other layers

– Label cells as to whether a via is permitted at its location

• How do we find wire paths in such a structure?

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Multilayer Routing

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Aside: VIAs• Vias:

– “Vertical” electrical connection

• Issue: size– On chips, vias are usually a lot bigger than wire widths so you

have to be careful where you put them

– You can’t put vias as close to each other as you can put wires

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Example

• Given two metal layers with vias allowed in some cells (labeled as ‘v’)

Layer 1 Layer 2

v v

vvS

T

Expansionmay go upand downas well asto adjacentcells

11

112

22

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3 33

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3 3

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44

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44 4 4

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4 44

55

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5 55

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555

555

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v v

References

• David Pan, VLSI Physical Design Automation, Lecture Slides, University of Texas, 2009.

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