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  • 1.Work itemsBy Sean Chen

2. Work items ATPG stil2tstl Slow path path delay CPU test Test flow JTAG Software solution openRISC External work for free publish Reference 3. stil2tstl Whats stil /tstl Test Pattern stil for human view tstl for machine view Why use it? License issue... Debug / Hack / Mask 4. stil2tstlDesign flow*.STIL Translation Parser: Parser Define Key words Assignment: Fit our data structures LibAssignment(class) Analysis: Preamble ShiftAnalysis capture Translation:Translation Cycle based Mapping: TSTL format Mapping 5. stil2tstl Memory usage 6. Traditional path delay flow PATH DELAY 1. Slack based1.Report analysis12. Module based 3. clock based6 *.xml total.rpt STAdebussy2 1.False path analysis2. scan path analysisscan.rpt3 1.critical path analysis2.Latch analysisana.rpt3.Lopp analysis4.Multi drive analysis 4 ATPG5 NC-simPattern1.ATPG report analysis 1.NC-sim report analysis atpg.rpt Nc-sim.rptNo Nc vs atpg analysisYes 7. Enhance Path-Delay FlowGarbage in = out 8. Enhance Path-Delay Flow Whats un-testable path?010 110 9. Enhance Path-Delay Flow Path extraction by STA Report timing slack, multi cycle check... Is that enough ? 10. Enhance Path-Delay Flow Sample timing reportA true Path list {=====================pin typeincr path_delay c=====================A[0](in) 0 0rU10/A NAND20 0rU10/Y NAND21 1fa bU9/ANOT1 0 1fU9/YNOT1 1 2rU4/ANAND21 3rU4/YNAND214 fM[1](out)04 fd====================Data Required time5Data Arrival time 4 Only one to one path test====================notSlack1 whole chip test} coverage lost ...... 11. *.v *.libCheck design constrainDesign constrain STASCAN_CHINSCANSCAN TRS CELLCHIN XML Re_Check PATH VIEWER DELAY SLOW Report_timing Report_timingDebussyPATHSLOWPATHTHROUGH LATCHSLOW PATH PATH DELAY 12. Enhance Path-Delay Flow Simulation results Enhance flow is better 13. Enhance Path-Delay Flow XML path Dumper 14. Flow extent 15. Commands Commands max_paths slack -nworst clockSLACK launch captureSLACK IO SLACK ++ CELL each CELL+CLOCK noZCritical case filter groupExample : commandwrite_delay_paths group -slack -nworst -max_paths 16. CPU test flow HW/SW co Design flow 17. CPU test flowThe key components of the ASCII Interface areASCII Interface configuration fileDVC fileASCII vector fileait tool for running timing translation automaticallyd2w for device cycle to timing setup conversionaiv tool for running pattern translation automaticallyv2b for translating tabular ASCII test patterns to binaryvector setups 18. CPU test flow 19. CPU test flow Test flow 20. CPU test flow Code analysis Test Suites DC test, Cache test Setup Files Pins, Levels, Timing, Vector, attribute 21. CPU test flow Test-suite for Bin Map. Whats Bin? CPU rank definition ex: 2.4G, 2.8G... 22. Hard to read 23. CPU test flow HARD Bin(1) HARD Bin(2)C1 ULV00C1 ULV00C2 ULV01C3 ULV02C3 ULV02C4 ULV03... ... 24. CPU test flow For each bin classify Cut redundant Test suites Merge Test suites Reduce ATE test time Enhance flow density Reduce ATE memory usage 25. CPU test flow 26. JTAG Whats JTAG? Standard Test Access Port and Boundary-ScanArchitecture Why use it? Easy debug GUI viewer Low cost Step by step OpenRISC project 27. JTAG Software solution 28. JTAG 29. JTAG JTAG FSM 30. JTAG Real view for JTAG @ Print port parallel control Wiggler 31. JTAG Wiggler 32. JTAG DLL control 33. How to use. 34. JTAG Test pattern inserted launch/capture 35. JTAG verilog/C/Driver/ 36. JTAG 37. JTAG 38. JTAG / UART HW/SW co simulationAll c model SystemC model c/c++Hardware 39. JTAG / UART 40. JTAG Same language @ platformSimulation timeDebugFast Test suiteC/C++Verilog 2 SystemCHardware DriverLinux system call 41. External work for ARM ARM ARM BUS 3.0 AHB, APB, AHB2APB Bridge. SystemC hardware model Emulator platform ARM BUS 4.0 (AXI) Emulator TLB(translation Lookup table) Emulator Cross compiler (gcc) Bootloader 42. External work High level synthesis LLVM C 2 Verilog assignment For loop 2 Bus interface emulator RISC CPU Emulator 3D IC Power Partition Multi STA 43. Reference My site


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