Work items

By Sean Chen

Work items

● ATPG● stil2tstl● Slow path● path delay

● CPU test● Test flow

● JTAG● Software solution ● openRISC

● External work for free publish

● Reference

stil2tstl

● What's stil /tstl● Test Pattern

– stil for human view– tstl for machine view

● Why use it?● License issue...● Debug / Hack / Mask

stil2tstl

Design flow● Translation● Parser:

● Define Key words● Assignment:

● Fit our data structures ● Analysis:

● Preamble● Shift● capture

● Translation:● Cycle based

● Mapping:● TSTL format

*.STIL

Parser

Lib(class)

Analysis

Assignment

Translation

Mapping

stil2tstl

● Memory usage ●

Traditional path delay flowPATH DELAY

1. Slack based2. Module based3. clock based

1.False path analysis2. scan path analysis

1.critical path analysis2.Latch analysis3.Lopp analysis4.Multi drive analysis

1.ATPG report analysis

STA

ATPG Pattern NC-sim

1.NC-sim report analysis

scan.rpt

ana.rpt

atpg.rpt Nc-sim.rpt

Nc vs atpg analysis No

Yes

1.Report analysis1

2

*.xml total.rpt

debussy

3

45

6

Enhance Path-Delay Flow

Garbage in = out

Enhance Path-Delay Flow

● What's un-testable path?

01

0

11

0

Enhance Path-Delay Flow

● Path extraction by STA● Report timing … slack, multi cycle check...

Is that enough ?

Enhance Path-Delay Flow● Sample timing report

A true Path list {

=====================

pin type incr path_delay

=====================

A[0] (in) 0 0 r

U10/A NAND2 0 0 r

U10/Y NAND2 1 1 f

U9/A NOT1 0 1 f

U9/Y NOT1 1 2 r

U4/A NAND2 1 3 r

U4/Y NAND2 1 4 f

M[1] (out) 0 4 f

====================

Data Required time 5

Data Arrival time 4

====================

Slack 1

}

a b

c

d

Only one to one path testnot

whole chip test

coverage lost ......

*.v*.lib

STADesignconstrain

SCANCHIN

SCAN_CHINTRS

SCANCELL

Report_timing Report_timing

Re_Check

SLOWPATH

SLOWPATH

THROUGHLATCH

PATHDELAY

XMLVIEWER

Debussy

SLOW PATH PATH DELAY

Check design constrain

Enhance Path-Delay Flow

● Simulation resultsEnhance flow is better

Enhance Path-Delay Flow

● XML path Dumper

Flow extent

Commands

● Commands• max_paths• slack • -nworst• clock• launch• capture• IO• each– noZ

• group

SLACK

SLACK + CELL

SLACK + CELL +CLOCK

Critical case filter

Example : commandwrite_delay_paths –group <list> -slack <float> -nworst <int> -max_paths <int>

CPU test flow

● HW/SW co Design flow

CPU test flow

The key components of the ASCII Interface are

ASCII Interface configuration file

DVC file

ASCII vector file

ait tool for running timing translation automatically

d2w for device cycle to timing setup conversion

aiv tool for running pattern translation automatically

v2b for translating tabular ASCII test patterns to binary vector setups

CPU test flow

CPU test flow

● Test flow

CPU test flow ● Code analysis

● Test Suites– DC test, Cache test

● Setup Files– Pins, Levels, Timing, Vector, attribute

CPU test flow

● Test-suite for Bin Map.● What's Bin?

● CPU rank definition ex: 2.4G, 2.8G...

Hard to read

CPU test flow

● HARD Bin(1)

C1 ULV00C2 ULV01C3 ULV02...

● HARD Bin(2)

C1 ULV00C3 ULV02C4 ULV03...

CPU test flow

● For each bin classify● Cut redundant Test suites ● Merge Test suites● Reduce ATE test time● Enhance flow density● Reduce ATE memory usage

CPU test flow

JTAG

● What's JTAG?● Standard Test Access Port and Boundary-Scan

Architecture

● Why use it?● Easy debug ● GUI viewer● Low cost ● Step by step

● OpenRISC project

JTAG

● Software solution

JTAG

JTAG

● JTAG FSM

JTAG

● Real view for JTAG● @ Print port parallel control “Wiggler”

JTAG

● Wiggler

JTAG

● DLL control

● How to use.●

JTAG

● Test pattern inserted launch/capture

JTAG

verilog/ C/

Driver/

JTAG

JTAG

JTAG / UART

● HW/SW co simulation ● SystemC model ●

c/c++

Hardware

All c model

JTAG / UART

JTAG

● Same language @ platform ● Simulation time ● Debug ● Fast

Hardware Driver Linux system call

Verilog 2 SystemC

Test suiteC/C++

External work for ARM

● ARM● ARM BUS 3.0

– AHB, APB, AHB2APB Bridge.– SystemC hardware model– Emulator platform

● ARM BUS 4.0 (AXI)– Emulator

● TLB(translation Lookup table)– Emulator

● Cross compiler (gcc)– Bootloader

External work

● High level synthesis● LLVM

– C 2 Verilog assignment● For loop 2 Bus interface emulator

● RISC CPU– Emulator

● 3D IC Power Partition● Multi STA

Reference

● My site● http://funningboy.blogspot.com/