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1. Verification of logic gates, HA and HS 2. Design and Verification of Multiplexer and De-multiplexer. 3. Design and Verification of Encoder and Decoder. 4. Design of Parity Generator and code converter (Binary to gray, gray to binary)

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1. Verification of logic gates, HA and HS2. Design and Verification of Multiplexer and De-multiplexer.3. Design and Verification of Encoder and Decoder.4. Design of Parity Generator and code converter (Binary to gray, gray to binary)

1. VERIFICATION OF LOGIC GATES

AIM:To study and verify the truth table of logic gates.APPARATUS\ COMPONENTS REQUIRED:

THEORY:The logic gates belonging to the TTL family perform the following functions:

OR GATE The OR gate does the OR logic operation. If A and B are the inputs then the output Y is given by Y=A+B, + denotes OR operation.AND GATE The AND gate does the AND logic operation. If A and B are the inputs then the output Y is given by Y=A.B, . denotes AND operation.NOT GATEThe NOT gate does the NOT logic operation. If A is the input then the output Y is given by Y=A, where denotes NOT operation.The logic gates OR, AND, NOT are called universal gates

NOR GATE The NOR gate does the NOR logic operation. It is NOT operation of the OR logic. If A and B are the inputs then the output Y is given by Y= (A+B), where + denotes OR operation.

NAND GATEThe NAND gate does the NAND logic operation. It is NOT operation of the AND logic. If A and B are the inputs then the output Y is given by Y= (A.B), . denotes AND operation.EXOR GATE The EXOR gate does the EXOR logic operation. If A and B are the inputs then the output Y is given by Y=A.B+A.B

AND gate ABY

OR gate ABY

NOT gate A

Y

NAND gate ABY

NOR gate ABY

EXOR gate ABY

EXNOR gateABY

1a. DESIGN HALF ADDER & HALF SUBTRACTOR USING LOGIC GATES

THEORYHalf AdderThis is a logic circuit, which accepts two binary bits on its input and produces two binary bits at the output called the sum and the carry bits. From the operation of the half adder circuit, the expression for sum and carry outputs are given as a function of the inputs SUM = A B. CARRY = AB.Half SubtractorThis is a logical circuit which subtracts one input from the other and generates the difference bit and the borrow bit. The logical expression for the difference and borrow output is a function of inputs.D =A BB0 = B

Half Adder Circuit Diagram

Truth TableABSumCarry

Half Subtractor Circuit Diagram

Truth Table

ABDB0

Inference and Result:

Facultys Evaluation:

2. DESIGN AND VERIFICATION OF MULTIPLEXER AND DE-MULTIPLEXER.

AIMTo study the 4:1 multiplexer and 1:4 De-multiplexer using gates.

APPARATUS REQUIRED

THEORY Multiplexer is a combinational circuit which can select any one of the input and route it to the out put. A multiplexer has data input lines, data select lines and output. The logical symbol of a 4 line to 1 line multiplexer is shown in figure. According to the two bit binary code on the data select input, corresponding data input line will be selected and routed to the output. For example if S1S0 is 00 , D0 will be selected, if S1S0 01, D1 will be selected and so on. from the truth table it can be seen that output Y=D0S1S0+D1S1S0+D2S1S0+D3S1S0

Logic Symbol /Truth TableD0D1D2MUXYS0S1D3

S0S1Y

Circuit Diagram

THEORY Demultiplexer does the reverse operation of multiplexer. The data on a line is distributed any one of the output line according to the binary code on data select lines. The logic symbol of a 1 line to 4 line demultiplixer is shown in figure. When the input on data select inputs S1 S0 is 00 , data on the data line will be available on D0 output, if the input on data select inputs S0 S1 is 01 , data on the data line will be available on D1 output and so on

Logic Symbol/ Truth TableD0D11D21D31DEMUXS0S1Data inputData select

S0S1D0D1D2D3

Circuit Diagram

Inference and Result

Facultys Evaluation

3. DESIGN AND VERIFICATION OF ENCODER AND DECODER.

AIM:To design and investigate the decoder and encoder.APPARATUS REQUIRED:

THEORY:DECODER: A decoder is a combinational circuit that converts binary information from n input lines to a maximum 2n unique output (n) lines.If the n-bit decoded information has an unused dont care combinations. The decoder output will be fewer than 2n outputs.2 to 4 DECODER:Since it has two input lines and four output lines, it is called 2 to 4 line decoder. Only one output will be activated for the given input.CIRCUIT OPERATIONS:i) If both the inputs are zero i.e., A=0 and B=0.The first AND gate D0 =A1 B1 is selected and the remaining AND gates are active low.ii) If the inputs A=0 and B=1, then the first, third and fourth AND gates outputs are active low. The output of second AND gate is active high.iii) If both the inputs A=1 and B=1, then the first, second and third AND gates outputs are active low and the fourth one is active high.

DECODER:BLOCK DIAGRAM:

TRUTH TABLE:

INPUTOUTPUT

ABD0D1D2D3

Circuit Diagram

THEORY:ENCODER: An encoder is a digital circuit that performs the reverse operation of the decoder. The encoder has 2n input lines and n output lines. The output lines generate the binary code corresponding to the input values. The process of translating decimal number to binary is encoding.4 to 2 ENCODER:It accepts four inputs and produces two bit output code corresponding to that input. It is assumed that only one input has a value 1 at any given time. CIRCUIT OPERATIONS:i) When D2 = 1 and D3 = 1 (active high) the output A is active high. So A=D2+D3.ii) When D1= 1 and D3 = 1 (active high) the output B is active high. So B=D1+D3.ENCODER:BLOCK DIAGRAM:

TRUTH TABLE:INPUTOUTPUT

D0D1D2D3XY

Circuit Diagram

Inference and Result

Facultys Evaluation

4. DESIGN OF PARITY GENERATOR AND CODE CONVERTER (BINARY TO GRAY, GRAY TO BINARY)AIMTo design the parity generator and code converter to convert binary to gray and vice versa.APPARATUS REQUIRED:

THEORYTo indicate any occurrence of error, an extra bit is included with the message according to the total number of 1s in a set of data, which is called parity.If the extra bit is considered 0 if the total number of 1s is even and 1 for odd quantities of 1s in a set of data, then it is called even parity.

On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for an odd number of 1s, then it is called odd parity.

Circuit Diagram

Truth TableD0D1D2D3PePO

BINARY TO GRAY CODEAn interesting application for the exclusive-OR gate is a logic gate to change a binary number to its equivalent in Gray Code. The logic circuit can be used to convert a 4-bit binary number ABCD into its Gray- code equivalent, G1, G2, G3 and G4. As an example, the binary number 0011 will be converted into its Gray-Code equivalent of 0010 by the circuit.Circuit Diagram

Truth Table

GRAY TO BINARY CONVERTERA Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. The term Gray code is often used to refer to a "reflected" code, or more specifically still, the binary reflected Gray code.To convert a binary reflected Gray codeto a binarynumber, start again with theth digit, and compute

Ifis 1, replaceby; otherwise, leave it the unchanged. Next compute

and so on. The resulting numberis thebinarynumber corresponding to the initial binary reflected Gray code.Circuit Diagram

Truth Table

Inference and Result

Facultys Evaluation