wince realtime
DESCRIPTION
WINCE CAPABILITIES PRESENTATIONTRANSCRIPT
KURT KENNETT
MICROSOFT CORPORATION
Real-Time OverviewBasic TerminologyPractical Usage ExampleWindows CE Interrupt ModelThreads, Processes, IST, ISR, Priorities
Real-Time OverviewBasic TerminologyPractical Usage ExampleWindows CE Interrupt ModelThreads, Processes, IST, ISR, Priorities
Real-Time specific featuresFlexible Thread QuantumPriority InversionVariable System Tick
Real-Time OverviewBasic TerminologyPractical Usage ExampleWindows CE Interrupt ModelThreads, Processes, IST, ISR, Priorities
Real-Time specific featuresFlexible Thread QuantumPriority InversionVariable System Tick
Measurement Tools
Real-Time OverviewBasic TerminologyPractical Usage ExampleWindows CE Interrupt ModelThreads, Processes, IST, ISR, Priorities
Real-Time specific featuresFlexible Thread QuantumPriority InversionVariable System Tick
Measurement ToolsCanned Demo
InterruptHardware signal indicating a real-world event has happened The corresponding hardware device needs to be serviced in some way by the computer system
InterruptHardware signal indicating a real-world event has happened The corresponding hardware device needs to be serviced in some way by the computer system
LatencyThe time from when the interrupt occurred to when the hardware begins to be serviced
InterruptHardware signal indicating a real-world event has happened The corresponding hardware device needs to be serviced in some way by the computer system
LatencyThe time from when the interrupt occurred to when the hardware begins to be serviced
JitterRange of allowable variation in service timeUsually defined by the “tolerance” of a mechanical system for the variability in response
InterruptHardware signal indicating a real-world event has happened The corresponding hardware device needs to be serviced in some way by the computer system
LatencyThe time from when the interrupt occurred to when the hardware begins to be serviced
JitterRange of allowable variation in service timeUsually defined by the “tolerance” of a mechanical system for the variability in response
BoundedExtreme limits are known precisely
InterruptHardware signal indicating a real-world event has happened The corresponding hardware device needs to be serviced in some way by the computer system
LatencyThe time from when the interrupt occurred to when the hardware begins to be serviced
JitterRange of allowable variation in service timeUsually defined by the “tolerance” of a mechanical system for the variability in response
BoundedExtreme limits are known precisely
Bounded low latency and jitter = “hard” real time
Consumers want to know if CE is hard real-timeWant to know if CE is capable of simultaneously running radio and UISome system developers were concerned that CE was not hard real-time enough to meet the requirements
Consumers want to know if CE is hard real-timeWant to know if CE is capable of simultaneously running radio and UISome system developers were concerned that CE was not hard real-time enough to meet the requirements
RequirementsRun cellular radio DSP Meet “tight” timing requirementsARM <= 250Mhz CPUFull performance Windows CE UIAnd play simultaneous video and audio
Soft Real-Time
Cycle Variation or Jitter (µs)
500 us
1 ms
5 ms
10 ms
20 ms
100 ms
Cyc
le T
ime
HardRealTime
0 1,000 µs 5,000 µs 10,000 µs100 µs
OMAC represents Industrial Automation Community
Soft Real-Time
Cycle Variation or Jitter (µs)
500 us
1 ms
5 ms
10 ms
20 ms
100 ms
Cyc
le T
ime
HardRealTime
0 1,000 µs 5,000 µs 10,000 µs100 µs
WindowsNT
OMAC represents Industrial Automation Community
Soft Real-Time
Cycle Variation or Jitter (µs)
500 us
1 ms
5 ms
10 ms
20 ms
100 ms
Cyc
le T
ime
HardRealTime
0 1,000 µs 5,000 µs 10,000 µs100 µs
WindowsCE 2.X
WindowsNT
OMAC represents Industrial Automation Community
Soft Real-Time
Cycle Variation or Jitter (µs)
500 us
1 ms
5 ms
10 ms
20 ms
100 ms
Cyc
le T
ime
HardRealTime
0 1,000 µs 5,000 µs 10,000 µs100 µs
WindowsCE 2.X
WindowsNT
Windows CE .NET
OMAC represents Industrial Automation Community
Soft Real-Time
Cycle Variation or Jitter (µs)
500 us
1 ms
5 ms
10 ms
20 ms
100 ms
Cyc
le T
ime
HardRealTime
0 1,000 µs 5,000 µs 10,000 µs100 µs
WindowsCE 2.X
WindowsNT
Windows CE .NET
90%of
Apps
OMAC represents Industrial Automation Community
So what were some actual requirements for a real project?200Mhz ARMWindows CE with Full UIRunning WMV Video playbackInterrupt as frequent as every 4.6 msAllowable jitter < 0.5ms
Interrupt every 4.6 ms
0.5 ms JitterActual Application Requirements
Windows CE Real-Time Test Results
In terms of the 0.5 ms jitter aloneCE’s longest ISR response time was 13.3 µs (2.6% of max allowed)CE’s longest IST response time was 103 µs (20.6% of max allowed)
ISR starts IST startsMinimum 1.2 µs 31.7 µsAverage 3.3 µs 67.2 µsMaximum 13.3 µs 103.0 µs
Time in microseconds (µs)
Windows CE Real-Time Test Results
In terms of the 0.5 ms jitter aloneCE’s longest ISR response time was 13.3 µs (2.6% of max allowed)CE’s longest IST response time was 103 µs (20.6% of max allowed)
ConclusionCE’s response time was well within the requirementsProject in case study went ahead and did well
ISR starts IST startsMinimum 1.2 µs 31.7 µsAverage 3.3 µs 67.2 µsMaximum 13.3 µs 103.0 µs
Time in microseconds (µs)
ThreadA piece of code that can be scheduled to run by the kernelA “unit” of execution May be launched by a process or a driver
ThreadA piece of code that can be scheduled to run by the kernelA “unit” of execution May be launched by a process or a driver
ProcessLaunched from an executable fileA collection of threads (at least one) with a common execution environmentCan create threads to handle interrupts
ThreadA piece of code that can be scheduled to run by the kernelA “unit” of execution May be launched by a process or a driver
ProcessLaunched from an executable fileA collection of threads (at least one) with a common execution environmentCan create threads to handle interrupts
DriverA DLL, (dynamically loaded library) loaded into the kernel or into a user-mode driver host processCan create threads to handle interrupts
Interrupt Service Routine (ISR)A piece of code built into or loaded into the kernel Logically assigned to a particular hardware interrupt Called within O(10) CPU instructions to service an interruptShould be written to run quickly with few or no outside dependencies and no synchronization with or unbounded calls to other codeCan be chained together if multiple devices might use the same hardware interrupt line (IRQ)Logically notifies the kernel which IST should run
Interrupt Service Routine (ISR)A piece of code built into or loaded into the kernel Logically assigned to a particular hardware interrupt Called within O(10) CPU instructions to service an interruptShould be written to run quickly with few or no outside dependencies and no synchronization with or unbounded calls to other codeCan be chained together if multiple devices might use the same hardware interrupt line (IRQ)Logically notifies the kernel which IST should run
Interrupt Service Thread (IST)A thread registered specifically to handle an interruptCan be created by either a process or a driverScheduled like any other thread on the systemShould be written to do the bulk of the interrupt handling work
ISRs and ISTs usually work as pairsISR handles the critical time-sensitive workIST typically handles the rest
ISRs and ISTs usually work as pairsISR handles the critical time-sensitive workIST typically handles the rest
They synchronize by using an OS EVENT ObjectThe IST creates an EVENT Object The IST associates the EVENT with a logical interruptIt uses the WaitForSingleObject() to wait for the EVENT object to be signaledThe ISR tells the kernel which EVENT object to signalWhen the EVENT is signaled, it unblocks the IST and makes it able to be scheduled by the kernel to run
ISRs and ISTs usually work as pairsISR handles the critical time-sensitive workIST typically handles the rest
They synchronize by using an OS EVENT ObjectThe IST creates an EVENT Object The IST associates the EVENT with a logical interruptIt uses the WaitForSingleObject() to wait for the EVENT object to be signaledThe ISR tells the kernel which EVENT object to signalWhen the EVENT is signaled, it unblocks the IST and makes it able to be scheduled by the kernel to run
If the IST is the highest priority run-able thread, it will get scheduled to run immediately
Windows CE 6.0 has 256 levels of priority
Levels Description0 through 96 Real-time above drivers
97 through 152 Default used by CE device drivers
153 through 247 Real-time below drivers
248 through 255 Non-real-time priorities
Windows CE 6.0 has 256 levels of priorityLevel 0 is the highest and 255 is the lowest
Levels Description0 through 96 Real-time above drivers
97 through 152 Default used by CE device drivers
153 through 247 Real-time below drivers
248 through 255 Non-real-time priorities
Windows CE 6.0 has 256 levels of priorityLevel 0 is the highest and 255 is the lowestThe default level for a thread is 252
Levels Description0 through 96 Real-time above drivers
97 through 152 Default used by CE device drivers
153 through 247 Real-time below drivers
248 through 255 Non-real-time priorities
Windows CE 6.0 has 256 levels of priorityLevel 0 is the highest and 255 is the lowestThe default level for a thread is 252Levels 0 through 248 can be reserved by OEM
Levels Description0 through 96 Real-time above drivers
97 through 152 Default used by CE device drivers
153 through 247 Real-time below drivers
248 through 255 Non-real-time priorities
Is responsible for determining which thread will runHas a queue for threads for each priority levelAlways schedules first thread at the highest priority level
Is responsible for determining which thread will runHas a queue for threads for each priority levelAlways schedules first thread at the highest priority level
A thread gets to run for set length of time, called a “quantum”
Typically 100 millisecondsA quantum of 0 means the quantum never runs out
The thread can run until blocked or interrupted
Is responsible for determining which thread will runHas a queue for threads for each priority levelAlways schedules first thread at the highest priority level
A thread gets to run for set length of time, called a “quantum”
Typically 100 millisecondsA quantum of 0 means the quantum never runs out
The thread can run until blocked or interrupted
A thread runs until—Its quantum runs outIt is interrupted by a higher priority threadIt is blocked by a resource contention such as access to a critical section or a mutex
Interrupt Handler calls registered ISR
Interrupt Occurs ISR runs, tells kernel which event to signal
Kernel signals event, IST becomes runable
Scheduler sets up the IST to run
IST runs and resets the interrupt
The maximum amount of time between a hardware interrupt being signaled and when the code in an IST begins to run is:
The maximum amount of time between a hardware interrupt being signaled and when the code in an IST begins to run is:
Maximum time before ISR can run
The maximum amount of time between a hardware interrupt being signaled and when the code in an IST begins to run is:
Maximum time before ISR can run+
Maximum time taken by ISR
The maximum amount of time between a hardware interrupt being signaled and when the code in an IST begins to run is:
Maximum time before ISR can run+
Maximum time taken by ISR+
Maximum time taken by kernel to be able to get to a state where it can schedule another thread
The maximum amount of time between a hardware interrupt being signaled and when the code in an IST begins to run is:
Maximum time before ISR can run+
Maximum time taken by ISR+
Maximum time taken by kernel to be able to get to a state where it can schedule another thread
+Maximum time taken by kernel to switch from whatever thread was running to the IST thread
MAXIMUM ISR LATENCY
KERNEL
OAL
Normal Thread
Interrupts Disabled
Preemption Disabled
ISH
ISR
ISH
IST
Scheduler Scheduler
IST LatencyISR Latency
INTERRUPT!
NormalThread Int Off
MAXIMUM ISR LATENCY
KERNEL
OAL
Normal Thread
Interrupts Disabled
Preemption Disabled
ISH
ISR
ISH
IST
Scheduler Scheduler
IST LatencyISR Latency
INTERRUPT!
NormalThread Int Off
MAXIMUM IST LATENCY
KERNEL
OAL
Normal Thread
Interrupts Disabled
Preemption Disabled
ISH
ISR
ISH
IST
KCall Scheduler
IST LatencyISR Latency
INTERRUPT!
NormalThread
SchedulerKCall
MAXIMUM IST LATENCY
KERNEL
OAL
Normal Thread
Interrupts Disabled
Preemption Disabled
ISH
ISR
ISH
IST
KCall Scheduler
IST LatencyISR Latency
INTERRUPT!
NormalThread
SchedulerKCall
Higher priority ISRs can preempt lower ISRs
Higher priority ISRs can preempt lower ISRsBased on support by the CPU, additional hardware, and/or OEM code
Higher priority ISRs can preempt lower ISRsBased on support by the CPU, additional hardware, and/or OEM codeARM
Uses a vectored interrupt tableOnly two CPU interrupt levels, each with its own hardware pin
IRQ – Normally only one used.FIQ – Supports ISR-only scenarios for critical time-sensitive tasks
Interrupts are not turned on before entering an ISROEM can re-enable CPU interrupt within ISR when/if they want
OEMs can prioritize the interrupts with an external Interrupt Controller and bit masks to turn on and off the different interrupts
Hardware designers often attach several devices to the same interrupt line (IRQ)
Hardware designers often attach several devices to the same interrupt line (IRQ)Multiple ISRs can be chained together to handle shared interrupts
Hardware designers often attach several devices to the same interrupt line (IRQ)Multiple ISRs can be chained together to handle shared interruptsEach ISR in turn determines if it can handle the interrupt
If it can, it does its work and either completes the interrupt or returns the logical SYSINTR value representing which IST is to runIf not, it returns SYSINTR_CHAIN indicating the kernel should try the next ISR in the chain.The default OEMInterruptHandler on a system typically will disable an interrupt that occurs that does not have a relative IST assigned to it (it is not claimed by an ISR)
A high priority thread can get stuck waiting for a lower priority thread to release a resource
Such as a critical section, semaphore, or mutexThis causes priority inversion
A high priority thread can get stuck waiting for a lower priority thread to release a resource
Such as a critical section, semaphore, or mutexThis causes priority inversion
The Kernel detects priority inversion and handles it with priority inheritance, or “boosting”
The lower priority thread temporarily inherits the higher priority thread’s priorityThe lower priority thread’s quantum is set to 0, which lets it run until it releases the resource
A high priority thread can get stuck waiting for a lower priority thread to release a resource
Such as a critical section, semaphore, or mutexThis causes priority inversion
The Kernel detects priority inversion and handles it with priority inheritance, or “boosting”
The lower priority thread temporarily inherits the higher priority thread’s priorityThe lower priority thread’s quantum is set to 0, which lets it run until it releases the resource
Supports only one level of inheritanceKernel will only boost one threadIf the boosted thread is also in turn blocked by a third thread, the third thread is not boostedCare must be taken when acquiring locks on shared resources
There is a per-thread quantum
There is a per-thread quantumThe default is set by the OEM in the OAL
dwDefaultThreadQuantum
There is a per-thread quantumThe default is set by the OEM in the OAL
dwDefaultThreadQuantum
APIs to set QuantumCe(Set/Get)ThreadQuantum
There is a per-thread quantumThe default is set by the OEM in the OAL
dwDefaultThreadQuantum
APIs to set QuantumCe(Set/Get)ThreadQuantum
Quantum of 0 sets a thread to “run-to-completion”This can occur at any priorityPreempted only by higher priority threads
Normally there is a 1 ms timer tick
Normally there is a 1 ms timer tickA tick interrupt can cause a reschedule
When a system tick occurs the kernel checks for a reschedule or No-OpThe kernel will make sure one of the highest priority run-able threads is executingIf there is no higher priority thread and the current thread has not exhausted its quantum, the current thread is allowed to continue to run
Normally there is a 1 ms timer tickA tick interrupt can cause a reschedule
When a system tick occurs the kernel checks for a reschedule or No-OpThe kernel will make sure one of the highest priority run-able threads is executingIf there is no higher priority thread and the current thread has not exhausted its quantum, the current thread is allowed to continue to run
Sleep(N) will generally wake up in N to N + 1 ms
Normally there is a 1 ms timer tickA tick interrupt can cause a reschedule
When a system tick occurs the kernel checks for a reschedule or No-OpThe kernel will make sure one of the highest priority run-able threads is executingIf there is no higher priority thread and the current thread has not exhausted its quantum, the current thread is allowed to continue to run
Sleep(N) will generally wake up in N to N + 1 msWhen the CPU has nothing to do (no threads can run) the system tick is reset to when the next scheduled event is to occur
An interrupt can re-set the system tick back to 1 ms
Windows CE 6.0 memory model was re-architectedGWES, Networking, File System, and Driver Manager were all moved into the kernel’s address spaceAll threads from a kernel mode driver run in the kernel process contextThey have full access to the kernel spaceSecurity checks are not required to run or call APIs
Windows CE 6.0 memory model was re-architectedGWES, Networking, File System, and Driver Manager were all moved into the kernel’s address spaceAll threads from a kernel mode driver run in the kernel process contextThey have full access to the kernel spaceSecurity checks are not required to run or call APIs
Kernel mode APIsThe exact same API interface is used, but without the overhead of a system privilege level change or argument marshallingThese resolve to quick calls through a vector table
Windows CE 6.0 memory model was re-architectedGWES, Networking, File System, and Driver Manager were all moved into the kernel’s address spaceAll threads from a kernel mode driver run in the kernel process contextThey have full access to the kernel spaceSecurity checks are not required to run or call APIs
Kernel mode APIsThe exact same API interface is used, but without the overhead of a system privilege level change or argument marshallingThese resolve to quick calls through a vector table
Kernel mode drivers are ideal for real-time work
Software-based real-time measurement toolCode in kernel is minimally instrumented to provide the data
Software-based real-time measurement toolCode in kernel is minimally instrumented to provide the data
Measures both ISR and IST latenciesISR latency
From IRQ to ISR
IST latencyFrom the end of the ISR to the start of the IST
Software-based real-time measurement toolCode in kernel is minimally instrumented to provide the data
Measures both ISR and IST latenciesISR latency
From IRQ to ISR
IST latencyFrom the end of the ISR to the start of the IST
Enabled for all sample platforms
Software-based real-time measurement toolCode in kernel is minimally instrumented to provide the data
Measures both ISR and IST latenciesISR latency
From IRQ to ISR
IST latencyFrom the end of the ISR to the start of the IST
Enabled for all sample platformsCan be used to test response under varying system load
This does scheduler performance timing tests
This does scheduler performance timing testsTool enables you to determine how long it takes to perform basic kernel tasks such as—
Acquire or release a critical section Wait or signal an event Create a semaphore or mutexYield a thread Call system APIs
This does scheduler performance timing testsTool enables you to determine how long it takes to perform basic kernel tasks such as—
Acquire or release a critical section Wait or signal an event Create a semaphore or mutexYield a thread Call system APIs
These things can be good to know in scenarios when more than one time-critical situation can be occurring
Shows interaction between processes, threads, and interrupts
Shows interaction between processes, threads, and interruptsShows events that affect scheduling and system performance
Shows interaction between processes, threads, and interruptsShows events that affect scheduling and system performanceShows thread state and migration
We want to:Take an existing BSPTrack the occurrence of an external event via a hardware interrupt.Show when CE initially responds to the external event through an ISRShow when CE responds to that even in an IST.
We want to:Take an existing BSPTrack the occurrence of an external event via a hardware interrupt.Show when CE initially responds to the external event through an ISRShow when CE responds to that even in an IST.
To do this, we will:Watch the MMC card-detect signal.Have an interrupt triggered on card insertion.Turn on an LED when the ISR startsTurn off the same LED when the IST starts.Watch the LED signal relative to the MMC card-detect signal to see how long it takes for CE to respond.
We want to:Take an existing BSPTrack the occurrence of an external event via a hardware interrupt.Show when CE initially responds to the external event through an ISRShow when CE responds to that even in an IST.
To do this, we will:Watch the MMC card-detect signal.Have an interrupt triggered on card insertion.Turn on an LED when the ISR startsTurn off the same LED when the IST starts.Watch the LED signal relative to the MMC card-detect signal to see how long it takes for CE to respond.
To watch the signals we’ll use an oscilliscope.
SOFTWARE
IRQ
CPU
SOFTWARE
IRQ
CPU
IST
SOFTWARE
IRQ
CPU
IST
SOFTWARE
IRQ
CPU
IST
SOFTWARE
CPU
IST
IRQ
SOFTWARE
CPU
IST
IRQ
ISR
SOFTWARE
IRQ
CPU
IST
IRQ
ISR
SOFTWARE
CPU
IST
IRQ
ISR
SOFTWARE
CPU
IST
IRQ
ISR
SOFTWARE
CPU
IST
SOFTWARE
CPU
IST
Scheduler
SOFTWARE
CPU
IST
Scheduler
SOFTWARE
CPU
IST
SOFTWARE
CPU
IST
SOFTWARE
CPU
IST
Events we will see on the scope:Card InsertionISR Response (turn on LED)IST Response (turn off LED)
Events we will see on the scope:Card InsertionISR Response (turn on LED)IST Response (turn off LED)
By using a timing scale we can see how responsive our system is.
Events we will see on the scope:Card InsertionISR Response (turn on LED)IST Response (turn off LED)
By using a timing scale we can see how responsive our system is.System used for test:
PXA27X (Marvell/Intel) on PhyCore270 Board100MhzMMC CD and LED via GPIO
Start with the desired deadline and acceptable jitter
Start with the desired deadline and acceptable jitterUnderstand the hardware
What is slow?What can be blocked by external events?
Start with the desired deadline and acceptable jitterUnderstand the hardware
What is slow?What can be blocked by external events?
Understand the OSKnow how critical sections and other synchronization methods workKnow what system calls can be blocked on shared resources
Start with the desired deadline and acceptable jitterUnderstand the hardware
What is slow?What can be blocked by external events?
Understand the OSKnow how critical sections and other synchronization methods workKnow what system calls can be blocked on shared resources
Separate Real-Time threads from UI threads
Start with the desired deadline and acceptable jitterUnderstand the hardware
What is slow?What can be blocked by external events?
Understand the OSKnow how critical sections and other synchronization methods workKnow what system calls can be blocked on shared resources
Separate Real-Time threads from UI threadsPre-allocate critical resources
Start with the desired deadline and acceptable jitterUnderstand the hardware
What is slow?What can be blocked by external events?
Understand the OSKnow how critical sections and other synchronization methods workKnow what system calls can be blocked on shared resources
Separate Real-Time threads from UI threadsPre-allocate critical resourcesUse buffers to communicate between time-critical system components and applications/UI
© 2009 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries.The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market
conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.