Von Neumann Machine

Objectives:Explain Von Neumann architecture: Memory

– Organization– Decoding memory addresses, MAR & MDR

ALU and Control Unit – Executing arithmetic & logic operations, ALU

register, CCR, multiplexor circuit– Decoding machine instructions, PC & IR

Decode and trace machine language programs

Von Neumann Architecture

A model for designing and building computers: Has following three characteristics

1. Has four major subsystems

1. memory

2. input-output (I/O)

3. arithmetic-logic unit (ALU)

4. control unit

2. Program is stored in memory

3. Each processor executes one instruction at a time (fetched, decoded and executed)

The Four Subsystems

Memory

Processor

Control Unit

ALUInput-Output

RAM

ROM . . .Register

Register

Disks

ScreenKeyboard

Bus

Control circuits (Chap 4) Decoders and Multiplexors

Decoder circuit (Figure 4.25, p. 164) : takes n inputs and helps choose one of the 2n outputs, numbered 0,1,…, 2n-1.

(determines which binary number the inputs represent and activates the output with that binary as its ID.)

Multiplexor circuit (Figure 4.26, p. 165): based on value of n selector lines (a binary number) selects one of the 2n (0, 1,…, 2n –1) inputs as the output. So, it has just one output.

Decoder CircuitSelects one output line, e.g. if inputs are 1, 0: output line 2 is chosen

(set to 1).01

2

3

Decoder

1

0

0

0

1

0

Used to decode memory addresses and operation codes.

TwoINPUTS

Multiplexor Circuitselects one input line, based on

value of selector lines.Used to select result from correct circuit.

Multiplexor

Inpu

t lin

es

Selector lines (11 selects input line 3)

0

1

2

3

1 1

1

1

1

0

0

Output line

Value in line 3 is passed to output

Internal Memory Random Access Memory (RAM) Stores in and retrieves from current programs and data from

different parts of memory -Can retrieve without destroying the current content -Replaces the old with new when storing. -Takes the same time to access any part of the memory. Read Only Memory (ROM)

-Stores permanent programs, e.g. start-up (Cannot overwrite).

Sizes of memory (internal and/or external)

-N Kilobytes (N * 210 -- thousands) N Megabytes (N * 220 -- millions) N Gigabytes (N * 230 -- billions)

RAMMemory Addresses

Each memory cell has an address.Simple example:

32-bit address space.

RAM

00

01

10

11

00101100

01010000

11001111

01110001

There are 4 memory cells,each containing 8 bits.The addresses are 0, 1, 2, 3in binary.Each address is 2 bits long.

Memory Address Register (MAR)

Memory Data Register (MDR)

Memory unit contains two of the special registers.

MAR holds the current memory address.

MDR hold the data which has been read from that memory address or about to be written to it.

How the MAR & MDR Work

For simple 4-cell example, showing one bit

being read.MAR

Decoder

RAM

00 01 10 11

0001

1011

Bit goes to MDR because line 00 carries a 1.

0 0

AND

0 0 0 1

Fetch

Fetch (address)

1. Decode the address in the MAR

2. Load the address into MAR

3. Copy contents of that memory location into MDR

(The fetch / store controller is set to fetch.)

Store

Store (address, value)1. Load the address into MAR2. Load the value into MDR3. Decode the address in the MAR4. Store the contents of the MDR

into that memory location.(The fetch / store controller is set to

store.)

Arithmetic-Logic Unit (ALU)

Registers Circuits to do math

operations Circuits to do logic (e.g.

compare)

(We have seen circuits for add and compare as examples)

See Fig 5.13 on page 194

Circuits Inside the ALUSee Figure 5.12, p. 193

In example, all circuits produce results: 1001 + 0011 ----> 1100 on line 00 1001 - 0011 ----> 0110 on line 01 1001 = 0011 ----> 0000 on line 10 1001 . 0011 ----> 0001 on line 11

Selector lines are 00 for add operation, so Multiplexor selects output on line 00: 1100

Multiplexor

a + b

a - b

a = b

a

a b

. b

Line 0 (00)

Line 1 (01)

Line 2 (10)

Line 3 (11)

out

Overall ALU Organization

R0

R1

R2

R3

Multiplexor

+ - / =

…Selector lines

BUS0BUS1

BUS2

ALU

…

More about the Von Neumann Machine

Stored Program—the most fundamental characteristics of Von Neumann machine.

A sequence of machine language instructions stored as binary values in memory.

Fetch----Decode----Execute----Store Op code and Operand

Op code & Operand Op code---A code for representing the

operation parts of the machine instructions of a computer.

Operand (Address in our book)---An entity on which an operation is performed or that which is operated upon. An operand is usually identified by an address part of an instruction.

CISC Machine & RISC Machine

CISC--Complex Instruction Set Computers

As few as 30-50 instructions

RISC--Reduced Instruction Set Computers

As many as 200-400 instructions

0 1 2 3 4 5 6 789

Simulator

5.2.4 Control Unit

Machine instructions are stored in RAM.

The job of the Control Unit is to repeatedly:

Fetch the next instruction from RAM Decode the instruction Execute the instruction

Flow Chart of an Instruction

In a real computer, there are five(5) steps

involved as follow:Instruction Fetch Unit

Instruction Decode Unit

OperandFetch Unit

InstructionExecution

Unit

Write BackUnit

1 2 3 4

5

3

Control Unit Registers PC : Program Counter

Holds address of next instruction It will automatic incremented to next instruction address.

IR : Instruction Register Holds current instruction

Computer will find the instruction by the address

Pointed by PC

Machine Instructions Each brand of processor has circuitry

for a particular set of instructions. One brand may have 30 instructions,

another 400 instructions. For any brand, a typical machine

instruction will contain:– Operation code: tells which operation to

do (Op Code)– One or more Addresses telling where the

data (operands) are. (see Fig. 5.14 Page 195)

Types of Operations Data transfer

(Copy data from one place to another -- RAM to Register, Register to RAM, one address to another in RAM)

Arithmetic (e.g. add) Compare (e.g. are the operands equal) Branch (tells where the next instruction

to be executed is stored)

5.2.5 The Entire Computer

Look at Figure 5.18, p. 203, and identify:

--the four major subsystems --the registers used by each

subsystem

Trace the execution of a machine instruction through the computer.

Machine Code

Registers Machine Instructions

Various Registers

MAR -Size to match the address space (20

bit for 1MB) MDR -Standard cell size 8-bits in Intel-

based pc’s (in our simulator 12 bits)It can be anything between 8-64 bits in

different Computer systems Fetch / Store control signal

Various Registers General Purpose Register -To work with ALU and MDR or I/O

Buffer Condition Code Register -Execution of Compare instruction

sets these registers (depending on the outcome)– GT, EQ, LE (100, 010, 001)

Various Registers IR

– Op code and Operands– Op code decoded and Control signals sent to

memory, ALU, I/O– Operands used to fetch / store data from / to

memory locations to / from general purpose registers.

PC – holds address for the next instruction;

usually it is incremented by 1, unless a JUMP Op-code is encountered.

Operation Codes – Details0000 LOAD X (Copy contents of memory Location

X to Register and replaces whatever Reg had before; X is in binary, pointing to an address)

0001 STORE X (Copy contents of R to X)1101 IN X (get integer value from standard input

device and store it in location X in binary form)1110 OUT X (Output the decimal equivalent of the

binary contents of X on the standard output device)

Operation Codes – Details0010 CLEAR X (Fill location X with 0’s)0011 ADD X (Add the contents of X to what is

already there in R and leave the result in R)0101 SUBTRACT X (Subtract the contents of

X from R and the result stays in R)0100 INCREMENT X (Add 1 to the contents of

X)0110 DECREMENT (Subtract 1 from the

contents of X)

Operation Codes – Details1000 JUMP X (Get the next instruction

from the next location 1001 JUMPGT X (If the contents of GT

condition code Register is 1, take the control (I.e., the next instruction from X)

1010 JUMPEQ X (If (EQ CCR) = 1,..)1011 JUMPLT X; (If (LT CCR = 1,…)1100 JUMPNEQ X (If (EQ CCR) = 0, …)Note: (L) means contents of L.