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1/77DAVIET Digital circuit logic Design Slide-1
Introduction to VLSI Design
Custom and semi custom design
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2/77DAVIET Digital circuit logic Design Slide-2
IC Evolution (1/3)
SSISmall Scale Integration (early 1970s)
contained 1 10 logic gates
MSIMedium Scale Integration
logic functions, counters
LSILarge Scale Integration first microprocessors on the chip
VLSIVery Large Scale Integration
now offers 64-bit microprocessors,
complete with cache memory (L1 and often L2),floating-point arithmetic unit(s), etc.
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IC Evolution (2/3)
Bipolar technology
TTL (transistor-transistor logic)
ECL (emitter-coupled logic)
MOS (Metal-oxide-silicon)
although invented before bipolar transistor,
was initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s
required fewer masking steps, was denser, andconsumed less power than equivalent bipolar ICs => anMOS IC was cheaper than a bipolar IC and led toinvestment and growth of the MOS IC market.
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4/77DAVIET Digital circuit logic Design Slide-4
IC Evolution (3/3)
aluminum gates are replaced by polysilicon by early 1980
CMOS (Complementary MOS): n-channel and p-channelMOS transistors =>lower power consumption, simplified fabrication process
Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
GaAs - Gallium Arsenide (for high speed)
Si-Ge - Silicon Germanium (for RF)
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5/77DAVIET Digital circuit logic Design Slide-5
VLSI Benefits
Smaller Size
Higher Performance
Higher Functionality
Higher Reliability
Lower Power Consumption
Design Security
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6/77DAVIET Digital circuit logic Design Slide-6
VLSI Design Styles (1/2)
Full-Custom ASICs
Some (possibly all) logic cellsare customized andall mask layers are customized
Semicustom ASICs
All logic cells are predesigned(defined in cell library) andsome (possibly all) of the masklayers are customized
Types:
Standard-cell based and Gate-array-based ASICs
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7/77DAVIET Digital circuit logic Design Slide-7
VLSI Design Styles (2/2)
Programmable ASICs
All logic cells are predesigned andnone of the mask layers are customized
Types: PLD (Programmable Logic Device) likeSPLD, CPLD, and FPGA (Field Programmable Gate
Array)
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Full-custom ASICs (1/3)
Engineers design some or all of the logic cells, circuits, or layout
specifically for one ASIC
Full-custom ICs are the most expensive to manufacture and todesign
Manufacturing lead time (the time it takes just to make an IC notincluding design time) is typically 8 weeks
When does it make sense?
there are no suitable existing cell libraries available
existing logic cells are not fast enough
logic cells are not small enough
logic cells consume too much power
ASIC is so specialized that some circuits must be custom designed Trends: fewer and fewer full-custom ICs are being designed
(excluding mixed analog/digital ASICs)
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Full-custom ASICs (2/3)
Each circuit element carefully handcrafted
Huge design effort High Design & NRE Costs
High Performance
Until Recently, Unthinkable
Expensive DevelopmentRisky
Special Skills
Lack of Manpower
Justified in Only the Most Desperate Cases optimize design, gain maximum speed, area
usually for large volume product, Typically used for
high-volume applications
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12/77DAVIET Digital circuit logic Design Slide-12
Full-custom ASICs (3/3)
All layers are optimized for an embedded systemsparticular digital implementation
Placing transistors
Sizing transistors
Routing wires
Benefits
Excellent performance, small size, low power
Drawbacks High NRE cost (e.g., $300k), long time-to-market
Vahid & Givargis
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Semi-Custom
Design with Pre-Designed Building Blocks(Standard Cell)
- Low Level Design
+Minimized Needed IC Design Skills
Uses Pre-Implemented Layout (Gate Array)
+Pre-Characterized and Tested
+Minimize Tooling
- Density Sacrifice
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14/77DAVIET Digital circuit logic Design Slide-14
Standard-Cell-Based ASICs (1/5)
Cell-Based ASIC (CBIC) uses pre-designed cells
(AND, OR gates, multiplexers, flip-flops, ...) Standard-cell areas are built of rows of standard cells
Standard-cell areas can be used in combination with larger pre-
designed cells (microcontrollers, or even microprocessors), known
as mega-cells
A cell-basedASIC (CBIC) diewith a singlestandard-cellarea combined
with 4 fixedblocks
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A section of two rows in a standard-cell chip
f1
f2
x1
x3
x2
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Standard-Cell-Based ASICs(2/5)
Characteristics
The layout of individual gates (standard cells) is pre-designed and stored in a library.
custom blocks can be embedded;ASIC designer defines only the placement of thestandard cells and the interconnect in a CBIC
standard cells can be placed anywhere on a silicon =>all mask layers of a CBIC are customized
manufacturing lead time is 8 weeks
The chip layout can be created automatically by CAD
tools because of the regular arrangement of logic gates(cells) in rows.
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Standard-Cell-Based ASICs (3/5)
Advantages
designers save time, money, and reduce risks using apredesigned, pretested, and precharacterized standard-celllibrary
standard cells in the library are constructed using full-custom;each standard cell can be optimized individually(for example, to maximize speed, minimize area, etc);
Disadvantages
time or expense of designing or buying the standard-cell library
time needed to fabricate all layers of the ASIC for each newdesign
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Standard-Cell-Based ASICs(4/5)
Standard-cells are designed
to fit horizontally together to form rows Internal construction of a cell
- 25 microns wide (lambda is 0.25)
- AB: abutment box
- BB: bounding box
- Power supplies: VDD, GND
- Each different shaded andlabeled pattern represents adifferent layer
- Connections: A1, B1, Z
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Standard-Cell-Based ASICs (5/5)
Routing the CBIC- Interconnectionsbetween cells use
spaces (calledchannels) betweenrows
- 2 separate layers ofmetal interconnect
(metal1 and metal2)running at right anglesto each other
- Feedthrough: referseither to the piece of
metal that is used topass a signal througha cell or to a space ina cell waiting to beused as a feedthrough
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Gate-Array-Based ASICs
In gate-array-based ASIC
transistors are predefined on the silicon wafer Base cell the smallest element that is replicated
Base array the predefined pattern of transistors
Masked Gate Array (MGA): only layers which define the
interconnect between transistors are defined by the designer
using custom masks
Designer chooses from a gate-array library pre-designed and
pre-characterized logic cells (often called macros)
.
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DAVIET Digital circuit logic Design Slide-23
Gate-Array-Based ASICs (1/4)
Since only metal interconnections are unique for MGA,
we can use prefabricated wafers(with completed transistor layers)
the turnaround time is reduced to a few days or at most acouple of weeks
the costs for all the initial prefabrication steps for MGA
are shared for each consumer => the cost of an MGA isreduced compared to FC and CBIC
Types: Channeled, Channelless, and Structured Gate Array
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DAVIET Digital circuit logic Design Slide-24
Gate-Array-Based ASICs (2/4)
Channeled gate array
we leave space between the rows of transistors for wiring
Characteristics
only interconnect is customized
the interconnect uses predefined spaces between rows
manufacturing lead time is between 2 days and 2 weeks
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DAVIET Digital circuit logic Design Slide-25
Gate-Array-Based ASICs (3/4) Channelless gate array (sea-of-gates
or SOG) there are no predefined areas set aside
for routing between cells we customize the contact layer that
defines the connections between metal1and transistors
when use area of transistor for routing,do not make any contacts to the deviceunderneath
Characteristics only some (the top few) mask layers
are customized the interconnect Transistor layers on the silicon wafer are
first fabricated to produce a gate-arraytemplate.
Connecting wires are then fabricated onthe template to produce a users circuit.
The technology is also known as a sea-of-gates technology
manufacturing lead time isbetween 2 days and 2 weeks
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DAVIET Digital circuit logic Design Slide-26
A sea-of-gates gate array
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DAVIET Digital circuit logic Design Slide-27
An example of a logic function in a gate array
f1
x1
x3
x2
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DAVIET Digital circuit logic Design Slide-28
Gate-Array-Based ASICs (4/4)
Structured gate array or embedded gate array combines features of CBIC and MGA
motivation: MGA has only fixed gate-array base cell;difficult and inefficient implementation of memory
we set aside some IC area and dedicate it to a specific function
(contain different cells, more suitable for building memory cells, forexample, or complete block, such as a microcontroller)
Characteristics
only some (the top few) mask layersare customized the interconnect
custom blocks can be embedded
manufacturing lead time isbetween 2 days and 2 weeks
problem: embedded function is fixed
S
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DAVIET Digital circuit logic Design Slide-29
Semi-custom
Lower layers are fully or partially built
Designers are left with routing of wires and maybeplacing some blocks
Benefits
Good performance, good size, less NRE cost than a
full-custom implementation (perhaps $10k to $100k)
Drawbacks
Still require weeks to months to develop
Vahid & Givargis
P bl L i (PLD FPGA )
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DAVIET Digital circuit logic Design Slide-30
Programmable Logic (PLDs, FPGAs)
Pre-manufactured components with programmable
interconnect CAD tools greatly reduce design effort
Low Design Cost / Low NRE Cost / High Unit Cost
Lower Performance
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DAVIET Digital circuit logic Design Slide-31
P bl L i D i (1/2)
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DAVIET Digital circuit logic Design Slide-32
Programmable Logic Devices(1/2)
PLDs
standard ICs, available in standard configurations sold in high volume to many different customers
PLDs may be configured or programmed to createa part customized to specific application
Characteristics
no customized mask layers or logic cells
fast design turnaround
a single large block of programmable interconnect
a matrix of logic macrocells that usually consists of
programmable array logic followed by a flip-flop or latch
P bl L i D i (2/2)
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DAVIET Digital circuit logic Design Slide-33
Programmable Logic Devices(2/2)
Types of PLDs PROM: uses metal fuse that can be blown permanently)
EPROM: used programmable MOS transistors whose characteristicsare altering by applying a high voltage
PAL Programmable Array Logic
programmable AND logic array or AND plane,and fixed OR plane
PLA Programmable Logic Array
programmable AND planefollowed by programmable OR plane
Depending on howthe PLD is programmed
erasable PLD (EPLD)
mask-programmed PLD
Fi ld P bl G t A (FPGA)
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DAVIET Digital circuit logic Design Slide-34
Field-Programmable Gate Arrays (FPGA)
FPGA
a step above the PLD in complexity;
it is usually larger and more complex than a PLD rapidly growing in importance
Characteristics
none of mask layers are customized
a method for programming basic cellsand the interconnect
the core is regular arrayof programmable basic logic cells(combinational + sequential)
a matrix of programmable interconnectthat surrounds the basic cells
programmable I/O cells around the core design turnaround is a few hours
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DAVIET Digital circuit logic Design Slide-39
Economics of ASICs
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DAVIET Digital circuit logic Design Slide-40
Economics of ASICs
Goal
discuss the economics of using ASICs in a product andcompare the most popular types of ASICs:an FPGA, an MGA, and a CBIC
Warning!
costs change rapidly and IC industry is notorious for keepingits costs, prices, and pricing strategy closely guarded secrets,
so the numbers we will use to illustrate the differentcomponents of cost are approximate
Part cost
vary enormously: from a few dollars to several hundreds
FPGAs are more expensive per gate than MGAs
MGAs are more expensive per gate than CBICs
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DAVIET Digital circuit logic Design Slide-41
VLSI Design Cycle
VLSI Design Cycle (1/9)
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DAVIET Digital circuit logic Design Slide-42
VLSI Design Cycle (1/9)
System Specification
Architectural Design
Logic Design
Circuit Design
Physical Design
Functional Design Fabrication
Packaging
VLSI Design Cycle (2/9)
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DAVIET Digital circuit logic Design Slide-43
VLSI Design Cycle (2/9)
System SpecificationSpecification of the size,
speed, power and functionality of the VLSI system.Architectural DesignDecisions on the
architecture, e.g., RISC/CISC, # of ALUs, pipeline
structure, cache size, etc. Such decisions can
provide an accurate estimation of the systemperformance, die size, power consumption, etc.
VLSI Design Cycle (3/9)
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DAVIET Digital circuit logic Design Slide-44
VLSI Design Cycle (3/9)
Functional DesignIdentify main functional units
and their interconnections. No details ofimplementation.
VLSI Design Cycle (4/9)
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DAVIET Digital circuit logic Design Slide-45
VLSI Design Cycle (4/9)
Logic DesignDesign the logic, e.g., boolean
expressions, control flow, word width, registerallocation, etc. The outcome is called an RTL
(Register Trans fer Level) description. RTL is
expressed in a HDL (Hardw are Descrip t ion
Language), e.g., VHDL and Verilog.
X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)
VLSI Design Cycle (5/9)
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DAVIET Digital circuit logic Design Slide-46
VLSI Design Cycle (5/9)
Circuit DesignDesign the circuit including gates,
transistors, interconnections, etc. The outcome iscalled a netl ist.
VLSI Design Cycle (6/9)
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DAVIET Digital circuit logic Design Slide-47
VLSI Design Cycle (6/9)
Net list:
net1: top.in1 in1.innet2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Component list:
top: in1=net1 n1=topin1n2=topin2 n3=topineout=outnet
i1: in=net1 out=net2
xxx: xin1=topin1 xin2=topin2
xin3=botin1 B=net2out=net3
i2: in=net3 out=outnet
VLSI Design Cycle (7/9)
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DAVIET Digital circuit logic Design Slide-48
VLSI Design Cycle (7/9)
top
i1 xxx i2
Component hierarchy
VLSI Design Cycle (8/9)
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DAVIET Digital circuit logic Design Slide-49
VLSI Design Cycle (8/9)
Physical DesignConvert the netlist into a
geometric representation. The outcome is called alayout.
VLSI Design Cycle (9/9)
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DAVIET Digital circuit logic Design Slide-50
VLSI Design Cycle (9/9)
FabricationProcess includes lithography,
polishing, deposition, diffusion, etc., to produce achip.
PackagingPut together the chips on a PCB
(Printed Circu i t Board) or an MCM (Mult i -Chip
Module)
VLSI Design Cycle
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DAVIET Digital circuit logic Design Slide-51
VLSI Design Cycle
System Specification
Architectural
Specification
RTL in HDL
Netlist
Layout
Timing & relationship
between functional units
Chips
Packaged and
tested chips
Architectural
Design
Functional
Design
Logic
Design
Physical
Design
Fabrication
Packaging
Circuit Designor
Logic Synthesis
VLSI Design Process
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DAVIET Digital circuit logic Design Slide-52
VLSI Design Process
VLSI Design Process
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DAVIET Digital circuit logic Design Slide-53
VLSI Design Process
VLSI Design Process
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DAVIET Digital circuit logic Design Slide-54
VLSI Design Process
VLSI Design Process
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DAVIET Digital circuit logic Design Slide-55
VLSI Design Process
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DAVIET Digital circuit logic Design Slide-56
The Hard Part
A real design will have at least 1 million polygons and 100Ktransistors
Mistakes are really expensive
A full set of masks for 0.13 is about $600,000
Any single error in any of the polygons can ruin the chip
No one person can really comprehend 1 million of anything
Much less 1 billion
Need to attack the problem with the standard engineering tools
Hierarchy and abstraction
Design reuse
Computer automation
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DAVIET Digital circuit logic Design Slide-57
Design Methodologies and Flows
Left fork: Full customdesign flow
Center fork: Semi custom ASIC flow
Right fork: System on Chip
(SOC) flow
Full Custom Design Flow
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DAVIET Digital circuit logic Design Slide-58
Full Custom Design Flow
Has the best performance
Is the most labor intensive
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DAVIET Digital circuit logic Design Slide-59
Schematic Capture/Simulation
Circuit drawn at transistor,gate, and block level
Blocks can be recursivelyplaced inside one another
Utility programs producenetlists for simulation tools
Layout
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DAVIET Digital circuit logic Design Slide-60
Layout
Draw and place transistors for alldevices in schematic
Rearrange transistors tominimize interconnect length
Connect all devices with routinglayers
Possible to place blocks withinother blocks
Layout hierarchy shouldmatch schematic hierarchy
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DAVIET Digital circuit logic Design Slide-61
Design Rule Checking (DRC)
Fab has rules for relationships between polygons inlayout
Required for manufacturability
DRC checker looks for errors
width
space
enclosure
overlap
Violations flagged for later fixup
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DAVIET Digital circuit logic Design Slide-62
Layout Versus Schematic (LVS)
Extracts netlist from layoutby analyzing polygonoverlaps
Compares extracted netlist
with original schematicnetlist
When discrepancies occur,tries to narrow downlocation
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DAVIET Digital circuit logic Design Slide-63
Layout Parasitic Extraction (LPE)
Estimates capacitance between structures in the layout Calculates resistance of wires
Output is either a simulation netlist or a file of interblockdelays
Semi custom ASIC Design Flow
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DAVIET Digital circuit logic Design Slide-64
g
Separate teams todesign and verify
Physical design is(semi-) automated
Loops to get deviceoperating frequencycorrect can betroubling
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DAVIET Digital circuit logic Design Slide-65
Register Transfer Level (RTL)
Sections of combinational Goo separated by timingstatements
Defines behavior of part on every clock cycle boundary
Logic Synthesis
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DAVIET Digital circuit logic Design Slide-66
g y
Changes cloud of combinationalfunctionality into standard cells(gates) from fab-specific library
Chooses standard cell flip-flop/
latches for timing statements Attempts to minimize delay and
area of resulting logic
Standard Cell Placement and Routing
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DAVIET Digital circuit logic Design Slide-67
Place layout foreach gate(cell) in designinto block
Rearrange celllayouts tominimize routing
Connect up cells
System on Chip Design Flow
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DAVIET Digital circuit logic Design Slide-68
g
Can buy Intellectual Property (IP) from various vendors
Soft IP: RTL or gate level description
Synthesize and Place and Route foryour process.
Examples: Ethernet, MAC, USB
Hard IP: Polygon level description
Just hook it up
Examples: XAUI Backplane driver,embedded DRAM
Also: Standard cell libraries for ASIC flow
CAD Design Flow for SPLD
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FPGA Design Flow
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g
Design Entry
Design Implementation
Design Verification
FPGA Configuration
Design Entry
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DAVIET Digital circuit logic Design Slide-71
g y
Schematic HDL
Compile
Logic Equations
Minimize
ReducedLogic Equations
(Netlist)
Test vectors
Simulation
Design Implementation
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DAVIET Digital circuit logic Design Slide-72
g
Input:Netlist Output:bitstream
Mapthe design onto FPGA resources Break up the circuit so that each block has
maximum n inputs
NP-hard problem
However, optimal solution is not required
Design Implementation (Cont.)
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DAVIET Digital circuit logic Design Slide-73
Place:assigns logic blocks created during
mapping process to specific location on FPGA Goal: minimize length of wires
Again NP-hard
Route:routes interconnect paths between logic
blocks NP-hard
Design Implementation Techniques
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DAVIET Digital circuit logic Design Slide-74
Simulated annealing
Genetic algorithm Mincut method
Heuristic method
Design Verification & FPGA Configuration
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DAVIET Digital circuit logic Design Slide-75
Functional Simulation
Timing Simulation Download bitstream into FPGA
Advantages of FPLD compared with ASIC
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DAVIET Digital circuit logic Design Slide-76
A reduction in development time (rapid
propotyping) by 3 to 4 In-circuit reprogrammability
Lower NRE costs resulting in more ecomomical
designs for solutions requiring less than 1000 units
Comparison
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Technology Performance/
Cost
Time until
running
Time to high
performance
Time to change code
functionality
ASIC Very High Very Long Very Long Impossible
FPGA Medium Medium Long Medium
ASIP/
DSP
High Long Long Long
Generic Low-Medium Very
Short
Not
Attainable
Very Short
Speed
Flexibility