vhdl reference - fsm

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VHDL Reference - Finite State Machine

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  • 1. 2.5. FINITE STATE MACHINES IN VHDL 1232.5 Finite State Machines in VHDL2.5.1 Introduction to State-Machine Design2.5.1.1 Mealy vs Moore State MachinesMoore Machines ..................................................................... . s0/0 a !a Outputs are dependent upon only the state s1/1 s2/0 No combinational paths from inputs to outputs s3/0Mealy Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. s0 a/1 !a/0 Outputs are dependent upon both the state and the in- puts s1 s2 Combinational paths from inputs to outputs /0 /0 s32.5.1.2 Introduction to State Machines and VHDLA state machine is generally written as a single clocked process, or as a pair of processes, whereone is clocked and one is combinational.
  • 2. 124 CHAPTER 2. RTL DESIGN WITH VHDLDesign Decisions ..................................................................... . Moore vs Mealy (Sections 2.5.2 and 2.5.3) Implicit vs Explicit (Section 2.5.1.3) State values in explicit state machines: Enumerated type vs constants (Section 2.5.5.1) State values for constants: encoding scheme (binary, gray, one-hot, ...) (Section 2.5.5)VHDL Constructs for State Machines ..................................................The following VHDL control constructs are useful to steer the transition from state to state: if ... then ... else loop case next for ... loop exit while ... loop2.5.1.3 Explicit vs Implicit State MachinesThere are two broad styles of writing state machines in VHDL: explicit and implicit. Explicitand implicit refer to whether there is an explicit state signal in the VHDL code. Explicit statemachines have a state signal in the VHDL code. Implicit state machines do not contain a statesignal. Instead, they use VHDL processes with multiple wait statements to control the execution.In the explicit style of writing state machines, each process has at most one wait statement. Forthe explicit style of writing state machines, there are two sub-categories: current state and cur-rent+next state.In the explicit-current style of writing state machines, the state signal represents the current stateof the machine and the signal is assigned its next value in a clocked process.In the explicit-current+next style, there is a signal for the current state and another signal for thenext state. The next-state signal is assigned its value in a combinational process or concurrent state-ment and is dependent upon the current state and the inputs. The current-state signal is assignedits value in a clocked process and is just a opped copy of the next-state signal.For the implicit style of writing state machines, the synthesis program adds an implicit register tohold the state signal and combinational circuitry to update the state signal. In Synopsys synthesistools, the state signal dened by the synthesizer is named multiple wait state reg.In Mentor Graphics, the state signal is named STATE VARWe can think of the VHDL code for implicit state machines as having zero state signals, explicit-current state machines as having one state signal (state), and explicit-current+next state ma-chines as having two state signals (state and state next).
  • 3. 2.5.2 Implementing a Simple Moore Machine 125As with all topics in E&CE 327, there are tradeoffs between these different styles of writing statemachines. Most books teach only the explicit-current+next style. This style is the style closest tothe hardware, which means that they are more amenable to optimization through human interven-tion, rather than relying on a synthesis tool for optimization. The advantage of the implicit style isthat they are concise and readable for control ows consisting of nested loops and branches (e.g.the type of control ow that appears in software). For control ows that have less structure, itcan be difcult to write an implicit state machine. Very few books or synthesis manuals describemultiple-wait statement processes, but they are relatively well supported among synthesis tools.Because implicit state machines are written with loops, if-then-elses, cases, etc. it is difcult towrite some state machines with complicated control ows in an implicit style. The followingexample illustrates the point. a s0/0 s2/0 !a !a a s3/0 s1/1 Note: The terminology of explicit and implicit is somewhat standard, in that some descriptions of processes with multiple wait statements describe the processes as having implicit state machines. There is no standard terminology to distinguish between the two explicit styles: explicit-current+next and explicit-current.2.5.2 Implementing a Simple Moore Machine s0/0 entity simple is a !a port ( a, clk : in std_logic; s1/1 s2/0 z : out std_logic ); end simple; s3/0
  • 4. 126 CHAPTER 2. RTL DESIGN WITH VHDL2.5.2.1 Implicit Moore State Machine Flops 3architecture moore_implicit_v1a of simple is Gates 2begin Delay 1 gate process begin z

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