vhdl design automation using evolutionary...

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VHDL Design AutomationUsing Evolutionary Computation

Kazuyuki KojimaSaitama University

Japan

1. Introduction

This chapter describes the automatic generation method of VHDL which lays out the controllogic of a control system. This framework releases a designer from the work of describing theVHDL directly. Instead, the designer inputs the equation of motion of a system and targetoperation.

In this chapter, first, FPGA, CPLD, VHDL and evolutionary computation are outlined. Thisis basic knowledge required for an understanding of this chapter. Next, the frameworkof automatic generation of FPGA using evolutionary computation is described. VHDLdescription is expressed by several kinds of data structures called a chromosome. VHDLexpressed in a chromosome is changed using evolutionary computation and changes to amore suitable code for controller purposes. Finally two example applications are shown.The first one is the controller for a simple inverted pendulum. After that, the frameworkis applied to a more complicated system, an air-conditioning system. The simulation resultsshow that the controller automatically generated using this framework can control the systemappropriately.

2. Computer-aided controller design using evolutionary computation

2.1 FPGA/CPLD/ASIC and VHDL

CPLDs and FPGAs are both sorts of programmable LSIs. The internal logic of both can bedesigned using HDL. The ASIC is one example of a device that can be designed using HDLin the same way as programmable LSIs. CPLDs and FPGAs can be immediately evaluated onthe system for the designed logical circuit. In addition, they are flexible for the rearrangementof a specification. These merits make them suitable for the intended use in the case of arapid prototyping. For this reason, a CPLD is used as a controller. However, the proposedframework is applicable to all devices that can be designed by HDL. VHDL is one of the mostpopular HDLs and is therefore used in this paper.

The logic described by VHDL is verified and synthesized using a simulator or a logic synthesistool so that it can be written into a device. When CPLD or FPGA serves as target devices,the programming code which determines the function of the target device can be, through adownload cable, written into it in order to obtain the target LSI easily. The VHDL for a simplelogical circuit is shown in Fig. 1.

18

2 Will-be-set-by-IN-TECH

library IEEE;

use IEEE.std_logic_1164.all;

entity HALF_ADDER is

port(

A,B : in std_logic;

S,CO : out std_logic);

end HALF_ADDER;

architecture DATAFLOW of HALF_ADDER is

signal C, D : std_logic;

begin

C <= A or B;

D <= A nand B;

CO <= not D;

S <= C and D;

end DATAFLOW;

library IEEE;

use IEEE.std_logic_1164.all;

entity HALF_ADDER is

port(

A,B : in std_logic;

S,CO : out std_logic);

end HALF_ADDER;

architecture DATAFLOW of HALF_ADDER is

signal C, D : std_logic;

begin

C <= A or B;

D <= A nand B;

CO <= not D;

S <= C and D;

end DATAFLOW;

AB S

CO

AB S

CO

Fig. 1. VHDL for simple logical circuit

2.2 Genetic algorithm

The genetic algorithm used as a basis of this framework is outlined below (Fig. 2). Thedecision-variable vector x of an optimization problem is expressed with the sequence of Nnotations sj(j = 1, · · · , N) as follows:

x : s = s1s2s3 · · · sN (1)

It is assumed that symbol string is a chromosome consisting of N loci. sj is a gene in thej-th locus and value sj is an allelomorph. The value is assumed to be a real number, a merenotation, and so on of the group of a certain integer or a certain range of observations as anallelomorph. The population consists of K individuals expressed with Eq. (1). Individualpopulation p(n) in generation n changes to individual population p(n + 1) in next generationn + 1 through the reproduction of a gene. If reproduction in a generation is repeated andif the individual who expresses solution x nearer to an optimum value is chosen with highprobability, then the value increases and an optimum solution is obtained (Goldberg, 1989;Koza, 1994).

2.3 Evolvable hardware

Higuchi et al. proposed evolvable hardware that regards the architecture bit of CPLD as achromosome of a genetic algorithm to find a better hardware structure by genetic algorithm(Higuchi et al., 1992). They applied this to myoelectric controllers for electrical prosthetichands, image data compression and so on (Kajitani et al., 2005; Sakanasi et al., 2004). Thisapproach features coding of an architecture bit directly for a chromosome. The designermust determine which CPLD is used beforehand, implicitly determining the meaning of thearchitecture bit. If hardware is changed for the problem of circuit scale or structure, it isnecessary to recalculate evolutionary computation.

Henmi et al. evolved a hardware description language (HDL) called structured functiondescription language (SFL) and applied it to robot walking acquisition (Hemmi et al., 1997).

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VHDL Design Automation Using Evolutionary Computation 3

Crossover

Mutation

Selection

n th generation n+1 th generation

0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 0Chromosome

Gene

x: s = s1 s2 s3 … sN

p(n) p(n+1)

Crossover

Mutation

Selection

n th generation n+1 th generation

0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 00 1 0 0 0 1 1 1 0 1 0 0 1 0 1 0Chromosome

Gene

x: s = s1 s2 s3 … sN

p(n) p(n+1)

Fig. 2. Genetic algorithm overview

The basic motion, called an "action primitive", must be designed in a binary string. Inour approach, the designer needs only to define I/O pins for CPLD. VHDL rather than anarchitecture bit is coded directly onto the chromosome, so the chromosome structure does notdepend on CPLD scale or type, and after VHDL is generated automatically, CPLD is selectedappropriately to the VHDL scale. Pin assignment is set after VHDL generation.

2.4 Controller design framework using evolutionary computation

The study of optimizing rewritable logical-circuit ICs, such as CPLD, using a geneticalgorithm has increased. The framework that changes an internal logic circuit IC configurationto attain evolution is called evolvable hardware (EHW). With this framework, the designerneeds only to define the criteria used to evaluate a controller. We explain the controller designframework using evolutionary computation with XC95144 (Xilinx, 1998) as the test device.Internal blocks of XC95144 are shown in Fig. 3. XC95144 is a small CPLD that has 144 pins(117 user input-outputs), 144 macro cells and 3200 usable gates. A designer chooses input andoutput signals from 117 user I/Os and assigns these pins. Each signal is defined for each I/O.If CPLD is used in control, sensors and actuators can be associated with CPLD I/O pins (Fig.4). Here, I/O pins are associated with two sensors and one actuator. The sensor values areinputs to CPLD as two 16-bit digital signals and a 10-bit digital signal is output as a referencesignal to the actuator.

VHDL, which describes internal CPLD logic, is encoded on a chromosome. An example ofthe VHDL generated is shown in Fig. 5, corresponding to Fig. 4. This VHDL consists ofthree declarations — (a) entity declaration, (b) signal declaration, and (c) architecture body.CPLD I/O signals are defined in (a) and internal CPLD signals are in (b). Signals mainly usedin VHDL are a std_logic type and a std_logic_vector type. The std_logic typeis used when dealing with a signal alone and the std_logic_vector type is used whendealing with signals collectively. The std_logic and the std_logic_vector types shouldbe combined to optimize maintenance and readability. A description of VHDL can be restoredif all of the input output signals and internal signals are used as the same std_logic typeand only the number is encoded on a chromosome. The number of input signals, output

359VHDL Design Automation Using Evolutionary Computation


JTAG Port

I/O

I/OI/O

I/O

I/O

I/OI/O

I/OI/O/GCKI/O/GSRI/O/GTS

JTAGController In-System Programming Controller

I/O B

lock

s

Fast

CO

NN

EC

T S

witc

h M

atrix

31

1854

1854

1854

1854

3

14

FunctionBlock 1

FunctionBlock 2

FunctionBlock 3

FunctionBlock 4

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

117

Fig. 3. XC95144 architecture

I/O B

lock

s

I/OI/O

I/OI/O

I/OI/OI/O

I/OI/O

I/OI/OI/O

I/OI/OI/O

Sensor1 ( 16 bit input )

Actuator1 ( 10 bit output )

Sensor2 ( 16 bit input )

Fig. 4. Example of CPLD application

signals and internal signals are encoded on the head of a chromosome (Fig. 6). In Fig. 4, twoinput signals are set up with 16 bits and an output signal with 10 bits.

A chromosome that represents a VHDL assignment statement is shown in Fig. 7. Achromosome structure corresponding to a process statement is shown in Fig. 8. The valuecurrently described is equivalent to the process statement in which "DI009" and "DI014" areenumerated in the sensitivity list.

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000: -------------------------------------------------------------------------------001: -- VHDL for I/P controller generated by _hiGA_AC with _hiGA.dll

002: -- (c) 2011, Saitama Univ., Human Interface Lab., programmed by K.Kojima003: -- Chromo#:E/50 Length:13 Inputs:32 Outputs:10 Signals:2004: -- Simulation: Initial condition: 180.0, dt=0.0100005: -------------------------------------------------------------------------------

006: library IEEE;007: use IEEE.std_logic_1164.all;008: use IEEE.std_logic_arith.all;

009: use IEEE.std_logic_unsigned.all;010:011: entity GA_VHDL is

012: port(013: DI000 : in std_logic;014: DI001 : in std_logic;015: DI002 : in std_logic;

016: DI003 : in std_logic;017: DI004 : in std_logic;018: DI005 : in std_logic;


022: DI009 : in std_logic;023: DI010 : in std_logic;024: DI011 : in std_logic;025: DI012 : in std_logic;



032: DI019 : in std_logic;033: DI020 : in std_logic;034: DI021 : in std_logic;035: DI022 : in std_logic;



042: DI029 : in std_logic;043: DI030 : in std_logic;044: DI031 : in std_logic;045: DO000 : out std_logic;

046: DO001 : out std_logic;047: DO002 : out std_logic;048: DO003 : out std_logic;

049: DO004 : out std_logic;050: DO005 : out std_logic;051: DO006 : out std_logic;

052: DO007 : out std_logic;053: DO008 : out std_logic;054: DO009 : out std_logic055: );

056: end GA_VHDL;057:

��

Fig. 5. (a) Automatically generated VHDL (List-1)

The VHDL description has an if-statement inside of a process statement and the descriptionhas two nesting levels. The hierarchy of the list structure is deep compared to the substitutionstatement. When the gene of such a multilist structure is prepared, it is possible to representvarious VHDL expressions.

2.5 Variable length chromosome and genetic operations

The structure of a chromosome changes with the control design specification. The numberof internal signals is set arbitrarily and different descriptions in VHDL are expressed withdifferent locus lengths. The length of a chromosome is determined by the VHDL line count.The length determines the number of internal signals enumerated on the sensitivity list or



058: architecture RTL of GA_VHDL is059:

060: signal S000 : std_logic;061: signal S001 : std_logic;062:063: begin

064:065:066: process(DI013) begin

067: S000 <= not DI013;068: end process;069:

070:071: process(DI002, DI009) begin072: S001 <= DI009;073: end process;

074:075: DO000 <= (((DI002 or not DI011) nor DI002) nand DI003);076: DO001 <= (((((((((((((((((((((((((((((DI028 nor not DI011) or DI001) or

077: DI008) nor DI017) and not DI008) nor DI016) or not DI030) or DI025) or not078: DI015) or not DI010) and DI010) nand not DI028) nand not DI010) and not DI012)079: and DI008) nand DI002) or not DI009) nor not DI031) nor DI007) nor not DI009)

080: nand DI023) or DI014) nor DI019) and not DI025) nand DI024) nand not DI010) or081: not DI031) nor not DI019) nand DI000);082:083: process(DI006, DI029, DI014) begin

084: DO002 <= ((not DI014 or DI029) or DI006);085: end process;086:

087:088: process(DI029) begin089: DO003 <= DI029;

090: end process;091:092:093: process(DI009, DI014) begin

094: if(DI009'event and DI009='0')then095: DO004<=DI009 nand not DI007;096: end if;

097: end process;098:099: DO005 <= ((((((((((((((((((((((((((((DI014 and DI016) nand not DI007) and

100: not DI022) nor not DI005) nand DI018) nor DI021) and not DI000) nand not DI013) or101: not DI022) or DI030) or not DI027) and DI031) and DI020) or DI023) nor not DI025)102: or not DI000) nor DI002) nand DI002) and not DI027) nand not DI017) nand not103: DI025) nand not DI007) nor DI031) and DI012) nand not DI012) or not DI030) nand

104: not DI026) and not DI011);105: DO006 <= ((((((((((((((((((((((((DI010 and not DI028) nand DI009) nor DI011) nand106: not DI016) or DI029) nand not DI001) and DI011) or DI017) or DI011) nand not

107: DI030) nor DI022) or not DI005) or DI001) and DI019) nor DI027) nand DI010) or not108: DI025) or not DI023) and DI019) or not DI019) and DI023) nor not DI008) or not109: DI005) nand not DI021);

110: DO007 <= DI009;111:112: process(DI025, DI013, DI023) begin113: DO008 <= not DI023;

114: end process;115:116:

117: process(DI014, DI024) begin118: DO009 <= DI014;119: end process;

120:121:122: end RTL;

��

��

��

��

Fig. 5. (b) Automatically generated VHDL (List-2)

the length of the right-hand side of an assignment statement. When dealing with such avariable length chromosome, the problem is that genetic operations will generate conflict ona chromosome. To avoid this problem, we prepared the following restrictions:

1. With a top layer, the length of a chromosome is equal to the number that added one to thesummary of the number of internal signals and the number of output signals.

2. All signals are encoded on a chromosome using a reference number.

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Number of inputs

Number of outputs

Number of signals

Chromosome

1st locus 32

10

2

Fig. 6. Signal definition on the first locus

Chromosome

n th locus

Architecture body

Reference No.

Command ID

ID

ID_CMD_SUBSTITUTION

Left term

35

1st Right term

Reference No. not

Right terms

Reference No. not Operator

3 0

112 ID_OP_OR

Fig. 7. Gene structure for assignment statement

3. The signal with a large reference number is described by only the signal whose referencenumber is smaller than the signal.

4. The top layer of a chromosome describes the entity declaration using all internal signalsand output signals in order with a low reference number. Each signal can be used onlyonce.

5. Crossover operates on the top layer of a chromosome.

These restrictions avoid the conflict caused by genetic operations.

Figure 9 shows an example of crossover operation. The back of the 6th gene is chosen in thisexample. Chromosome (A) and chromosome (B) cross and change to chromosome (A’) andchromosome (B’). Only the gene before and behind the crossover point of each chromosome



Chromosome

n th locus

Architecture body

Command ID

ID

ID_CMD_PROCESS_SENSITIVITY

Sensitivity list

10

Process body

ID_CMD_PS_IFTHENELSE

[0] [1]15

ID

Command ID

Reference No.

Event

Edge

Substitution

Reference No.

Left term

38

1st Right term

Reference No. not

Right terms

Reference No. not Operator

10 0

18 ID_OP_NAND

10

1

0

Fig. 8. Gene structure for if-then-else statement in process body

show the gene of a lower layer. In the figure, chromosome (A) has two sensitivity lists andchromosome (B) has two assignment statements. The structure of a chromosome changes byreplacing the gene from the back of a top gene to before a crossover point. Both chromosome(A’) and chromosome (B) came to have an assignment statement and a sensitivity list.

3. Application to HDL-based controller of inverted pendulum

In this section an application to an HDL-based controller for the inverted pendulum isdescribed (Kojima, 2011).

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Chromosome (A)Crossover point

Crossover point

Crossover point

Chromosome (B)

Chromosome (A’)

Chromosome (B’)Crossover point

ID

5 16

IDID

5 16

2 162 16

5 165 16

2 162 16

Chromosome (A)Crossover point

Crossover point

Crossover point

Chromosome (B)

Chromosome (A’)

Chromosome (B’)Crossover point

ID

5 16

IDID

5 16

2 162 16

5 165 16

2 162 16

Fig. 9. Crossover operation

θ

lz

c1θ

c2z

f

d

m, J

M

Fig. 10. Inverted pendulum

3.1 Equations of motion

Figure 10 shows the model of the inverted pendulum. The equations of motion are given by

(ml2 + J)θ = mgl sin θ − mlz cos θ − c1 θ + d (2)

(M + m)z = f − c2 z (3)



CPLD

A/D

A/D

Motor Driver Inverted Pendulum

10

Duty

PWM

16

16

Position

Angle θz

Fig. 11. Control system block diagram

I/O B

lock

s

I/OI/O

I/OI/O

I/OI/OI/O

I/OI/O

I/OI/OI/O

I/OI/OI/O

Angle ( 16 bit input )

Duty ( 10 bit output )

Position ( 16 bit input )

Fig. 12. CPLD pin assignment

f = Kv (4)

where θ [rad] is the angle of the pendulum, m [kg] is the mass of the pendulum, M [kg] is themass of the cart, J [kgm2] is the inertia of the rod, l [m] is the length between the gravity pointand fulcrum, z [m] is the position of the cart, d [Nm] is the disturbance torque, c1 [Ns/rad] isthe viscous resistance of the pendulum, c2 [Ns/m] is the viscous resistance of the cart, f [N]is the controlling force, v is the parameter for the control input and K is the gain. J, a and b aredefined as:

J = J + ml2 (5)

a =c2

M + m(6)

b =K

M + m(7)

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then, equations (2) and (3) become:

θ =mgl

Jsin θ − mlz

Jcos θ − c1

Jθ +

dJ

(8)

z = −az + bv. (9)

Each parameter can be determined by measurement and experiment as l = 0.15, m = 46.53 ×10−3, J = 1.58× 10−3, c1 = 2.05× 10−2, a = 4.44 and b = 2.46× 10−1. Using these parameters,evolutionary simulations are conducted.

3.2 Control system and CPLD pin assignment

Figure 11 shows the control system block diagram. The CPLD is used as the controller of theinverted pendulum. The position of the cart and the angle of the pendulum are converted16 bit digital signals respectively and input to the 32 CPLD pins. The control logic in theCPLD, which is formed using the framework previously mentioned, determines the 10 bitcontrol signal driving the motor of the inverted pendulum. Figure 12 shows the CPLD pinassignment for this application. In this case, 32 bit parallel inputs and 10 bit parallel outputsare adopted. Instead of using them, we can use serial I/Os connected with A/D convertersand D/A converters. In this case, serial to parallel logics should be formed in the CPLD andeven though serial inputs are used, automatically generated VHDL can be used as a VHDLcomponent.

3.3 Fitness

The fitness value is calculated as a penalty to the differences in the rod angle and the cartposition.

fitness = − 1π

∫ 30

0|θ|dt −

∫ 30

0|z|dt (10)

Disturbances are given as a random torque during the control simulation. When calculatingfitness value, disturbance torque is always initialized. Therefore, all individuals are givendifferent disturbance at each evaluation. This kind of disturbance makes the controller robustto various disturbances.

3.4 Simulation

Simulations are conducted under two conditions – (1) θ0 = 1◦, z0 = 0, (2) θ0 = 180◦, z0 =0. Population size is 50, mutation rate is 0.5, crossover rate is 1.0, tournament strategy,tournament size is 10 and the elite strategy is adopted.

Figures 13 and 14 show the simulation results. Figure 13 shows the result of condition (1),Figure 14 shows the result of condition (2). (a) the result at 0 generation and (b) the resultat 1000 generation are represented respectively. The angle of the rod, the position of thecart, disturbance and the control signal are shown at each generation. At zero generation,in both conditions (1) and (2), the obtained controller cannot control the inverted pendulumadequately. The rod moves in a vibrating manner at around 180◦. At 1000 generation,the controller controls the inverted pendulum successfully in both conditions. Further, incondition (2), swing up motion can be observed (Fig.14(b)). The control signal at 1000generation has more various patterns than the signal at 0 generation.



(a) 0th generation

(b) 1000th generation

Fig. 13. Simulation results ( θ0 = 1◦, z0 = 0 )

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(a) 0th generation


Fig. 14. Simulation results ( θ0 = 180◦, z0 = 0 )



4. Application to an air-conditioning controller

Next, the framework is applied to an air-conditioning controller. Simulation model, taskdefinition and fitness function are described in this section. Simulation results will be shownat the end of the section (Kojima et al., 2007; Kojima, 2009).

4.1 Simulation model

In the targeted air-conditioning system(Fig. 15), the outside air imported is cooled or warmedand sent to the console to adjust temperature. Air entering from the inlet (a) is cooled by therefrigerator (c). Part of the cooled air is warmed with a heater (e), then mixed with cool air toadjust the temperature. The angle of the mixture door (d) controls the mixing ratio of warmand cold air. Mixed air is sent to console (f), changing the indoor temperature. The systemcontroller controls blower motor rotation and the angle of the air mixture door.

Outdoor

(b) Blower (d) Air mixture door

(e) Heater(f) Console

(c) Refrigerator

5 80

Full cool 0%Full hot 100%

Air temperature 30Humidity 50%

500 m3/h max.

(0) (2)(1)

(3)

(4)

(5)(6)

(8)(7)(a) Inlet

Outdoor

(b) Blower (d) Air mixture door

(e) Heater(f) Console

(c) Refrigerator

5 80

Full cool 0%Full hot 100%

Air temperature 30Humidity 50%

500 m3/h max.

(0) (2)(1)

(3)

(4)

(5)(6)

(8)(7)(a) Inlet

Fig. 15. Air-conditioning system

Fig. 16. Control volumes

To evaluate the controller performance, an air-conditioning simulation model is required inevolutionary computation. We consider an air-conditioning model combining the console andduct using nine control volumes (Fig. 16). Temperature and humidity, but not compressibility,are considered in this model. To calculate the predicted mean vote (PMV), which indicatesthermal comfort, we require globe temperature, metabolization, flow rate, insulation ofclothes and external work.

Figure 16 shows three control volumes in this system. We assume that air flows towardthe control volume indexed with (i + 1) from the control volume indexed with (i). Airtemperature Ti+1[K] and relative humidity φi+1 vary with temperature Ti[K], relative

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humidity φi, mass flow Gi[kg/s] and heat transfer Q[kJ/s]. In air-conditioning simulation,mass flow is proportional to the opening of blower motor α.

G0 = Gi = αGmax (0 ≤ α ≤ 1) (11)

where Gmax is maximum flow at full blower opening. Flow rate G0 is the sum of air flow Ga0and steam flow Gw0.

G0 = Ga0 + Gw0 (12)

Water vapour pressure Pw0 is as follows:

Pw0 = φ0 · Ps0 (13)

where Ps0 saturation water vapour pressure from Tetens’ formula (Tetens, 1930):

Ps0 = 610.78 × e17.2694(T0−273.15)(T0−273.15)+238.3 (14)

Specific humidity x0 is given by water vapour pressure Pw0.

x0 = 0.622Pw0

P0 − Pw0(15)

Air mass flow Ga0 is calculated from the following gas equation:

Ga0 = Pa0 · VRaT0

(16)

where Ra is a gas constant. Water vapour mass flow Gw0 is given by:

Gw0 = x0 · Ga0 (17)

Air flow rate Ga is constant. Steam flow Gw is constant except during dehumidification.Considering the air flow into control volume (i) from control volume (i − 1) in unit timedt[s], temperature T′

i , humidity x′i and mass of control volume M′i after dt is given as follows:

T′i =

Gi−1Ci−1Ti−1dt + (Mi − Gidt)CiTiGi−1Ci−1dt + (Mi − Gidt)Ci

+QidtMiCi

(18)

x′i =Mixi + (1 + xi)(Gwi−1 − Gwi)dt

Mi + (1 + xi)(Gai−1 − Gai)dt(19)

M′i = Mi + (Gi−1 − Gi)dt (20)

where specific heat Ci[kJ/kg · K] is given by

Ci =1.005 + xi{(2501.6/Ti) + 1.859}

1 + xi(21)

At the mixture door, air is divided into two flows. The ratio of the mass of divided air dependson the mixture door angle. Here G1 is the mass flow at location (1) in Fig. 15, G2 that at location(2) and G3 that at location (3),

G2 = βG1 (22)



G3 = (1 − β)G1 (23)

where β (0 ≤ β ≤ 1) is the opening ratio of the mixture door. Adding two mass flow ratesenables us to calculate the downstream mass at a juncture. Here G4 is the mass flow at location(4) in Fig.15, G5 that at location (5) and G6 that at location (6),

G6 = G4 + G5 (24)

Temperature and humidity at a juncture are given in the same way as for when three controlvolumes are considered.

4.2 Predicted mean vote (PMV)

PMV is the predicted mean vote of a large population of people exposed to a certainenvironment. PMV represents the thermal comfort condition on a scale from -3 to 3, derivedfrom the physics of heat transfer combined with an empirical fit to sensation. Thermalsensation is matched as follows: "+3" is "hot." "+2" is "warm." "+1" is slightly warm." "0" is"neutral." "-1" is slightly cool." "-2" is "cool." "-3" is "cold." Fanger derived his comfort equationfrom an extensive survey of the literature on experiments on thermal comfort (Fanger,1970). This equation contains terms that relate to clothing insulation Icl[clo], metabolicheat production M[W/m2], external work W[W/m2], air temperature Ta[◦C], mean radianttemperature Tr[◦C], relative air speed v[m/s] and vapour pressure of water vapour P[hPa].

PMV = {0.33 exp(−0.036M) + 0.028}[(M − W)

−3.05{5.73 − 0.007(M − W)− P}−0.42{(M − W)− 58.1}−0.0173M(5.87 − P)

−3.96 × 10−8 fcl{(Tcl + 273.15)4

− (Tmrt + 273.15)4}

− fclhc(Tcl − Ta)]

(25)

fcl is the ratio of clothed and nude surface areas given by:

fcl = 1.0 + 0.2Icl(Icl ≤ 0.5)fcl = 1.05 + 0.1Icl(Icl > 0.5) (26)

where Tcl is the clothing surface temperature given by repeated calculation of:

Tcl = 35.7 − 0.028(M − W)

−0.155Icl

[3.96 × 10−8 fcl{(Tcl + 273.15)4

−(Tmrt + 273.15)4}+ fclhc(Tcl − Ta)]

(27)

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where hc is the heat transfer coefficient,

hc = max{2.38(Tcl − Ta)0.25, 0.0121

√v} (28)

and Tmrt is mean radiant temperature. PMV is detailed in (Fanger, 1970).

4.3 Task definition

The task is to adjust PMV in the console despite heat transfer from outside changes. Theair-conditioning controller controls the opening ratio of blower n and the opening ration ofmixture door m appropriately.

4.4 Control system and CPLD pin assignment

Figure 17 shows the control system block diagram. PMV is input to the CPLD as a 8 bit signal.The control logic in the CPLD determines the 8 bit blower opening control signal and the 8 bitmixture door control signal. Figure 18 shows the CPLD pin assignment for this application.

PMV8

8

8

Blower opening

Mixture door openingCPLD

Fig. 17. Control system block diagramI/O

Blo

cks

I/O

I/OI/O

I/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/O

I/OI/OI/OI/O

PMV ( 8 bit input )

Mixture door ( 8 bit output )

Blower motor ( 8 bit output )

I/O B

lock

s

I/O

I/OI/O

I/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/O

I/O

I/OI/O

I/OI/O

I/OI/O

I/O

I/OI/OI/OI/O

PMV ( 8 bit input )

Mixture door ( 8 bit output )

Blower motor ( 8 bit output )

Fig. 18. Control system block diagram



4.5 Fitness

The fitness function is as follows:

fitness = −∫ tend

0|PMVctrl − PMVtarget|dt (29)

where tend is the end of simulation time. The difference between target and controlled PMV isintegrated as a penalty in the controller simulation.

4.6 Simulation results

Blower

Mix-door

(a) 0th generation

Blower

Mix-door


Blower

Mix-door

(c) 10000th generation

Fig. 19. Simulation results

Figure 19 shows the simulation results. PMV in a console is fed back to the controller. In thegraphs, trends change every 60 seconds. Variations are based on the load effect change each60 seconds. At zero generation (Fig. 19 (a)), temperature rises or falls with the change in heatload. PMV also changes simultaneously. This means that simply optimizing a controller isnot enough. After 100 generations of calculation, the difference between the target and the

374 Automation


estimated value decreases (Fig. 19 (b)). In the 10,000th generation (Fig. 19 (c)), tolerancedecreases further. These results show that hardware corresponding to the purpose is obtainedautomatically using this framework.

Figure 20 shows simulation results under other conditions. Nine graphs result for threethermal loads. Three graphs — temperature, PMV and control — are shown for each thermalcondition. The controller used under three conditions was obtained after 10,000 generationsof calculation. Although thermal load and load change timing were random, the blower andmix door were controlled so that PMV is set to zero.

Blower

Mix-door

Blower

Mix-door

Blower

Mix-door

Fig. 20. Simulation results

5. Conclusion

In this chapter, to automate controller design, CPLD was used for controller data-processingand VHDL to describe the logical circuit was optimized using the genetic algorithm. Twoexample cases (an inverted pendulum and an air-conditioner) were shown and we confirmedthis framework was able to be applied to both systems. Since this framework is a generalizedframework, so in these kinds of systems which process data from some sensors and drivesome actuators, this framework will work functionally.



6. References

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Barate, R. & Manzanera, A. (2008). Evolving Vision Controllers with a Two-Phase GeneticProgramming System Using Imitation, Proceedings of the 10th international conferenceon Simulation of Adaptive Behavior: From Animals to Animats, pp.73-82, ISBN:978-3-540-69133-4, Osaka, July 2008.

Fanger, P. O. (1970). Thermal Comfort, McGraw-Hill.Goldberg, D. E. (1989). Genetic Algorithm in Search, Optimization and Machine Learning,

Addison-Wesley.Hemmi, H., et al., (1997). AdAM: A Hardware Evolutionary System, Proc. 1997 IEEE Conf.

Evolutionary Computat.(ICEC’97), pp.193-196.Higuchi, T. et al. (1992). Evolvable Hardware with Genetic Learning: A First Step Towards

Building a Darwin Machine, Proceedings of the 2nd International Conference on theSimulation of Adaptive Behavior, MIT Press, pp.417-424.

Kajitani,I. & Higuchi, T. (2005). Developments of Myoelectric Controllers for Hand Prostheses,Proceedings of the Myoelectric Controls Symposium 2005, pp.107-111, Fredericton,August 2005.

Kojima, K. et al. (2007). Automatic Generation of VHDL for Control Logic of Air-ConditioningUsing Evolutionary Computation, Journal of Advanced Computational Intelligence andIntelligent Informatics, Vol.11, No.7, pp.1-8.

Kojima, K. (2009). VHDL Design Automation Using Evolutionary Computation, Proceedingsof 2009 International Symposium on Industrial Electronics (IEEE ISIE 2009), pp.353-358,Seoul, July 2009.

Kojima, K. (2011). Emergent Functions of HDL-based Controller of Inverted Pendulum inConsideration for Disturbance, Proceedings of 2011 IEEE/SICE International Symposiumon System Integration, Kyoto, December 2011.

Koza, J. (1994). Genetic Programming, A Bradford Book, ISBN0262111705.Sakanashi, H. et al., (2004). Evolvable Hardware for Lossless Compression of Very High

Resolution Bi-level Images, IEEE Proceedings-Computers and Digital Techniques,Vol.151, No.4, pp.277-286, Ibaraki, August 2004.

Tetens, O. (1930). Uber einige meteorologische Begriffe, Zeitschrift fur Geophysik, Vol.6, pp.297-309.(in German)

wyns10] Wyns, B., et al., (2010). Evolving Robust Controllers for Corridor FollowingUsing Genetic Programming, Proceedings of the International Conference on Agents andArtificial Intelligence, volume 1 : artificial intelligence; pp.443-446, Valencia, January2010.

Xilinx. (1998). DS056(v.2.0) XC95144 High Performance CPLD Product Specification, Xilinx; 2.

376 Automation

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