verilog for design - indian statistical instituteansuman/vlsitv/verilogintro.pdf · • cadence...

Verilog for design

History of Verilog

• Gateway Design Automation started developing this language in 1985

• Phil Moorby designed the basic language and the simulator

• Cadence Design System acquired Gateway in 1989

• Cadence opens Verilog in 1990

History of Verilog (contd.)

• OVI (Open Verilog International): 1990• 1993-1995 IEEE standardized 1364 LRM• OVI merged with IEEE• OVI proposes Verilog-AMS• IEEE standardized Verilog 2000 LRM

What is Verilog?• Most popular Hardware Description Language (HDL)• Easy to learn and master – syntactically similar to C• Can be used to model system in almost all stages of EDA flow

– Behavioural– RTL– Structural– Switch– Analog – Verilog AMS

• Enhanced and exists in different version– Verilog 95– Verilog 2001 (V2K)– System Verilog (SV)

• This training will follow Verilog 95 standard and its design aspects

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Structural design• AOI – AND OR INVERT

• 4 gates to describe– 2 AND gates– 1 OR gate– 1 INVERTER

• Interconnection between gates

• Verilog defines module as a unit of boolean logic

• Module will have input and output ports

• Output ports will be driven by some boolean equations with input ports as parameters

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AB

CD

Y

AB

CD

YY = AOI(A,B,C,D)

module

Input ports

Output port

Structural representation• AOI module • Verilog file AOI.v

// AOI module definitionmodule AOI(A, B, C, D, Y);// port declarationinput A, B, C, D;output Y;// internal wire declarationwire e, f, g;// gate instantiationsand i1(e, A, B);and i2(f, C, D);or i3(g, e, f);not i4(Y, g);endmodule

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AB

CD

Y

e

f

gi1

i2i3 i4

Module definition• AOI module • Verilog file AOI.v


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AB

CD

Y

e

f

gi1

i2i3 i4

Port declarations• AOI module • Verilog file AOI.v


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AB

CD

Y

e

f

gi1

i2i3 i4

Internal net declarations• AOI module • Verilog file AOI.v


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AB

CD

Y

e

f

gi1

i2i3 i4

Instantiations• AOI module • Verilog file AOI.v


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AB

CD

Y

e

f

gi1

i2i3 i4

Behavioral representation• AOI module • Verilog file AOI.v

// AOI module definitionmodule AOI(A, B, C, D, Y);// port declarationinput A, B, C, D;output Y;// boolean logic equationassign Y = ~((A & B) | (C & D));endmodule

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AB

CD

Ylogic cloud

Test AOI - testbench• To test AOI

– Drive input ports– Monitor or check output ports

• To drive input ports– Use columns of truth-table– Driving value set is known as

test-vector

• A top-level Verilog module is created known as testbench

• Testbench will instantiate AOI module

• Testbench will use a block for driving test-vectors

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AB

CD

Y

test-vectors

0110

AOI module

A

BC

D

YAOI

testbench

test-vector driver block

Verilog testbench• Testbench module

– No ports– Instantiates AOI

• Verilog file testbench.vmodule testbench;reg TA, TB, TC, TD;wire TY;// module instantiationAOI inst1(TA, TB, TC, TD, TY);initial // drive test vectorsbegin

TA = 1’b0; TB = 1’b0;TC = 1’b0; TD = 1’b0;

#10 TD = 1’b1;#10 TC = 1’b1; TD = 1’b0;#10 TD = 1’b1;#10 TB = 1’b1;

TC = 1’b0; TD = 1’b0;endendmodule

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A

BC

D

Yinst1

testbench


TA

TBTC

TD

Reg declaration for test-vectors• Testbench module • Verilog file testbench.v

module testbench;reg TA, TB, TC, TD;wire TY;// module instantiationAOI inst(TA, TB, TC, TD, TY);initial // drive test vectorsbegin

TA = 1’b0; TB = 1’b0;TC = 1’b0; TD = 1’b0;



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A

BC

D

YAOI

testbench

TA

TBTC

TD


Driver block generating test-vectors

• initial block

– Uses truth table columns

• Verilog file testbench.vmodule testbench;reg TA, TB, TC, TD;wire TY;// module instantiationAOI inst(TA, TB, TC, TD, TY);initial // drive test vectorsbegin

TA = 1’b0; TB = 1’b0;TC = 1’b0; TD = 1’b0;



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A

BC

D

YAOI

testbench

TA

TBTC

TD

A B C D Y0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1


Monitor block for outputs• Whenever output value

changes, monitor should display that

0: 0000 : 110: 0001 : 120: 0010 : 130: 0011 : 040: 0100 : 1

• Verilog file testbench.vmodule testbench;reg TA, TB, TC, TD;wire TY;// module instantiationAOI inst(TA, TB, TC, TD, TY);initial // monitor outputbegin// VCD waveform capture$dumpvars;// Log based data monitor$monitor($time, “: “,TA, TB, TC, TD, “ : “, TY);

// Control simulation time#100 $finish;

endendmodule

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Concurrent execution units• Verilog module can have following concurrent execution units

– Continuous assignment statements – assign– Instantiations (module, gate, udp etc)– Initial block – initial– Always block – always

• Such units can execute concurrently – irrespective of where they are declared

• Each of such unit represents logic cones driving internal reg / wires or output / inout ports (ports are by of default wire type)

• Instantiation and assign statements can only drive wires• initial and always blocks can only drive reg signals

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Continuous assignmentwire x;assign x = a + b – c * d;

• Continuous assignments represents a wire driven by a logic cone i.e. boolean equation.

• Executes whenever there is any change in any driving net of the logic cone

• Wires are only driven as wires can be driven continuously

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x

a

b

c

d

Module instantiationwire x, y, z;AOI i1(a, b, c, d, x);AOI i2(e, f, c, g, y);AOI i3(b, h, x, y, z);

• Module instantiation will a insert a copy of a parent / instantiating module in the upper module

• Only wires can be connected to the output / inout ports of the instances

• Each instance of same parent module will represent distinct unit of logic

– There will be no sharing or interference of logic between two instances of same parent module

– Instances are copy of the entire logic of the parent module

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abcd

ef

h

g

z

x

y

i1

i2i3

Initial blockreg x, y;initialbegin

x = 1’b0; y = 1’b0;#20 x = 1’b1;#10 x = 1’b0; y = 1’b1;#50 y = 1’b0;#30 x = 1’b1; y = 1’b1;

• Initial block is mainly used in testbench for generating directed test-vectors

• Executes once and starts at the beginning of the simulation

• Can only drive reg signals• Represents a timed sequence of

signal values – waveform– Timing delays are used to create

the timed sequence– If no timing delay or waits are

used, initial block ends instantaneously at zero time

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Examples of initial block• Clock generator// Clock generatormodule clockgen(clock);parameter period = 10;output clock;reg clock;initialbegin

clock = 1’b0;forever

#(period/2) clock = ~clock;endendmodule

• Common timing controls used in initial blocks– Timing delays / waits

• #10;• wait(10);• @(x or y);

– System tasks• $display• $monitor• $dumpfile• $dumpvars• $stop• $finish

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Random test-vector generation and self-checking of AOI module

• Testbench module module testbench;parameter N = 10;reg TA, TB, TC, TD;wire TY;AOI inst(TA, TB, TC, TD, TY);initial begin // random test generator

repeat (N)#10 { TA, TB, TC, TD } = $random;

#10 $finish;endinitial // self checking blockforever begin

@(TA or TB or TC or TD or TY) #1;if (TY != ~((TA & TB) | (TC & TD)))$display(“ERROR[%0d]: ”, $time,TA, TB, TC, TD, “ : “, TY);

endendmodule

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Random test-vector generator initial block

Self-checkinginitial block

Top level testbench module

Always block• Difference between initial and

always block executions• Always block is used for

implementation of– Complex combinational logic– Sequential logic - flip flop– Finite state machine (FSM)

• Executes repeatedly infinite number of times

• Can only drive reg signals• Triggered by any change in signals

in the sensitivity list– @(x or y or z)– @(posedge clock)

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initial block always block

Start of simulation

End of simulation

combinational always• 2x1 Multiplexer

always @(s or a or b)if (s)q = a;

elseq = b;

• ALU

always @(ACC_in or B)if (op == `ADD)ACC_out = ACC_in + B;

else if (op == `SUB)ACC_out = ACC_in - B;

else if …

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1

0

a

bq

s

ACC_in

BACC_out

op

Sequential always• Flip flop

always @(posedge Clock)Q = Data;

• Latch

always @(Enable or Data)if (enable)Q = Data;

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Data

Clock

Q Data

Enable

Q

Blocking and Non-blocking Assignments

• AssignmentLHS_expr1 = RHS_expr2;LHS_expr3 <= RHS_expr4;

• When the assignment is evaluated– Blocking assignment updates LHS

by RHS– Non-blocking assignment

evaluates RHS and schedules to LHS. The LHS is updated by the scheduled value, when execution waits for an event

integer x, y, z;always @(posedge clock)beginx <= x + 1;y = x + 1;z <= x + y;

end

If x was 5 before clock comes, at clock edge the always will be executed and values of

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Blocking and Non-blocking Assignments

• AssignmentLHS_expr1 = RHS_expr2;LHS_expr3 <= RHS_expr4;

• When the assignment is evaluated– Blocking assignment updates LHS

by RHS– Non-blocking assignment

evaluates RHS and schedules to LHS. The LHS is updated by the scheduled value, when execution waits for an event

integer x, y, z;always @(posedge clock)beginx <= x + 1;y = x + 1;z <= x + y;

end

If x was 5 before clock comes, at clock edge the always will be executed and values of

– x will be 5 + 1 = 6– y will be 5 + 1 = 6– z will be 5 + 6 = 11

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Blocking and Non-blocking Assignments continued

• Swap logicalways @(posedge clock)beginx <= y;y <= x;

end

• If always block has no other timing wait except the sensitivity list, you can consider that scheduled non-blocking assignment happens at the end of always block

• Design guidelines– Separate combinational and

sequential blocks, so that later only represents flip flops

– For combinational block, use only blocking assignments

– For sequential block, use only non-blocking assignments

– Do not mix them. If you mix, you might find:

• Unexplainable behavior• Simulation output varies with

simulation tool

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Representation of vector or bus• Bus or vectors are represented as

reg [3:0] data4;output [0:7] q;

• Bus is just collection of a number of signals with same name but different indices

• One can perform following vector operations

– Bit wise operation– Bit select– Part select– Concatenation

• Bitwise operationreg [3:0] data;assign is_all_zero = & data;

• Bit select// Multiplexerassign q = data[i];

• Part select// Address latch enableaddress[15:8] = address_high;if (ale) address[7:0] = data;

• Concatenation // Bit reversalreg [3:0] data;data = { data[0], data[1],

data[2], data[3] };

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Representation of 4-valued logic• Verilog introduces two more values except

normal 0 and 1– 0: Low value e.g. 1’b1– 1: High value e.g. 4’b1111– x: Unknown– z: Tristate or undriven

• Note, in w’Tv, say 16’h8CD2– w represents width in bits– T represents type – d, b, o, h– v represents value – 0-9, A-F, x, z

• Tristate bufferq = enable ? data : 1’bz;

• Tristate buffers are mainly used for modeling bidirectional / inout portsinput read;inout [7:0] data;wire data_in; reg data_out;assign data = read ?

data_out : 8’bzzzz_zzzz;assign data_in = data;

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data

enable

q

data_out

read

data

data_in

Memory

Design of bus interface units• Consider that the slave becomes

ready after 4 clocks from master asserts valid

• So slave bus interface logic has– ready driving unit– Data transfer unit

• ready driving logic– Assert ready signal at 4 clocks after

valid assertion– De-asserted when valid is de-

asserted– Note, valid here means clocked

value of valid at slave• Data transfer logic

– Data is transferred when both validand ready are asserted

– Note, clocked value of valid and ready are checked at slave. Also note, clocked value of ready means, one clock after driving ready

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‘ready‘ driving logic

Data transfer

logicdata

clock

validready

Slave Bus

Interface Logic

Slave implementation• ready driving logicmodule ready_logic(clock, valid, ready);input clock, valid;output ready;reg ready;reg [4:0] count;always @(posedge clock)

if (valid)begin

if (count < 4)count <= count + 1;

elseready <= 1’b1;

endelsebegin

count <= 0;ready <= 1’b0;

endendmodule

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Data transfer logicmodule data_transfer_logic(clock, valid,

ready, data);input clock, valid, ready;input [7:0] data;always @(posedge clock)if (valid && ready)

// some serialization logic$display(“Slave: %0d: Data Tranferred: %h\n”, $time, data);

endmodule

Assignment: Write Slave Bus Interface Unit module Master Bus Interface Unit as testbench

verilog for design - indian statistical instituteansuman/vlsitv/verilogintro.pdf · • cadence...

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