verilog basics 3 assingments
DESCRIPTION
Digital System Design - Verilog by Dr. Bassam Jamil Hashemite UniversityTRANSCRIPT
Digital System Design
Verilog:Assignments
Dr. Bassam Jamil
22
Topics
Blocks (Named, always, initial )
Continuous Assignment
Procedural Assignment
Blocking
Non-blocking
Event blocking (wait, @, #)
3
Block Types
4
5
Assignment Types: Overview
6
Modeling
7
Modeling Examples
8
Continuous Assignment Statement
9
Concurrent (Continuous) Assign Statement
10
11
12
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2-1 Mux Using Continuous Assignment
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4-1 Mux Using Continuous Assignment
15
3-1 Mux Using Continuous Assignment
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8-bit MULT Using Continuous Assignment
17
Procedural Blocking Assignment
18
Event Control
19
Event Control
# delay
delay execution for specific amount of time
@ ( signal )
Delay the execution until a logic transition on the signal
@ ( posedge signal) or @ (negedge signal)
Delay the execution until the specified transition on the signal
wait ( expression)
Delay execution until the expression evaluates True
20
Blocking Assignment Example
wait for a to change: 0 to 1
posedge a
21
Another Blocking Assignment Example
22
Non-Blocking Assignment
Non-blocking assignment evaluates at the end of the time step.
23
Blocking vs. Non-blocking (1)
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Blocking vs. Non-blocking (2)
25
Blocking vs. Non-blocking (3)
26
Delays and (Blocking vs. Non-blocking)
27
28
Chain of 3 Registers Using Non-Blocking
29
Same Chain Using Structural
30
Implicit Event Expression List
31
Implicit Event Expression List
32
Implicit Event Expression List