vcc: function-architecture co-design: modelling and examples ee 249: november 7, 2002

CADENCE CONFIDENTIAL

VCC: Function-Architecture Co-Design: Modelling and ExamplesEE 249: November 7, 2002

Grant MartinFellow, Cadence Berkeley LabsWith thanks to Frank Schirrmeister, Jean-Yves Brunel and Paolo Giusto

Agenda

• System-level SoC Design – The Rise in Abstraction

• The VCC Design Flow as an example of Function-Architecture Co-Design

• Performance Modeling

• Architectural Services

• Co-Design Example: Automotive Distributed SW

• Co-Design Example: Design Space Exploration of Multimedia platform

ImplementationTimed,Clocked,RTL Level

RefinementDesign Export

SpecificationUntimed,Unclocked,C/C++ Level

Embedded System on Chip (SoC) Design

Testbench

Satellite

Macro-Cell Micro-Cell

Zone 2: UrbanZone 1: In-Building

Pico-Cell

Zone 4: Global

Zone 3: Suburban

SystemEnvironment

Implem

entation

CharacterizationFirmware

CORE

Software

SOC

µP/CAnalog

EmbeddedSoftware

Memory

Embedded Systems Design

Requirements Specification

How did we use abstraction in the past?Step 1 – Layout to Transistor

Digital Abstraction

• Switching delay of the transistor

• Interconnect delay between transistors

1970’s

• The design complexity exceeds what designers can comprehend and think through at the layout level

• Transistor level simulation allows to verify the logic of digital and analog designs based on transistor switching characteristics

abst

ract

Transistor ModelCapacity Load

1970’s

cluster

How did we use abstraction in the past?Step 2 – Transistors to Gates

abst

ract


1970’s

cluster

abst

ract

Gate Level ModelCapacity Load

1980’s

1980’s The design complexity exceeds what

designers can comprehend and simulate at the transistor level

Gate level simulation allows to verify the logic of digital designs based on gate switching characteristics.

cluster

Digital Abstraction

Gate delay

Interconnect delay between gates

How did we use abstraction in the past?Step 3 – Gates to RTL-HDL

RTL

cluster

abst

ract

1990’s

Digital Abstraction

Not really a abstraction of performance (e.g. SDF only used for gate to layout to gate)

Textual statements result in “many gates” after synthesis

abst

ract

Gate Level ModelCapacity Load

1980’s

1990’s The design complexity exceeds what

designers can comprehend and simulate at the gate level alone

HDL is first used for fast verification, synthesis allows translation of text into gates

Synthesis algorithms map text to actual registers and logic in between based on characterized gate and wire-load libraries

Gate and wire-load delays are refined after layout. SDF emerges as format

And what is the next step?

abst

ract


cluster

abst

ract

SDFGate Level Model

Capacity Load

RTL

cluster

abst

ract

1970’s 1980’s 1990’s Year 2000 +

MPE

G

Vide

o De

code

r

I/F

DMACPorts

Timers

MPEGAudio Decoder

GraphicsEngine

DRAM

Ctrl

Bu

s/Ca

che

Cont

rol

Register File

uC

On-Chip Ram

D-Ca

che

I-Cac

he

RTLClusterscluster

abst

ract

IP Block Performance

Modeling of Performance for IP Blocks

… by attaching performance data to timing free functional models


abst

ract


cluster

abst

ract

SDFGate Level Model

Capacity Load

RTL

cluster

abst

ract

1970’s 1980’s 1990’s Year 2000 +

RTLClusterscluster

abst

ract

Inter IP Communication Performance

Modeling of Performance for Communication between IP Blocks


abst

ract


cluster

abst

ract

SDFGate Level Model

Capacity Load

RTL

cluster

abst

ract

1970’s 1980’s 1990’s Year 2000 +

MPE

G

Vide

o De

code

r

I/F

DMACPorts

Timers

MPEGAudio Decoder

GraphicsEngine

DRAM

Ctrl

Bu

s/Ca

che

Cont

rol

Register File

uC

On-Chip Ram

D-Ca

che

I-Cac

he

RTLClusterscluster

abst

ract

IP Block PerformanceInter IP Communication Performance

SWModels

Driver

RTOS

Tasks

Discontinuity:Embedded Software

Apply this to Hardware and Software

The Platform-Based Design ConceptTaking Design Block Reuse to the Next Level

Rapid Prototype forEnd-Customer Evaluation

SoC Derivative DesignMethodologies

System-level performanceevaluation environment

ApplicationSpace

Methodology / Flows:

Foundation Block

MEM

FPGACPU Processor(s), RTOS(es)

and SW architecture

*IP can be hardware (digital or analogue) or software. IP can be hard, soft or‘firm’ (HW), source orobject (SW)

*IP can be hardware (digital or analogue) or software. IP can be hard, soft or‘firm’ (HW), source orobject (SW)

Scaleablebus, test, power, IO,clock, timing architectures

+ Reference Design

Programmable

SW IP

Hardware IP

Pre-Qualified/VerifiedFoundation-IP*

Foundry-SpecificPre-Qualification

Foundry Targetting Flow

The Platform-Based Design ConceptPlatform Type Examples

“Full ApplicationHW/SW Platform”

“ProcessorCentric”

“Communication Centric”

Examples:–TI OMAP–Philips nExperia, –Infineon MGold

Examples:– ARM Micropack– ST100 Platform– Improv Jazz

Examples:–Palmchip–Sonics

Improv JAZZ Platform

SiliconBackplane™

(patented) {DSP MPEGCPUDMA

C MEM I O

SONICs Architecture

System House Requirements… exploring and developing on top of SoC Platforms

Platform Based Design Objectives

• Define the application instance to be implemented to satisfy product requirements defined by consumer

• Specify the system platform together with suppliers accordingly

• Evaluate top down different instances of SOC platforms

Architectural Space

System Platform

Application Space

PlatformSpecification

PlatformDesign SpaceExploration

SOC Provider Requirements… designing SoC Platforms and Sub-systems

Platform Based Design Objectives

• Define the SOC platform instance so that multiple instances of applications can be mapped to the same system platform

• Present this to system customers as SOC Design-Kit and optimally leverage economy of scale for SOC platform instance

• Provide bottom up instances of SOC platform for evaluation without disclosing the details of the IP

Architectural Space

System Platform

Application Space

PlatformSpecification

PlatformDesign SpaceExploration


The VCC Design Flow:An example of Function-Architecture Co-Design

VCC Front End

• Enabling communication within the SOC Design Chain

• Design Space Exploration with abstracted Performance Models

• Untimed Functional and Performance Verification

• Integration Platform Design, Optimization and Configuration

Functional IP

C/C++SDLSPW

SimulinkPerformance Analysis and

Platform Configuration

System Integration

Platform Function Platform Architecture

Embedded System Requirements


… at theun-clocked, timing-aware

system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW

VCC Front EndFunctional Integration and Analysis

Functional IP

C/C++SDLSPW



System Integration





system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW

VCC Front EndDefine Architectural Options and Configuration

Functional IP

C/C++SDLSPW



System Integration





system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW

VCC Front EndDefine Function Architecture Mapping

Functional IP

C/C++SDLSPW



System Integration





system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW

VCC Front EndRun Performance Analysis for Platform Configuration

Functional IP

C/C++SDLSPW



System Integration





system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW

Cache Results Processor Load Process Gant Chart Analysis

VCC Backend

• Linking System Level Design to Implementation

– Fast track to prototyping

– Fast track to software development

– Design consistency through the design flow

Design Export… after initial platform configuration through design refinement and

communication synthesis

Synthesis / Place & Route etc.

Implementation Level Verification

SoftwareAssembly

HardwareAssembly

CommunicationRefinement, Integration & Synthesis

VCC BackendCommunication Refinement and Synthesis





SoftwareAssembly

HardwareAssembly


AbstractToken

AbstractToken

CommunicationRefinement

CPU

VCC ModelVCC Model to RTOS Protocol Component

CPU to Bus Protocol Component

Bus

Bus Slave to VCC Model Component

Bus ModelBus

VCC Model

Bus to Bus Slave Component

Bus Slave

RTOSRTOS to CPU

Protocol Component

CommunicationSynthesis

VCC BackendExport to Implementation (Design and Test Bench)





SoftwareAssembly

HardwareAssembly


Flow To Implementation

HardwareTop-level

SystemTest Bench

Softwareon RTOS

VCCSystem Exploration

Communication Refinement

VCC Flow Summary



Functional IP

C/C++SDLSPW

Simulink



SoftwareAssembly

HardwareAssembly


Performance Analysis and Platform Configuration

System Integration





system level

Architecture IP

CPU/DSPRTOS

Bus, MemoryHWSW


Performance Modeling… using Abstraction

Functional SimulationGate Level

Functional Simulation

• Gate switching defines functionality

• Combination of gate functionality defines “functionality” of the design

• Simulation slow in complex systems as huge amounts of events are to be processed

A B OUT0 0 10 1 01 0 01 1 0

Function

C++ C

Simulink

SDL

SPW

StateCharts

Functional SimulationUsing VCC at the System-Level


• Function of system blocks executed

– General Descriptions

– C, C++, State Charts, OMI

– Application specific

– SPW, Telelogic SDL, Matlab Simulink, ETAS Ascet

• Functional execution defined as “fire and return” with a OMI 4.0 compliant discrete event simulation infrastructure

• Simulation is as fast as the abstract, un-timed models simulate

A B OUT0 0 10 1 01 0 01 1 0

Function

Abstraction

Performance SimulationGate Level


• Gate switching functionality

Performance Simulation

• functionality annotated with intrinsic gate delay

• interconnect delay modeled from capacity

Refinement

• SDF data is refined after layout is carried out

Inter-ConnectCapacity

Performance

A B OUT0 0 10 1 01 0 01 1 0

Function

t

Performance

SDF andGate Level

Library

VCC Performance SimulationSystem-Level Block Performance Modeling


• functionality annotated with intrinsic delay models

• Delay Script and Inline Models, refined after implementation

A B OUT0 0 10 1 01 0 01 1 0

Function

t

Performance

Abstraction

Annotated IP Functional Model

FEC() {f = x.read();// FEC function part A here __DelayCycles(60*cps);// FEC function part B here __DelayCycles(78*cps);// FEC function part C here __DelayCycles(23*cps);y.write(r);}

IP Functional Model Forward Error Correction

FEC() {f = x.read();// FEC function herey.write(r);}

FEC on CPU

// FEC_ip_implemdelay() {input(x);run();delay(200*cps);output(y);}

FEC in slow HW


FEC in fast HW

Delay Script// FEC_ip_implemdelay() {input(x);run();delay(64*cps);output(y);}



ScriptedDelayModel

InlineDelayModel

t

Performance

Interleaver

VCC Performance SimulationSystem Level Block Interconnect Performance Modeling


Performance

A B OUT0 0 10 1 01 0 01 1 0

Function

Abstraction

Shared MemoryCommunication PatternSender Receiver

Post() from Behavior 1Value()/Enable() from Behavior 2

Pattern Services

Standard CLibrary

RTOS

Architecture Services

MemoryAccess

CPU

RAMPort

Bus Adapter

Bus Arbiter

SlaveAdapter

CPUPort

Bus Adapter

ASICPort

Bus

Memory

RAM

VCC Performance SimulationEnabled through Architecture Services in VCC

SemProt_Send

A B

CPU Mem

RTOS

mutex_lock;memcpy;

signal

Post(5)

write

busRequest

arbiterRequest/Release

busIndication

setEnabled

Value()

wait;memcpy;

signal

read

SemaphoreProtected

busRequest

arbiterRequest/Release

busIndication

User Visible SwMutexes

BusMaster SlaveAdapter

BusArbiter

MemoryAccess Architecture Services

SemProt_Send SemProt_Recv

Pattern Services

VCC Performance Modeling …… the System Level extension of SDF

IP BlockInterconnectPerformance

C++ C

Simulink

SDL

SPWStateCharts

IP BlockPerformance

PerformanceSystem

Level Library

VCC System Level Technology

t

Interleaver

FunctionC, C++,

SPW, SDL,Simulink,

Statecharts


InterconnectPerformance

A B OUT0 0 10 1 01 0 01 1 0

Function

t

Performance

Classical Gate Level Technology

SDF andGate Level

Library

How to get the performance numbers…IP Block Performance Modeling

Top Down Flow

• In a pure top down design flow the performance models are “Design Requirements” for functional models

• They are refined using bottom up techniques in due course throughout the project

Bottom Up Flow

• SOC Provider characterizes IP portfolio, e.g. of a Integration platform

– using HDL model simulation

– using software simulation on ISS

– using benchmarking on SOC

Annotated IP Functional Model

FEC() {f = x.read();// FEC function part A here __DelayCycles(60*cps);// FEC function part B here __DelayCycles(78*cps);// FEC function part C here __DelayCycles(23*cps);y.write(r);}



FEC on CPU


FEC in slow HW


FEC in fast HW

Delay Script// FEC_ip_implemdelay() {input(x);run();delay(64*cps);output(y);}



ScriptedDelayModel

InlineDelayModel

How to get the performance numbers… IP Block Interconnect Performance Modeling

Top Down Flow

• Datasheets for architectural IP information are entered in parameters for architectural services

• Can be done fast by System Integrator without SOC Provider

• Refinement with SOC Provider models

Bottom Up Flows

• Architectural IP is profiled using HDL simulation, ISS or silicon and data is entered in VCC architectural services

MemoryAccess

CPU

Memory

RAM

RAMPort

Bus Adapter

Bus Arbiter

SlaveAdapter

CPUPort

Bus Adapter

ASICPort

Bus

Shared MemoryCommunication PatternSender Receiver

Post() from Behavior 1Value()/Enable() from Behavior 2

Standard CLibrary

RTOS

Pattern Services

Architecture Services

How to get the performance numbers…Software Estimation for ANSI C code (“Whitebox C”)

• Estimation of software performance prior to implementation

• CPU characterized as Virtual Processor Model

– Using a Virtual Machine Instruction Set

– Used for dynamic control SW estimation during performance simulation taking into account bus loading, memory fetching, and register allocation

• Value

– True co-design: SW estimation using annotation into C Code (as opposed to to simulation in instruction simulators used in co-verification)

– Good for early system scheduling, processor load estimation

– Two orders of magnitude faster than ISS

– Greater than 80 percent accuracy

– Enables pre-implementation decision but is not a verification model

How to get the performance numbers…Virtual Processor Model Characterization Methods

Data Book Approach

– CPU data book information to count cycles and estimate VIM

Calibration Suite using “Best Fit”

– Run Calibration Suite on VIM and ISS

– Solve a set of linear equations to minimize difference

Application Specific Calibration Suite

– using the “Best Fit” method but use application specific routines for automotive, wireless telecom, multimedia etc.

Exact Count on ISS

– cycle counts exactly derived from ISS run

– Filter specific commands out (e.g. OPi etc.)


Virtual MachineInstruction Set Model

LD,3.0 Load from Data MemoryLI,1.0 Load from Instr. Mem.ST,3.0 Store to Data MemoryOP.c,3.0 Simple ALU OperationOP.s,3.0OP.i,4.0OP.l,4.0OP.f,4.0OP.d,6.0MUL.c,9.0 Complex ALU OperationMUL.s,10.0MUL.i,18.0MUL.l,22.0MUL.f,45.0MUL.d,55.0DIV.c,19.0DIV.s,110.0DIV.i,118.0DIV.l,122.0DIV.f,145.0DIV.d,155.0IF,5.0 Test and BranchGOTO,2.0 Unconditional BranchSUB,19.0 Branch to SubroutineRET,21.0 Return from Subroutine


char *event;int proc;if (*(event+proc) & 0x1: 0x0)... ld

ld op ld li op ts -- br

tmp=b+cc=f(d)MT update 1

1

y=a*c+bMT update 2+3write B y

3

f6(y)MT update 4return

4

r=(s<<*a)a=r+m*x 2

tmp !tmp

ŒWhitebox Cdeclare ports

ANSI CInput

ld #event,R1 ld #proc,R2 add R1,R2,R3 ld (R3),R4 ldi #0x1, R5 and R4, R5, R6 cmp R0, R6, R7 br R7, LTRUE ba LFALSE

Assembler

VirtualProcessor

Model Analyse

basic blockscompute delays

PerformanceEstimation

ArchitectureCharacterization

ŽGenerate new C

with delay counts

Compile

generated C andrun natively


Architectural Services Example

Architecture Service

• The service is the element that defines the functionality of an architecture

• A service is coded in C++ and performs a specific role to model architecture, for example:

– bus arbitration

– memory access

– interrupt propagation

– etc.

Example of Services

Behavior PatternSender

BusMaster BusArbiter

BusSlave

ASIC Bus

Mem

Memory

Post

Example of Services

• Behavior calls Post, i.e., send a communication

• Pattern hears Post and directs ASIC block’s BusMaster to send a communication

• BusMaster asks the Bus Block’s BusArbiter for use of the bus

• BusArbiter grants the bus, so communication can go to Memory Block

• Memory Block’s BusSlave receives communication and forwards to memory

• Memory stores communication.

Categories of Services

• Pattern Service

– services that coordinate the communication of architecture services

• Architecture Service

– services that define the functionality of architecture

• Internal Service

– generic, default service used during functional simulation

• A pattern coordinates architectural services that collectively model a communication path from sender to receiver

• Patterns are composed of a sender service and a receiver service

– Sender service defines Post

– Receiver service defines Enabled/Value

• Both the sender and receiver service direct the actions of architecture services to send/receive communication

Pattern Service

PatternSender

Post

PatternReceiver

Enabled/Value

Basic Example

• Let’s assume two behaviors.

• b1 and b2 talk to each other:

– b1 says Post; b2 says Value

– and visa versa

Basic Example (cont)

• What does it mean for b1 to talk to b2?

• What does it mean for b1 to say Post?

• What does it mean for b2 to say Value?

• We should consider an architecture to give meaning to b1 and b2.

• We should consider how the behavior blocks map to the architecture.


• Let’s assume the following architecture:


• Here we map the behavior to the architecture:


• What do we see in the mapping diagram?

– b1 is mapped to software.

– b2 is mapped to hardware.

– b1 to b2 communication is set to Shared Memory.

– b2 to b1 communication is set to to Interrupt Register Mapped.

• For simplicity’s sake, we’re focusing on b1-to-b2 communication.

– b2 to b1 will be ignored for now.

• If b1 talks to b2, how does that look when mapped to an architecture?

– What happens when b1 says Post?

– What happens when b2 says Value?

– Note b1 to b2 is shared memory communication.


• Using Shared Memory, we have the following sequence of communication:

1. b1 writes to memory:

b1 RTOS CPU Bus Mem

2. b2 reads from memory:

b2 ASIC Bus Mem


• So b1 talks to b2 through the various architecture components:

– b1 says Post and that becomes a write to memory.

– b2 says Value and that becomes a read from memory.

• What is the underlying mechanism that propagates Post/Value through the architecture?

– It’s something called the “service”.

Commercial ExampleST Microelectronics

IP models support codesign effortsBy Benoit Clement

System-Level Design Engineer

Doha BenjellounSystem-Level Design Engineer

Co-Design Methodology for Systems &Architecture (CMSA)

STMicroelectronics, Grenoble, France

http://www.eetimes.com/story/OEG20010913S0069


Example of Co-Design – Distributed Automotive SW

Distributed Automotive Applications over networks – “Software-Software Codesign”

• Electronic Control Units (ECU’s)

• Standard buses (TTP, CAN, FlexRay)

• Standard Platforms

analysisanalysis“functional network”

system designsystem design“real world assumption”

implementationimplementation“automatic target code gen.”

production & after salesproduction & after sales“handling at the garage”

specificationspecification“zero time assumption”

integration & calibrationintegration & calibration“step into a real car”

Current Design Practices

ECU-1ECU-1 ECU-2ECU-2

ECU-3ECU-3CAN/TTP-busCAN/TTP-bus

MatlabMatlab

ASCETASCET

.c .c .c ....c .c .c ... ArchitectureArchitecture

RequirementsRequirements

f1f1 f2f2

f3f3 f4f4

Engine Control

Gear-Box Control

Deve

lopm

ent p

roce

ss

• Integration is done too late In the car

• Tools are PER-ECU – conservative, costly, no tradeoffs

Virtual Integration Platform for Distributed Automotive Applications

BusesBusesMatlab

CPUs Buses OperatingSystems

SpecificationASCET

Analysis

After Sales Service

Calibration

ImplementationASCET

Software Components Architectural Models C-Code

IP’s

C++

Dev

elo

pm

ent

Pro

cess

Evaluation ofArchitectural and Partitioning Alternatives

VCCVCC

System Behavior System Architecture

Mapping


Refinement

f2f2f1f1f3f3

Scenarios for SW-driven co-development

ff??

f f

f

fff ff ff??

f f

f

ff

fff

ff??

f f

f

ff

ProjectA

HWIntrpt1

HWIntrpt2

Message1Message2Message3Message4

These are behavioral memories

The test-bench can include Matlab imported modelsas well as VCC authored models

This is the ASCET imported Project

TestBench

HW_Intrpt1

HW_Intrpt2

Module0

SW_Interrupt1

HW_Interrupt1

SW_Interrupt2

Module1SW_InterruptHW_Interrupt

Module2

SW_Interrupt1

SW_Interrupt2

HWIntrpt1

HWIntrpt2

Timer10msec

Timer20ms

Timer30ms

These are behavioral timers

These are the processesfor the protected

variables

These are the modulesof the ASCET project

GlobalVariable

GlobalVariable2

These are behavioralmemories

HWIntrpt

ReceiveSendTask1

HWIntrpt

ReceiveSendTas

SWIntrpt

ReceiveSendTask3

SWIntrpt

ReceiveSendTask4

ReceiveSendTask5

ReceiveSendTask6

ReceiveSendTask7

Module0

SW_Interrupt1

HW_Interrupt1

SW_Interrupt2

Module1SW_InterruptHW_Interrupt

Module2

SW_Interrupt1

SW_Interrupt2

HWIntrpt1

HWIntrpt2

Timer10msec

Timer20ms

Timer30ms

These are behavioral timers

These are the processesfor the protected

variables

These are the modulesof the ASCET project

GlobalVariable

GlobalVariable2

These are behavioralmemories

HWIntrpt

ReceiveSendTask1

HWIntrpt

ReceiveSendTas

SWIntrpt

ReceiveSendTask3

SWIntrpt

ReceiveSendTask4

ReceiveSendTask5

ReceiveSendTask6

ReceiveSendTask7

SW_Interrupt

HW_Interrupt

Process8

Process9

Process10

HWIntrp

Interrupt

IntrptReceiveTask1

Interrupt

IntrptSendTask1

ASCET-SD imported project in VCC

Broadcast Bus

PPCRTOS

BusController

ECU 1

internal bus

Behavioral Diagram

Module A

Behavioral Memory 1

Module B

Peak Load

PPCRTOS

BusController

ECU 1

internal bus

MemMemArchitecturalBus Memory

Universal Communications Model of Bus

Example Design Flow (1): Power Window

• Definition of a behavioral diagram: Import of functional components (software projects and modules)

UniformPulses

UniformPulses

UniformPulses

SpeedRL

SteeringWheelTorque1

TieRodForce2

SteeringWheelAngle2

VoltageBatterie1

SpeedFL

ClampForceRL


CurrentBatterie1

SteeringWheelAngle4

SpeedRR

YawRate

CurrentBatterie2

VoltageAlternator

ClampForceFR

TieRodForce1

BrakeSwitch

PedalSensor1

LateralAcceleration

VoltageBatterie2

SpeedFR

PedalSensor3

SteeringWheelAngle3

TieRodForce3

SteeringWheelAngle1

PedalSensor2

CurrentAlternator

ClampForceRR

ClampForceFL


HandBrakeSwitch

RackPosition3

RackPosition4

RackPosition2

RackPosition1

Trigger

BordnetStimulator

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger

HandWheelTorqueActuator


WarningLightYellow

WarningLightYellow

WarningLightRed

WarningLightRed

2 TrackVehicleModel

Trigger

DriverSteer

DriverBrake

DriverGas

DriverClutch

DriverGear

SteeringActuator1

SteeringActuator2

BrakeActuatorRR

BrakeActuatorRL

BrakeActuatorFL

BrakeActuatorFR

UniformPulses

Driver

DriverSteer

Trigger

DriverBrake

DriverGas

DriverClutch

DriverGear

DbW_TopBlock

BTSetUp

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

ComputePowerManagement

Manipulator



Manipulator

Manipulator

Manipulator

Manipulator

Manipulator

Diagnosis

Manipulator

Manipulator

Master1SteeringAngleOut

TieRodForce1Fil

Master1BrakeFR

VoltageBatterie1Fil

SpeedRLFil

RackPosition4Fil

SteeringWheelTorque2Fil

Master1SteeringTorqueOut

SpeedFRFil

vel_veh_master_1

SteeringWheelAngle4Fil

PedalSensor2Fil

Master1Warning

ClampForceRLFil

LateralAccelerationFil

YawRateFil

BrakeSwitchFil


CurrentAlternatorFil

RackPosition2Fil

AlternatorDiagnosis

Timer

PedalSensor3Fil

TieRodForce2Fil


RackPosition3Fil

PedalSensor1Fil

Battery2Diagnosis

ClampForceRRFil

Master1BrakeRL

CurrentBatterie2Fil


ClampForceFLFil


SpeedFLFil

VoltageBatterie2Fil


Battery1Diagnosis

Master1BrakeFL

VoltageAlternatorFil

SpeedRRFil

Master1BrakeRR

ClampForceFRFil

CurrentBatterie1Fil

HandBrakeSwitchFil

RackPosition1Fil

TieRodForce3Fil

Base Brake & ABS

Base Steering

HandwheelFeedback

BrakeOutFL

BrakeOutRR

BrakeOutFR

BrakeOutRL

SteeringWheelTorqueOut2


SteeringOut2

SteeringOut1

Master2Warning

Master2BrakeFR

Master2BrakeRR


Master2BrakeRL

Master2BrakeFL


vel_veh_master_2

Master Controller

BrakeDiagnosis

SteeringDiagnosis

HWFeedbackDiagnosis

Diagnosis

Master Controller

Design Flow (2)• Generation of an ideal communication between the functional components

– No delay or error handling considered.

– Functional co-verification

Design Flow (3)

TTP Channel 2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

PPC_TTP Channel1

Channel2

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

TTPController

Channel2

Channel1

PPCRTOS

• Creation of an architectural diagram in VCC

Design Flow (4)• Mapping the software modules onto the ECU

– Either retaining the original per-ecu mapping from ASCET-SD or creating a new one

UniformPulses

UniformPulses

UniformPulses

SpeedRL


TieRodForce2

SteeringWheelAngle2

VoltageBatterie1

SpeedFL

ClampForceRL


CurrentBatterie1

SteeringWheelAngle4

SpeedRR

YawRate

CurrentBatterie2

VoltageAlternator

ClampForceFR

TieRodForce1

BrakeSwitch

PedalSensor1

LateralAcceleration

VoltageBatterie2

SpeedFR

PedalSensor3

SteeringWheelAngle3

TieRodForce3

SteeringWheelAngle1

PedalSensor2

CurrentAlternator

ClampForceRR

ClampForceFL


HandBrakeSwitch

RackPosition3

RackPosition4

RackPosition2

RackPosition1

Trigger

BordnetStimulator

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger



WarningLightYellow

WarningLightYellow

WarningLightRed

WarningLightRed

2 TrackVehicleModel

Trigger

DriverSteer

DriverBrake

DriverGas

DriverClutch

DriverGear

SteeringActuator1

SteeringActuator2

BrakeActuatorRR

BrakeActuatorRL

BrakeActuatorFL

BrakeActuatorFR

UniformPulses

Driver

DriverSteer

Trigger

DriverBrake

DriverGas

DriverClutch

DriverGear

DbW_TopBlock

BTSetUp

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal


Manipulator



Manipulator

Manipulator

Manipulator

Manipulator

Manipulator

Diagnosis

Manipulator

Manipulator


TieRodForce1Fil

Master1BrakeFR

VoltageBatterie1Fil

SpeedRLFil

RackPosition4Fil



SpeedFRFil

vel_veh_master_1


PedalSensor2Fil

Master1Warning

ClampForceRLFil


YawRateFil

BrakeSwitchFil



RackPosition2Fil

AlternatorDiagnosis

Timer

PedalSensor3Fil

TieRodForce2Fil


RackPosition3Fil

PedalSensor1Fil

Battery2Diagnosis

ClampForceRRFil

Master1BrakeRL

CurrentBatterie2Fil


ClampForceFLFil


SpeedFLFil

VoltageBatterie2Fil


Battery1Diagnosis

Master1BrakeFL


SpeedRRFil

Master1BrakeRR

ClampForceFRFil

CurrentBatterie1Fil

HandBrakeSwitchFil

RackPosition1Fil

TieRodForce3Fil

Base Brake & ABS

Base Steering

HandwheelFeedback

BrakeOutFL

BrakeOutRR

BrakeOutFR

BrakeOutRL



SteeringOut2

SteeringOut1

Master2Warning

Master2BrakeFR

Master2BrakeRR


Master2BrakeRL

Master2BrakeFL


vel_veh_master_2

Master Controller

BrakeDiagnosis

SteeringDiagnosis

HWFeedbackDiagnosis

Diagnosis

Master Controller

Base Brake & ABS onechannel

BTSetUp

BrakeOutRL_channel4

BrakeOutRR_channel2

BrakeOutFR_channel3

BrakeOutFL_channel4

BrakeOutRL_channel3

BrakeOutRR_channel3

BrakeOutFR_channel4

Timer

BrakeOutFR_channel1

BrakeOutRR_channel1

BrakeOutFL_channel2

BrakeOutRR_channel4

BrakeOutFR_channel2

BrakeOutFL_channel1

BrakeOutFL_channel3

BrakeOutRL_channel2

BrakeOutRL_channel1




Vote Brake Comand

Vote Brake Comand

Vote Brake Comand

Vote Brake Comand

SteeringActuatorOut_channel1




Vote_Cmp_Rack_Act

BTSetUpTimer

Vote_Cmp_Rack_Act

Base Steering onechannel




SteeringWheelTorqueOut_channel2


SteeringWheelTorqueOut_channel1HandwheelFeedback one

channel

BTSetUpTimer

Vote HW Feedback

HandwheelFeedback one

channel


channel

Vote HW Feedback

DiagnosisBrakePedal

ComputeBrakeCommand

force_clp_fl_ABS_des

force_clp_rl_ABS_des

force_clp_r_base_des

force_clp_f_base_des

long_acc_veh_des

force_clp_fr_ABS_des

force_clp_rr_ABS_des

Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

ComputeSteeringCommand

Diagnosis_Lateral_Sensors

BTSetUp

VotedRackPosition

Timer

VotedSteeringWheelAngle



BTSetUp

VotedRackPosition

Timer


Diagnosis Feedback Sensors

ComputeSteeringTorqueCommand

BTSetUpTimer

VotedTieRodForce

VotedSteeringWheelTorque



BTSetUpTimer

VotedTieRodForce




BTSetUp

VotedRackPosition

Timer




BTSetUp

VotedRackPosition

Timer


ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FCFSB

u

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort



BTSetUpTimer

VotedTieRodForce


DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

Design Flow(5)

Hierarchical Scheduler

SingleTaskScheduler

SingleTaskScheduler

SingleTaskScheduler

ParentScheduler

• Generation of the CPU scheduling

– Either manually or automatically in case the original scheduling is preserved

Design Flow (6)• Computation Performance Simulation

– No communication performance estimation

– Co-verification of Computational Resource ‘fit’

Design Flow(7)• Design iterations

– Re-distribution of the functionality and tuning of the scheduling

Channel1

Channel1

Channel2

l

hannel2

C

hannel2

hannel1

hannel1

Channel2

lll

TTP Channel 2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

PPC_TTPChannel1

Channel2

TTPController

Channel2

PPCRTOS

TTPController

Channel2

PPCRTOS

TTPController

Channe1

PPCRTOS

TTPController

CChannel1

PPCRTOS

TTPController

Channel1

PPCRTOS

TTPController

Channel2

C

PPCRTOS

TTPController

Channel2

C

PPCRTOS

TTPController

Channel1

PPCRTOS

TTPController

Channe2

Channel1

PPCRTOS

TTPController

Channel2

Channe1

PPCRTOS

TTPController

Channel2

Channe1

PPCRTOS

Channel2

UniformPulses

UniformPulses

UniformPulses

SpeedRL


TieRodForce2

SteeringWheelAngle2

VoltageBatterie1

SpeedFL

ClampForceRL


CurrentBatterie1

SteeringWheelAngle4

SpeedRR

YawRate

CurrentBatterie2

VoltageAlternator

ClampForceFR

TieRodForce1

BrakeSwitch

PedalSensor1

LateralAcceleration

VoltageBatterie2

SpeedFR

PedalSensor3

SteeringWheelAngle3

TieRodForce3

SteeringWheelAngle1

PedalSensor2

CurrentAlternator

ClampForceRR

ClampForceFL


HandBrakeSwitch

RackPosition3

RackPosition4

RackPosition2

RackPosition1

T r ig g e r

BordnetStimulator

BrakeActuator

Br a k e A c tu a to r O u t

T r ig g e r

BrakeActuator


T r ig g e r

BrakeActuator


T r ig g e r

BrakeActuator


T r ig g e r

SteerActuator

S te e r A c tu a to r O u t

T r ig g e r

SteerActuator

S te e r A c tu a to r O u t

T r ig g e r

H a n d W h e e lT o r q u e A c tu a to r

H a n d W h e e lT o r q u e A c tu a to r

W a r n in g L ig h tY e llo w

W a r n in g L ig h tY e llo w

W a r n in g L ig h tR e d

W a r n in g L ig h tR e d

2 TrackVehicleModel

T r ig g e r

D r iv e r S te e r

D r iv e r Br a k e

D r iv e r G a s

D r iv e r C lu tc h

D r iv e r G e a r

S te e r in g A c tu a to r 1

S te e r in g A c tu a to r 2

Br a k e A c tu a to r R R

Br a k e A c tu a to r R L

Br a k e A c tu a to r F L

Br a k e A c tu a to r F R

UniformPulses

Driver

D r iv e r S te e r

T r ig g e r

D r iv e r Br a k e

D r iv e r G a s

D r iv e r C lu tc h

D r iv e r G e a r

DbW_TopBlock

BTSetUp

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

C o m p u te P o w e r M a n a g e m e n t

M a n ip u la to r



M a n ip u la to r

M a n ip u la to r

M a n ip u la to r

M a n ip u la to r

M a n ip u la to r

Diagnosis

M a n ip u la to r

M a n ip u la to r

M a s te r 1 S te e r in g A n g le O u t

TieRodForce1Fil

M a s te r 1 Br a k e F R

VoltageBatterie1Fil

SpeedRLFil

RackPosition4Fil


M a s te r 1 S te e r in g T o r q u e O u t

SpeedFRFil

v e l_ v e h _ m a s te r _ 1


PedalSensor2Fil

M a s te r 1 W a r n in g

ClampForceRLFil


YawRateFil

BrakeSwitchFil



RackPosition2Fil

A lte r n a to r D ia g n o s is

T im e r

PedalSensor3Fil

TieRodForce2Fil


RackPosition3Fil

PedalSensor1Fil

Ba t te r y 2 D ia g n o s is

ClampForceRRFil

M a s te r 1 Br a k e R L

CurrentBatterie2Fil


ClampForceFLFil


SpeedFLFil

VoltageBatterie2Fil


Ba t te r y 1 D ia g n o s is

M a s te r 1 Br a k e F L


SpeedRRFil

M a s te r 1 Br a k e R R

ClampForceFRFil

CurrentBatterie1Fil

HandBrakeSwitchFil

RackPosition1Fil

TieRodForce3Fil

Base Brake & ABS

Base Steering

HandwheelFeedback

Br a k e O u tF L

Br a k e O u tR R

Br a k e O u tF R

Br a k e O u tR L

S te e r in g W h e e lT o r q u e O u t2

S te e r in g W h e e lT o r q u e O u t1

S te e r in g O u t2

S te e r in g O u t1

M a s te r 2 W a r n in g

M a s te r 2 Br a k e F R

M a s te r 2 Br a k e R R

M a s te r 2 S te e r in g T o r q u e O u t

M a s te r 2 Br a k e R L

M a s te r 2 Br a k e F L

M a s te r 2 S te e r in g A n g le O u t

v e l_ v e h _ m a s te r _ 2

Master Controller

Br a k e D ia g n o s is

S te e r in g D ia g n o s is

H W F e e d b a c k D ia g n o s is

Diagnosis

Master Controller


BTSetUp

Br a k e O u tR L _ c h a n n e l4

Br a k e O u tR R _ c h a n n e l2

Br a k e O u tF R _ c h a n n e l3

Br a k e O u tF L _ c h a n n e l4




T im e r













V o te Br a k e C o m a n d




S te e r in g A c tu a to r O u t_ c h a n n e l1




V o te _ C m p _ R a c k _ A c t

BTSetUpT im e r

V o te _ C m p _ R a c k _ A c t





S te e r in g W h e e lT o r q u e O u t_ c h a n n e l2

S te e r in g W h e e lT o r q u e O u t_ c h a n n e l3

S te e r in g W h e e lT o r q u e O u t_ c h a n n e l1HandwheelFeedback one

channel

BTSetUpT im e r

V o te H W F e e d b a c k


channel


channel

V o te H W F e e d b a c k

DiagnosisBrakePedal

ComputeBrakeCommand

f o r c e _ c lp _ f l_ A BS _ d e s

f o r c e _ c lp _ r l_ A BS _ d e s

f o r c e _ c lp _ r _ b a s e _ d e s

f o r c e _ c lp _ f _ b a s e _ d e s

lo n g _ a c c _ v e h _ d e s

f o r c e _ c lp _ f r _ A BS _ d e s

f o r c e _ c lp _ r r _ A BS _ d e s

C o m p _ C m d _ A BS _ Br

A r b ite r _ Br

BTSetUpT im e r

DiagnosisBrakePedal

ComputeBrakeCommand









A r b ite r _ Br

BTSetUpT im e r

DiagnosisBrakePedal

ComputeBrakeCommand









A r b ite r _ Br

BTSetUpT im e r

C o m p u te S te e r in g C o m m a n d


BTSetUp

VotedRackPosition

T im e r




BTSetUp

VotedRackPosition

T im e r



C o m p u te S te e r in g T o r q u e C o m m a n d

BTSetUpT im e r

VotedTieRodForce




BTSetUpT im e r

VotedTieRodForce




BTSetUp

VotedRackPosition

T im e r




BTSetUp

VotedRackPosition

T im e r


E C U _ 2 T a s k s _ 1 Bu s C h a

E x te r n a lBu s P o r t







E C U _ 2 T a s k s _ 1 Bu s C h a n














C P U

I n te r r u p tBu s

D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC


I n te r n a lD a ta Bu s

E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s


C P U


D a ta Bu s

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBusFCFSBu

S im ple

A S IC



E x te r n a lBu s




BTSetUpT im e r

VotedTieRodForce


DiagnosisBrakePedal

ComputeBrakeCommand









A r b ite r _ Br

BTSetUpT im e r

UniformPulses

UniformPulses

UniformPulses

SpeedRL


TieRodForce2

SteeringWheelAngle2

VoltageBatterie1

SpeedFL

ClampForceRL


CurrentBatterie1

SteeringWheelAngle4

SpeedRR

YawRate

CurrentBatterie2

VoltageAlternator

ClampForceFR

TieRodForce1

BrakeSwitch

PedalSensor1

LateralAcceleration

VoltageBatterie2

SpeedFR

PedalSensor3

SteeringWheelAngle3

TieRodForce3

SteeringWheelAngle1

PedalSensor2

CurrentAlternator

ClampForceRR

ClampForceFL


HandBrakeSwitch

RackPosition3

RackPosition4

RackPosition2

RackPosition1

Trigger

BordnetStimulator

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

BrakeActuator

BrakeActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger

SteerActuator

SteerActuatorOut

Trigger



WarningLightYellow

WarningLightYellow

WarningLightRed

WarningLightRed

2 TrackVehicleModel

Trigger

DriverSteer

DriverBrake

DriverGas

DriverClutch

DriverGear

SteeringActuator1

SteeringActuator2

BrakeActuatorRR

BrakeActuatorRL

BrakeActuatorFL

BrakeActuatorFR

UniformPulses

Driver

DriverSteer

Trigger

DriverBrake

DriverGas

DriverClutch

DriverGear

DbW_TopBlock

BTSetUp

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal

AquireSignal


Manipulator



Manipulator

Manipulator

Manipulator

Manipulator

Manipulator

Diagnosis

Manipulator

Manipulator


TieRodForce1Fil

Master1BrakeFR

VoltageBatterie1Fil

SpeedRLFil

RackPosition4Fil



SpeedFRFil

vel_veh_master_1


PedalSensor2Fil

Master1Warning

ClampForceRLFil


YawRateFil

BrakeSwitchFil



RackPosition2Fil

AlternatorDiagnosis

Timer

PedalSensor3Fil

TieRodForce2Fil


RackPosition3Fil

PedalSensor1Fil

Battery2Diagnosis

ClampForceRRFil

Master1BrakeRL

CurrentBatterie2Fil


ClampForceFLFil


SpeedFLFil

VoltageBatterie2Fil


Battery1Diagnosis

Master1BrakeFL


SpeedRRFil

Master1BrakeRR

ClampForceFRFil

CurrentBatterie1Fil

HandBrakeSwitchFil

RackPosition1Fil

TieRodForce3Fil

Base Brake & ABS

Base Steering

HandwheelFeedback

BrakeOutFL

BrakeOutRR

BrakeOutFR

BrakeOutRL



SteeringOut2

SteeringOut1

Master2Warning

Master2BrakeFR

Master2BrakeRR


Master2BrakeRL

Master2BrakeFL


vel_veh_master_2

Master Controller

BrakeDiagnosis

SteeringDiagnosis

HWFeedbackDiagnosis

Diagnosis

Master Controller


BTSetUp

BrakeOutRL_channel4

BrakeOutRR_channel2

BrakeOutFR_channel3

BrakeOutFL_channel4

BrakeOutRL_channel3

BrakeOutRR_channel3

BrakeOutFR_channel4

Timer

BrakeOutFR_channel1

BrakeOutRR_channel1

BrakeOutFL_channel2

BrakeOutRR_channel4

BrakeOutFR_channel2

BrakeOutFL_channel1

BrakeOutFL_channel3

BrakeOutRL_channel2

BrakeOutRL_channel1




Vote Brake Comand

Vote Brake Comand

Vote Brake Comand

Vote Brake Comand





Vote_Cmp_Rack_Act

BTSetUpTimer

Vote_Cmp_Rack_Act







SteeringWheelTorqueOut_channel1HandwheelFeedback one

channel

BTSetUpTimer

Vote HW Feedback


channel


channel

Vote HW Feedback

DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer



BTSetUp

VotedRackPosition

Timer




BTSetUp

VotedRackPosition

Timer




BTSetUpTimer

VotedTieRodForce




BTSetUpTimer

VotedTieRodForce




BTSetUp

VotedRackPosition

Timer




BTSetUp

VotedRackPosition

Timer


ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusCha

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

ECU_2Tasks_1BusChan

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort

CPU

InterruptBus

DataBus

StaticPriority

Scheduler

CycloStatic

Scheduler

CycloStatic

Scheduler

InterruptBus

FC

FS

Bu

SimpleASIC

InterruptBus

InternalDataBus

ExternalBus

ExternalBusPort



BTSetUpTimer

VotedTieRodForce


DiagnosisBrakePedal

ComputeBrakeCommand





long_acc_veh_des



Comp_Cmd_ABS_Br

Arbiter_Br

BTSetUpTimer

Design Flow(8)• Initialization of the UCM performance model.

– Automated generation of an initial communication matrix that carries the dependency of the functional system mapping.

• Definition of a specific bus protocol implementation

– UCM parameterization. Definition of the communication cycle layout. Data frame definition.

Bus TypePattern

Design Flow (9)

• Performance simulation including the bus latencies

• Full System co-verification: both communications and computation

Design Iterations

Bus TypePattern


Example of Co-Design: Design Space Exploration of Multimedia Platform

vccMapDatabase

Design DataExported from VCC diagrams using “VCCAPI”

vccDseDatabase

Design Space Navigator (SQL queries)

vccSimDatabase

Performance DataCollected by VCC probes under control of system events

Data Analysis Workbooks for specific roles(Excel+StatBox)

Process AnalystApplication Analyst Communication AnalystClassification

es

cosy_init

finfoSinfo

Yo_Info

Yo_Data

Uo_Info

Uo_Data

Vo_Info

Vo_Data

Tvld_bits_In

Tvld_cmd_In

Tvld_prop_seq_In

Tvld_prop_pic_In

Tvld_prop_slice_In

Thdr

_stat

us_O

ut

mb_QFS_Out

Tisiq_prop_seq_Out

Tisiq_prop_mb_Out

TdecMV_prop_pred_Out

TdecMV_prop_mv_Out

cosy_init

Tvld

Thdr_status_In

Tvld_cmd_Out

Tvld_prop_seq_Out

Tvld_prop_pic_Out

Tvld_prop_slice_Out

Tisiq_prop_pic_Out

TwriteMB_prop_pic_Out

TdecMV_prop_seq_Out

TdecMV_prop_pic_Out

Tpredict_prop_pic_Out

cosy_init

Thdr

TdecMV_prop_mv_In

TdecMV_prop_pred_In

Tdec

MV_

prop

_seq

_In

Tdec

MV_

prop

_pic_

In

Tpredict_mv_Out

Tpredict_prop_pred_Out

Tpredict_prop_seq_Out

cosy

_init

TdecMV

Tpredict_prop_pred_In

Tpredict_mv_In

Tpredict_prop_seq_In

Tpredict_prop_pic_In

Tpred

ict_r

ef_me

m_id_

In

Tmemory_mb_p_In

Tpredict_token_Out

Tadd_mb_p_Out

cosy

_init

Tpredict

mb_QFS_In

Tisiq_prop_seq_In

Tisiq_prop_pic_In

Tisiq_prop_mb_In

mb_F_Out

Tidct_prop_seq_Out

Tidct_prop_mb_Out

cosy_init

Tisiq

mb_F_In

Tidct_prop_seq_In

Tidct_prop_mb_In

mb_f_Out

Tadd_prop_seq_Out

Tadd_prop_mb_Out

cosy

_init

Tidct

mb_f_In

mb_p_In

Tadd_prop_seq_In

Tadd_prop_mb_In

mb_d_Out

TwriteMB_prop_seq_Out

TwriteMB_prop_mb_Out

cosy

_init

Tadd

mb_d_In

TwriteMB_prop_seq_In

TwriteMB_prop_pic_In

TwriteMB_prop_mb_In TwriteMB_mem_id_In

Tmemory_ack_In

TmemMan_prop_seq_Out

TmemMan_cmd_Out

Tmem

ory_

mb_to

ken_

Out

TmemMan_prop_pic_Out

cosy_init

TwriteMB

TmemMan_cmd_In

TmemMan_rdy_mem_id_In

TmemMan_prop_seq_In

TwriteMB_pic_In

TwriteMB_mem_id_Out

Tpred

ict_r

ef_me

m_id_

Out

Toutput_cmd_Out

Toutput_prop_seq_Out

Tmem

ory_

prop

_seq

_Out

Toutput_pic_Out

Tmem

ory_

stat_r

dy_O

ut

cosy_init

TmemMan

TmemMan_prop_seq_In

Tmem

Man

_stat

_rdy

_In

Tpredict_token_In

Twrit

eMB_

token

_In

Toutput_line_address_In

Tadd_mb_p_Out TwriteMB_ack_Out

Toutput_line_data_Out

cosy_init

Tmemory

Toutput_prop_seq_In

Toutput_cmd_In

Tmemory_line_data_In

TmemMan_pic_In

TmemMan_rdy_mem_id_Out

Y_Info

Y_Data

U_Info

U_Data

V_Info

V_Data

Sinfo

finfo

Tmemory_line_address_Out

cosy_init

Toutput

Created by COSY (c) May 2001

YHS1

YSH1YSH1YSH1YSH1

YHS1VHH1

YSS1YHH1YSH1YHS1

YHH1YSH1YSS1

YHHPYHHPYSH1YHH1

YHHPYHHPYHH1YHH1

YHH1YHHPYSH1YHHP

YHHPYHH1YHHPYHHP

YSH1

YSH1

YSH1

YHH1

YSH1

YHS1

YHSP

YHSP

YHSPYHH1

YHHP

YSH1YSH1YSH1

YSH1YSH1

EJTAGFPBC_MPIC

M_bridge

MPBC_GLOBAL

BOOT_DBG

SMCARD

IIC1_2

UART1_3

CLOCKS

USB

IEEE1394

SPDIO

AIO1_3

SSI

TPBC

f_pi_bus

m_pi_bus

t_pi_bus

C_Bridge

PR3940

VIP1_2

ICP1_2

MBS

MSP1_2

PCI

DE

FPIMI

TPIC

GPIO

VMPG

MMIMemory

pSOSRTOS TM_3218

VMPG_AUX

FR_MEM

Multimedia Applications – Design Space Exploration

Export Mapping Data to DataBase

es

cosy_init

finfoSinfo

Yo_Info

Yo_Data

Uo_Info

Uo_Data

Vo_Info

Vo_Data

Tvld_bits_In

Tvld_cm

d_In

Tvld_prop_seq_In

Tvld_prop_pic_In

Tvld_prop_slice_In

Thd

r_st

atus

_Out

mb_Q

FS_Out

Tisiq_prop_seq_O

ut

Tisiq_prop_m

b_Out


TdecMV_prop_mv_Out

cosy_init

Tvld

Thdr_status_In

Tvld_cm

d_Out

Tvld_prop_seq_O

ut

Tvld_prop_pic_O

ut

Tvld_prop_slice_O

ut

Tisiq_prop_pic_O

ut

Tw

riteMB

_prop_pic_Out

TdecM

V_prop_seq_O

ut

TdecM

V_prop_pic_O

ut

Tpredict_prop_pic_O

ut

cosy_init

Thdr

TdecMV_prop_mv_In

TdecMV_prop_pred_In

Tde

cMV

_pro

p_se

q_In

Tde

cMV

_pro

p_pi

c_In

Tpredict_mv_Out



cosy

_ini

t

TdecMV


Tpredict_mv_In



Tpr

edic

t_re

f_m

em_i

d_In

Tmemory_mb_p_In

Tpredict_token_Out

Tadd_m

b_p_Outco

sy_i

nit

Tpredict

mb_QFS_In

Tisiq_prop_seq_In

Tisiq_prop_pic_In

Tisiq_prop_mb_In

mb_F_Out

Tidct_prop_seq_Out

Tidct_prop_mb_Out

cosy_init

Tisiq

mb_F_In

Tidct_prop_seq_In

Tidct_prop_mb_In

mb_f_Out

Tadd_prop_seq_Out

Tadd_prop_mb_Out

cosy

_ini

t

Tidct

mb_f_In

mb_p_In

Tadd_prop_seq_In

Tadd_prop_mb_In

mb_d_Out



cosy

_ini

t

Tadd

mb_d_In




Tm

emory_ack_In


TmemMan_cmd_Out

Tm

emor

y_m

b_to

ken_

Out


cosy_init

TwriteMB

TmemMan_cmd_In

Tm

emM

an_rdy_mem

_id_In

TmemMan_prop_seq_In

TwriteMB_pic_In

TwriteMB_mem_id_Out

Tpr

edic

t_re

f_m

em_i

d_O

ut

Toutput_cmd_Out


Tm

emor

y_pr

op_s

eq_O

ut

Toutput_pic_Out

Tm

emor

y_st

at_r

dy_O

ut

cosy_init

TmemMan

Tm

emM

an_prop_seq_In

Tm

emM

an_s

tat_

rdy_

In

Tpredict_token_In

Tw

rite

MB

_tok

en_I

n


Tadd_mb_p_Out Tw

riteMB

_ack_Out


cosy_init

Tmemory

Toutput_prop_seq_In

Toutput_cmd_In


TmemMan_pic_In

Tm

emM

an_rdy_mem

_id_Out

Y_Info

Y_Data

U_Info

U_Data

V_Info

V_Data

Sinfo

finfo


cosy_init

Toutput

Created by COSY (c) May 2001

EJTAGFPBC_MPIC

M_bridge

MPBC_GLOBAL

BOOT_DBG

SMCARD

IIC1_2

UART1_3

CLOCKS

USB

IEEE1394

SPDIO

AIO1_3

SSI

TPBC

f_pi_bus

m_pi_bus

t_pi_bus

C_Bridge

PR3940

VIP1_2

ICP1_2

MBS

MSP1_2

PCI

DE

FPIMI

TPIC

GPIO

VMPG

MMIMemory

pSOSRTOS TM_3218

VMPG_AUX

FR_MEM

YHS1

YSH1YSH1YSH1YSH1

YHS1VHH1

YSS1YHH1YSH1YHS1

YHH1YSH1YSS1

YHHPYHHPYSH1YHH1

YHHPYHHPYHH1YHH1

YHH1YHHPYSH1YHHP

YHHPYHH1YHHPYHHP

YSH1

YSH1

YSH1

YHH1

YSH1

YHS1

YHSP

YHSP

YHSP

YHH1

YHHP

YSH1 YSH1 YSH1

YSH1 YSH1

YSH1

YSH1

YSH1

YSH1

YSH1

YSH1

YSH1

YSH1

out

cosy_init

TBINFILE_unsigned_char

in

cosy_init

TDROP_field_info

CA_Info

CA_Data

CB_Info

CB_Data

CC_Info

CC_Data

sinfob

cosy_init

TBE

es

finfo

Sinfo

Yo_Info

Yo_Data

Uo_Info

Uo_Data

Vo_Info

Vo_Datacosy_init

SMPEGDecode

cosy_init

beh_MPEG_Processes

Created by COSY (c) June 2001

EJTAGFPBC_MPIC

M_bridge

MPBC_GLOBAL

BOOT_DBG

SMCARD

IIC1_2

UART1_3

CLOCKS

USB

IEEE1394

SPDIO

AIO1_3

SSI

TPBC

f_pi_bus

m_pi_bus

t_pi_bus

C_Bridge

PR3940

VIP1_2

ICP1_2

MBS

MSP1_2

PCI

DE

FPIMI

TPIC

GPIO

VMPG

MMIMemory

pSOSRTOS TM_3218

VMPG_AUX

FR_MEM

System-Observation-Windows

Frame Port Name Transaction Item Actual IntraID Nb Nb Delay Delay1 Tvld_bits_In 324 20,736 0.14 0.021 Tvld_cmd_In 208 208 0.13 0.001 Tvld_prop_pic_In 1 1 0.00 0.001 Tvld_prop_slice_In 36 36 0.00 0.001 mb_QFS_Out 1,622 622,704 6.66 0.651 Thdr_status_Out 208 208 0.01 0.011 Tisiq_prop_mb_Out 1,622 1,622 0.03 0.031 TdecMV_prop_mv_Out 1,622 1,622 0.04 0.04… … … …. … ….2 Tvld_bits_In 525 33,600 0.23 0.032 Tvld_cmd_In 206 206 0.12 0.002 Tvld_prop_pic_In 1 1 0.00 0.002 Tvld_prop_slice_In 36 36 0.00 0.002 mb_QFS_Out 1,619 621,696 6.53 0.652 Thdr_status_Out 206 206 0.01 0.012 Tisiq_prop_mb_Out 1,619 1,619 0.03 0.032 TdecMV_prop_mv_Out 1,619 1,619 0.04 0.042 TdecMV_prop_pred_Out 1,619 1,619 0.09 0.09… … … … … …

Frame Requestor Delay DelayID Mean StDev1 Behavior/in_es_out_sender 5.64E-06 3.00E-061 Behavior/decode/t_vld_Tvld_bits_In_receiver 2.91E-06 1.20E-061 Behavior/decode/t_hdr_Tvld_cmd_Out_sender 2.40E-07 1.17E-141 Behavior/decode/t_vld_Tvld_cmd_In_receiver 2.40E-07 1.17E-141 Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender 2.16E-06 0.00E+001 Behavior/decode/t_vld_Tvld_prop_pic_In_receiver 2.16E-06 0.00E+001 Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender 7.20E-07 1.22E-14… …. … …2 Behavior/in_es_out_sender 5.64E-06 3.00E-062 Behavior/decode/t_vld_Tvld_bits_In_receiver 2.91E-06 1.20E-062 Behavior/decode/t_hdr_Tvld_cmd_Out_sender 2.40E-07 1.17E-142 Behavior/decode/t_vld_Tvld_cmd_In_receiver 2.40E-07 1.17E-142 Behavior/decode/t_hdr_Tvld_prop_pic_Out_sender 2.16E-06 0.00E+002 Behavior/decode/t_vld_Tvld_prop_pic_In_receiver 2.16E-06 0.00E+002 Behavior/decode/t_hdr_Tvld_prop_slice_Out_sender 7.20E-07 1.22E-142 Behavior/decode/t_vld_Tvld_prop_slice_In_receiver 7.20E-07 1.22E-14… … … …

es

cosy_init

finfo

Sinfo

Yo_Info

Yo_Data

Uo_Info

Uo_Data

Vo_Info

Vo_Data

Tvld_bits_In

Tvld_cm

d_In

Tvld_prop_seq_In

Tvld_prop_pic_In

Tvld_prop_slice_In

Thd

r_st

atus

_Out

mb_Q

FS

_Out

Tisiq_prop_seq_O

ut

Tisiq_prop_m

b_Out


TdecMV_prop_mv_Out

cosy_init

Tvld

Thdr_status_In

Tvld_cm

d_Out

Tvld_prop_seq_O

ut

Tvld_prop_pic_O

ut

Tvld_prop_slice_O

ut

Tisiq_prop_pic_O

ut

Tw

riteMB

_prop_pic_Out

TdecM

V_prop_seq_O

ut

TdecM

V_prop_pic_O

ut

Tpredict_prop_pic_O

ut

cosy_init

Thdr

TdecMV_prop_mv_In

TdecMV_prop_pred_In

Tde

cMV

_pro

p_se

q_In

Tde

cMV

_pro

p_pi

c_In

Tpredict_mv_Out



cosy

_ini

t

TdecMV


Tpredict_mv_In



Tpr

edic

t_re

f_m

em_i

d_In

Tmemory_mb_p_In

Tpredict_token_Out

Tadd_m

b_p_Outco

sy_i

nit

Tpredict

mb_QFS_In

Tisiq_prop_seq_In

Tisiq_prop_pic_In

Tisiq_prop_mb_In

mb_F_Out

Tidct_prop_seq_Out

Tidct_prop_mb_Out

cosy_init

Tisiq

mb_F_In

Tidct_prop_seq_In

Tidct_prop_mb_In

mb_f_Out

Tadd_prop_seq_Out

Tadd_prop_mb_Out

cosy

_ini

t

Tidct

mb_f_In

mb_p_In

Tadd_prop_seq_In

Tadd_prop_mb_In

mb_d_Out



cosy

_ini

t

Tadd

mb_d_In




Tm

emory_ack_In


TmemMan_cmd_Out

Tm

emor

y_m

b_to

ken_

Out


cosy_init

TwriteMB

TmemMan_cmd_In

Tm

emM

an_rdy_mem

_id_In

TmemMan_prop_seq_In

TwriteMB_pic_In

TwriteMB_mem_id_Out

Tpr

edic

t_re

f_m

em_i

d_O

ut

Toutput_cmd_Out


Tm

emor

y_pr

op_s

eq_O

ut

Toutput_pic_Out

Tm

emor

y_st

at_r

dy_O

ut

cosy_init

TmemMan

Tm

emM

an_prop_seq_In

Tm

emM

an_s

tat_

rdy_

In

Tpredict_token_In

Tw

rite

MB

_tok

en_I

n


Tadd_mb_p_Out Tw

riteMB

_ack_Out


cosy_init

Tmemory

Toutput_prop_seq_In

Toutput_cmd_In


TmemMan_pic_In

Tm

emM

an_rdy_mem

_id_Out

Y_Info

Y_Data

U_Info

U_Data

V_Info

V_Data

Sinfo

finfo


cosy_init

Toutput

EJTAGFPBC_MPIC

M_bridge

MPBC_GLOBAL

BOOT_DBG

SMCARD

IIC1_2

UART1_3

CLOCKS

USB

IEEE1394

SPDIO

AIO1_3

SSI

TPBC

f_pi_bus

m_pi_bus

t_pi_bus

C_Bridge

PR3940

VIP1_2

ICP1_2

MBS

MSP1_2

PCI

DE

FPIMI

TPIC

GPIO

VMPG

MMIMemory

pSOSRTOS TM_3218

VMPG_AUX

FR_MEM

Pict 1 Pict 2

For, e.g. Each MPEG Frame Measure…

e.g. MEMORY usagee.g. process activity

“Probe-Synch” & Observer Probes

Probe-Synch is triggered on conditions in a behavioral block (i.e. MPEG frame decoded)

Control up to 200 distributed observer probes of different types: i.e Memory probes, Bus probes, CPU “Delay” probes etc…

Observer Probes record summary data at the granularity defined by the peekerBUS

OBSERVERPROBE

CPUOBSERVER

PROBE

MEMORY OBSERVER PROBE

Calculate Average Actual & Intrinsic Communication Rates of all “YAPI” application level Channels


Queries 1: link Map & Simulation data

SELECT simComAppYapi.sessionCounter AS frameID…, simComAppYapi.actualDelay,… FROM mapComAppYapi INNER JOIN fctProc ON mapComAppYapi.srcProcID = fctProc.ID… WHERE simComAppYapi.VccInstanceName)=[fctProc].[diagName] & "/" & [fctProc].[procName];

chanID frameID nbTransaction nbItem nbByte actualDelay intrinsicDelay

2 3 5,76E+02 5,76E+02 6,91E+03 6,06E-04 6,06E-04

2 10 5,10E+01 5,10E+01 6,12E+02 4,56E-05 4,56E-05

16 18 1,62E+03 1,62E+03 4,54E+04 7,26E-02 3,54E-05

Key to retrieve Design “Mapping” Decision

Simulation resultsSimulation “Frame” Context



Queries 2: calculate basic Statistics

SELECT DISTINCTROW Avg([nbByte]/[actualDelay]) AS AvgOfActualRate, StDev([nbByte]/[actualDelay]) AS StDevOfActualRate,… Avg([nbByte]/[intraDelay]) AS AvgOfIntraRate, … INTO staComAppYapiRate_perChan FROM mkStaComAppYapiRate_perChan_step1 GROUP BY chanID…;

comAppClas

s

transaction

chanID

portID AvgOfActualRate StDevOfActualR

ate

MinOfActualR

ate

MaxOfActualRat

e

AvgOfIntraRate StDevOfIntraRat

e YAPI Rd 2 14 5,61E+06 5,98E+0

4 5,55E+

06 5,77E+0

6 6,09E+06 5,86E+0

4 YAPI Wr 2 48 7,34E+06 1,58E+0

6 6,47E+

06 1,21E+0

7 1,13E+07 4,90E+0

5 YAPI Rd 3 15 6,27E+07 6,27E+

07 6,27E+0

7 6,67E+07

YAPI Rd 4 11 5,62E+08 1,61E+07

5,39E+08

6,00E+08

6,47E+08 1,59E+07

YAPI Wr 4 46 5,80E+08 4,86E+07

5,49E+08

7,20E+08

5,89E+08 4,82E+07

YAPI Wr 7 44 7,29E+06 7,15E+06

5,10E+06

3,15E+07

7,57E+06 7,86E+06

YAPI Rd 9 13 9,73E+06 2,17E+05

9,33E+06

1,01E+07

1,09E+07 3,34E+05

YAPI Wr 9 45 1,45E+07 2,68E+06

1,30E+07

2,24E+07

1,90E+07 1,36E+06

YAPI Rd 10 16 5,68E+08 1,70E+07

5,30E+08

5,99E+08

6,27E+08 1,38E+07

YAPI Wr 10 50 4,48E+08 8,08E+07

4,02E+08

6,82E+08

4,52E+08 8,17E+07

YAPI Rd 11 17 6,89E+08 1,19E+07

6,68E+08

7,13E+08

7,19E+08 7,93E+06

YAPI Wr 11 51 7,54E+08 2,24E+06

7,48E+08

7,58E+08

7,58E+08 2,19E+06

YAPI Rd 12 12 9,48E+04 1,49E+04

3,36E+04

1,11E+05

1,05E+07 1,71E+05

YAPI Wr 12 52 2,92E+07 4,02E+07

4,63E+06

1,65E+08

3,55E+07 4,71E+07

YAPI Rd 14 65 3,07E+08 1,04E+08

1,20E+07

3,43E+08

4,00E+08 6,58E+00

YAPI Wr 14 118 4,91E+06 0,00E+00

4,91E+06

4,91E+06

4,92E+06 1,26E-01

YAPI Wr 16 67 5,19E+07 2,29E+08

4,23E+05

1,21E+09

1,19E+09 1,49E+08

YAPI Rd 16 76 1,14E+09 4,03E+08

9,29E+05

1,28E+09

1,28E+09 3,23E+01

YAPI Rd 17 66 1,32E+08 3,37E+08

1,21E+07

1,18E+09

1,59E+09 4,56E+01

YAPI Wr 17 77 1,39E+09 4,81E+08

2,65E+07

1,59E+09

1,56E+09 3,92E+07

YAPI Wr 18 120 1,80E+07 0,00E+00

1,80E+07

1,80E+07

1,80E+07 7,13E-01

YAPI Rd 18 130 4,11E+08 2,77E+08

1,17E+08

7,08E+08

7,26E+08 2,46E+01

YAPI Wr 19 27 1,85E+06 3,02E+05

1,66E+06

3,30E+06

6,69E+06 1,26E-01

YAPI Rd 19 100 6,35E+06 3,64E+05

6,15E+06

7,91E+06

6,64E+06 2,79E+05

YAPI Wr 22 63 4,58E+08 2,31E+07

4,44E+08

5,17E+08

5,21E+08 1,35E+05

YAPI Wr 23 86 7,22E+05 1,90E+04

6,94E+05

7,65E+05

7,22E+05 1,90E+04

YAPI Rd 23 116 1,26E+04 2,45E+03

1,10E+04

2,03E+04

9,87E+05 3,40E-02

YAPI Rd 25 94 1,60E+08 4,03E+00

1,60E+08

1,60E+08

2,00E+08 0,00E+00

YAPI Wr 25 106 1,90E+06 5,75E-02 1,90E+06

1,90E+06

1,90E+06 5,14E-02

YAPI Rd 26 69 2,62E+08 2,98E+06

2,58E+08

2,76E+08

1,59E+09 4,56E+01

YAPI Wr 26 129 1,58E+09 4,85E+06

1,57E+09

1,59E+09

1,58E+09 4,85E+06

YAPI Wr 27 59 1,24E+09 1,86E+01

1,24E+09

1,24E+09

1,24E+09 1,86E+01

map_FAKIR_Diagrams.MPEG_VIPER_SH2Frame Processing - Actual Delay (sec)

28P27B26B25P24B23B22I21B20B19P18B17B16P15B14B13P12B11B10I9B8B7P6B5B4P3B2B1I

26P25B24P23P22B21I20I19B18P17P16B15P14P13B12P11P10B9I8I7B6P5P4B3P2P1B

29B28P27B26B25P24B23B22I21B20B19P18B17B16P15B14B13P12B11B10I9B8B7P6B5B4P3B2B1I

0,00 0,20 0,40 0,60 0,80 1,00

tStart

proc

ID

15:t_hdr

14:t_memMan (Probe-Synch)

8:t_output

28 Frames in … 2 sec

Application Analyst

map_FAKIR_Diagrams.MPEG_VIPER_S1Breakdown of Process Execution on basic Architectural Resources of Type:

CORE, MEM & BUS - Average Actual Delay per Frame (sec)

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R2c

R25c

R27c

R27c

R30c

R30c

R30c

R30c

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R34b

R16m

R27m

R27m

R27m

R30m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

R32m

E2c

E2c

E2c

E2c

E2c

E2c

E2c

E2c

E2c

E16c

E27c

E27c

E27c

E30c

E30c

E30c

E30c

E34b

E34b

E34b

E34b

E34b

E34b

E34b

E34b

E34b

E32m

E32m

E32m

E32m

E32m

E32m

E32m

E32m

E32m

W2c

W2c

W2c

W2c

W2c

W2c

W2c

W2c

W2c

W2c

W2c

W27c

W27c

W27c

W30c

W30c

W30c

W30c

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W34b

W6m

W6m

W6m

W25m

W27m

W30m

W30m

W30m

W32m

W32m

W32m

W32m

W32m

W32m

W32m

W32m

W32m

W32m

W32m

0,00E+00 5,00E-02 1,00E-01 1,50E-01 2,00E-01 2,50E-01 3,00E-01 3,50E-01 4,00E-01

3:ofileproc

4:drop_finfo

5:in_es

6:t_decMV

7:t_memory

8:t_writeMB

9:t_add

10:t_idct

11:t_predict

12:t_vld

13:t_isiq

14:t_output

15:t_memMan

16:t_hdr

proc

AvgOfactualDelay

R2cR25cR27cR30cR34bR16mR27mR30mR32mE2cE16cE27cE30cE34bE32mW2cW27cW30cW34bW6mW25mW27mW30mW32m

Process Analyst

Body-FunctionExec DelayOn Memory “32”

IO- (Write Trans.)Execution DelayOn CPU “2”

Body-FunctionExecution DelayOn CPU “2”

IO-(Read Trans.)Exec DelayOn CPU “2”

Process“t-predict”

map_FAKIR_Diagrams.MPEG_VIPER_S1YAPI Transactions - Write - Number of bytes per channel per frame

0,00E+00

5,00E+05

1,00E+06

1,50E+06

2,00E+06

2,50E+06

3,00E+06

3,50E+06

4,00E+06

1 3 5 7 9 11 13 15 17 19 21 23 25

frameID

nbB

yte

2468910111415171820212223263032343536374041

Communication Analyst

map_FAKIR_Diagrams.MPEG_VIPER_SH2YAPI IO Rates - avg Actual versus avg Intrinsic (Byte/sec, log scale)

75Rd

71Rd70Rd

66Rd

65Rd

64Rd

62Rd

59Rd56Rd

54Rd

53Rd50Rd

48Rd

47Rd

45Rd

44Rd 43Rd

42Rd

40Rd37Rd

36Rd

33Rd

30Rd27Rd

26Rd25Rd

23Rd

19Rd

18Rd17Rd

16Rd14Rd

12Rd

11Rd10Rd

9Rd

4Rd

3Rd

2Rd

75Wr

71Wr

70Wr66Wr

65Wr

64Wr62Wr

59Wr56Wr54Wr

53Wr50Wr

48Wr

47Wr

46Wr45Wr44Wr

43Wr

42Wr

40Wr37Wr36Wr

35Wr

33Wr

30Wr27Wr26Wr

25Wr23Wr

22Wr

19Wr

18Wr

17Wr

16Wr

14Wr

12Wr

11Wr10Wr

9Wr7Wr

4Wr

2Wr

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1,00E+11

1,00E+05 1,00E+06 1,00E+07 1,00E+08 1,00E+09 1,00E+10AvgOfIntraRate

Avg

OfA

ctua

lRat

e

YAPI.RdYAPI.Wr

Communication Analyst

Very bad “performance” compared to “intrinsic rate”;Arbitration issue or… always busy waiting for input?

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis - YAPI Application Level Communication

itemSize

fifoDepth

AvgOfnbTransaction

AvgOfnbItem

AvgOfactualDelay

AvgOfPerf

-1

-0,8

-0,6

-0,4

-0,2

0

0,2

0,4

0,6

0,8

1

-1 -0,8 -0,6 -0,4 -0,2 0 0,2 0,4 0,6 0,8 1-- axe F1 (34 %) -->

-- a

xe F

2 (2

3 %

) --

>

Opposed characteristics

Linked characteristics

Principal Component Analysis Characteristics

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis -

YAPI Application Level Communication

10Rd.VHH110Wr.VHH1

11Rd.VHH111Wr.VHH1

12Rd.VHH1

12Wr.VHH114Rd.YSH114Wr.YSH1

16Rd.YHHP

16Wr.YHHP

17Rd.YHHP

17Wr.YHHP

18Rd.YSH118Wr.YSH1

19Rd.YSH1

19Wr.YSH1

22Wr.YHHP

23Rd.YHS1

23Wr.YHS125Rd.YSH125Wr.YSH1

26Rd.YHHP

26Wr.YHHP

27Rd.YHSP27Wr.YHSP2Rd.VHH1

2Wr.VHH1

30Rd.YHH1

30Wr.YHH1

33Rd.YSH133Wr.YSH1

35Wr.YHH1

36Rd.YHS1

36Wr.YHS1

37Rd.YSH137Wr.YSH1

3Rd.VHH1

40Rd.VHH1

40Wr.VHH1

42Rd.YHHP

42Wr.YHHP

43Rd.YHHP

43Wr.YHHP44Rd.YHS1

44Wr.YHS1

45Rd.YSH145Wr.YSH146Wr.YHH147Rd.YHS147Wr.YHS148Rd.YSH1

48Wr.YSH1

4Rd.VHH14Wr.VHH1

50Rd.YSH150Wr.YSH153Rd.YSH1

53Wr.YSH1

54Rd.YHH1

54Wr.YHH1

56Rd.YHH1

56Wr.YHH1

59Rd.YHH159Wr.YHH1

62Rd.YHSP

62Wr.YHSP64Rd.YSH1

64Wr.YSH1

65Rd.YHH1

65Wr.YHH1

66Rd.YSS166Wr.YSS170Rd.YSH170Wr.YSH1

71Rd.YHHP71Wr.YHHP

75Rd.YHH1

75Wr.YHH1

7Wr.YHH19Rd.VHH19Wr.VHH1

itemSize

fifoDepth

AvgOfnbTransaction

AvgOfnbItem

AvgOfactualDelay

AvgOfPerf

-0,5

-0,3

-0,1

0,1

0,3

0,5

0,7

0,9

-0,9 -0,7 -0,5 -0,3 -0,1 0,1 0,3 0,5 0,7 0,9

-- axe F1 (34 %) -->

-- a

xe F

2 (2

3 %

) --

>Principal Component Analysis Results on 108 Communication Channels

map_FAKIR_Diagrams.MPEG_VIPER_SH2 - Principal Component Analysis - YAPI Application Level Communication

10Rd.VHH110Wr.VHH1

11Rd.VHH111Wr.VHH1

12Rd.VHH1

12Wr.VHH114Rd.YSH114Wr.YSH1

16Rd.YHHP

16Wr.YHHP

17Rd.YHHP

17Wr.YHHP

18Rd.YSH118Wr.YSH1

19Rd.YSH1

19Wr.YSH1

22Wr.YHHP

23Rd.YHS1

23Wr.YHS125Rd.YSH125Wr.YSH1

26Rd.YHHP

26Wr.YHHP

27Rd.YHSP27Wr.YHSP2Rd.VHH1

2Wr.VHH1

30Rd.YHH1

30Wr.YHH1

33Rd.YSH133Wr.YSH1

35Wr.YHH1

36Rd.YHS1

36Wr.YHS1

37Rd.YSH137Wr.YSH1

3Rd.VHH1

40Rd.VHH1

40Wr.VHH1

42Rd.YHHP

42Wr.YHHP

43Rd.YHHP

43Wr.YHHP44Rd.YHS1

44Wr.YHS1

45Rd.YSH145Wr.YSH146Wr.YHH147Rd.YHS147Wr.YHS148Rd.YSH1

48Wr.YSH1

4Rd.VHH14Wr.VHH1

50Rd.YSH150Wr.YSH153Rd.YSH1

53Wr.YSH1

54Rd.YHH1

54Wr.YHH1

56Rd.YHH1

56Wr.YHH1

59Rd.YHH159Wr.YHH1

62Rd.YHSP

62Wr.YHSP64Rd.YSH1

64Wr.YSH1

65Rd.YHH1

65Wr.YHH1

66Rd.YSS166Wr.YSS170Rd.YSH170Wr.YSH1

71Rd.YHHP71Wr.YHHP

75Rd.YHH175Wr.YHH1

7Wr.YHH19Rd.VHH19Wr.VHH1

-2

-1

0

1

2

3

4

-4 -3 -2 -1 0 1 2-- axe F1 (34 %) -->

-- a

xe F

2 (2

3 %

) --

>

Class 1

Class 2

Class 3

Class 5

Class 4

Clustering into Communication Port Classes

Summary• Talked about System-level SoC Design and changes in abstractions

• Discussed the VCC Design Flow as an example of Function-Architecture Co-Design, including the key concepts of:

– Performance Modeling

– Architectural Services

• Described two usage examples of function-architecture co-design, illustrating the pragmatic use of these concepts by real design teams:

– Automotive Distributed SW

– Design Space Exploration of Multimedia platform

• As a result, I hope you are convinced of both the need for system level design for SoC, and the real possibility of creating practical tools to support it

• Next important step for such tools: a common standardised model integration infrastructure based on SystemC

vcc: function-architecture co-design: modelling and examples ee 249: november 7, 2002

Documents

design objectivesdefine

soc designkit

soc platform instanceprovide

soc platformsplatform

agendasystemlevel soc

abstractionthe vcc design

gate level alonehdl

example of function