MPSD D-Bug12 & ANSI Display Lab Exercise

Using the D-Bug12 Monitor and ANSI Display Commands

Student's name & ID (1): ___________________________________________________

Partner's name & ID (2): ___________________________________________________

Your Section number & TA's name __________________________________________

Notes:

You must work on this assignment with your partner.

Hand in a printer copy of your software listings for the team. Hand in a neat copy of your circuit schematics for the team.

These will be returned to you so that they may be used for reference.

------------------------------- do not write below this line -----------------------------

POINTS (1) (2) TA init.

Grade for performance verification (50% max.)

Grade for answers to TA's questions (20% max.)

Grade for documentation and appearance (30% max.)

TOTAL

Grader's signature: ___________________________________________

Date: ______________________________________________________

Page 2

Using the D-Bug12 Monitor Commands and Programming an ANSI Display

GOAL

By doing this lab assignment, you will learn: 1. To use the D-Bug12 monitor commands on the M68HC12. 2. Exercise the 6812 CPU registers and built-in hardware functions (ports, timers, A/D converters, etc.). 3. To use the VT100 Terminal Interface (with HyperTerminal or ProComm Plus) on the M68HC12. 4. To program an ANSI terminal display through a C program using the Introl C cross-compiler.

PREPARATION

• Read Sections 2.2 and 5.1 to 5.5 from Software and Hardware Engineering by Cady & Sibigtroth. • Read the Introl M6812 C Cross-Compiler handout. • Review the M68HC12 hardware features. • Review the C language stdio utilities. • References: 68HC12 EVB User's Manual, pp. 3-4, 3-5, 4-17, & 4-18 MC68HC812A4 Technical Summary, pp 11-16

VT100/ANSI ESCAPE SEQUENCES and Hello.c sample program

D-BUG12 COMMANDS ON THE MC6812

1. Monitor Commands

Become familiar with the commands for observing and changing the values of the CPU registers and memory, including the hardware control and status registers (the first 512 memory locations). The EVB uses the 6812's ports A through D for expanded mode access to 64k of external memory. This leaves only ports G, H, and J available for general use (see Figure 2-1 in text and attached to this exercise).

2. Tasks

Use the monitor commands and the Cady & Sibigtroth text (see examples in Chapter 5, 7, and 12) to:

• Check and change CPU12 register values.

• Set and display both memory and control register values. Use both the byte and word access commands. Note which byte address is in the most significant (high) position and which is in the least significant (low) position. Also note that the processor can writes words (2 bytes) to odd addresses.

Page 3

• Set a block of addresses to a byte value and verify that the value is there. Move the block of data to a new address range and verify again.

• Change the terminal BAUD rate. (Remember you will need to adjust your ProComm Plus or HyperTerminal settings to continue communicating with the EVB.)

• Set output port bits (use a voltmeter or a TA provided 6-LED module with series current limiting resistors to verify values). You will first need to set the corresponding bits in the port’s data direction register to a 1 for output. See the attached data sheets for port and data direction register addresses.

• Input logic levels set on ports (use 0 V (ground) for a logic low and +5 V through a 1 k resistor for a logic high). Again, for ports G, H, and J you will first need to set the data direction register bits to 0 for input.

• Read in a voltage on an analog to digital converter channel. (This may be a little confusing since the settings necessary for this aren't covered until later in the course.) The minimum steps necessary to read in a voltage on pin PAD0 (channel 0) are:

1. Power up the converter – set bit 7 in ATDCTL2 ($0062) to 1.

2. Start continuous conversion cycling – set bit 5 in ATDCTL5 ($0065) to 1.

3. Read the 8-bit numerical value in the results register ADR0H ($0070 for channel 0).

If a pot (use the pot modules assigned to lab groups by the TA) between ground and +5 V with the wiper connected to the A/D input is used to give various voltage readings, you should be able to confirm that voltages near 0 V yield small numerical values and voltages near +5 V yield values near 255. Explain why this makes sense.

• Enter and execute the assembly language program on the following page. First wire up an LED and series resistor between any bit on PORT H and ground. Use the ASM command to enter the program line by line, starting at $5000. For the last two instructions you will need to substitute the absolute address of the instruction to which the program will jump instead of the label (e.g. $500A for LOOP). Use the ASM command again to list the program to verify correctness. Set the PC to $5000 and use T to trace through the program one instruction at a time. Note what information is displayed when T is executed. After cycling through the loop a few times, change the value in the decrement counter register (IY) to 2. Continue to trace through the program until the LED lights. Execute the program with the command G 5000 and verify operation. The LED should flash with about a 1.4 Hz repetition rate. Change the immediate constant loaded into IY to increase the frequency. Find the value giving the maximum repeat rate at which your eye can still detect flashing as opposed to what appears as a steady dim light from too high a flashing frequency.

Page 4

Use the move memory command to move the program down to $4000 and the block fill command to erase the original at $5000 by setting all bytes from $5000 to $5020 to zero. Remember to change the countdown constant back to 0. Do you expect the program to run correctly in the new location? Try running it. If that doesn’t work, set the PC to $4000 and use the GT [<address>] where the address is the address of an instruction you suspect may be causing problems. D-Bug12 will stop executing the program at that point and allow you to trace through manually from there. Using BR to set breakpoints will accomplish the same objective. If problems are found, fix them so that the program runs as it did at $5000.

ledflash.asm Sep 21 10:09 19101 Page 1 1 ; LEDFLASH.ASM 2 ; Test program to flash an LED on any bit on output port H 3 ; Written in 68HC12 Assembly Language 4 ; RPK 9/21/01 5 6 ORG $5000 7 00005000 86ff START: LDAA #$FF ;A=$FF 8 00005002 5a25 STAA $0025 ;SET ALL BITS ON PORT H FOR OUTPUT (=1) 9 00005004 41 TOGGLE: COMA ;A IS COMPLEMENTED, EITHER $00 OR $FF 10 00005005 5a24 STAA $0024 ;OUTPUT A TO PORT H (ALL BITS) 11 00005007 cd0000 LDY #0000 ;LOAD THE COUNTDOWN VALUE (0->65536) 12 ;THE VALUE IS LOADED FROM THE MEMORY 13 ;LOCATION IMMEDIATELY FOLLOWING THE 14 ;INSTRUCTION. CHANGING THIS VALUE 15 ;WILL ADJUST THE FLASHING FREQUENCY 16 0000500a ce0001 LOOP: LDX #1 ;WASTE TIME (IX=D/IX) 17 0000500d 1810 IDIV ;THIS IS A LONG 12 CYCLE INSTRUCTION 18 0000500f b7c5 XGDX 19 00005011 ce0001 LDX #1 ;DO IT TWICE 20 00005014 1810 IDIV 21 00005016 b7c5 XGDX 22 00005018 03 DEY ;DECREMENT IY COUNTDOWN VALUE 23 00005019 26ef BNE LOOP ;DELAY LOOP, BRANCH IF NOT ZERO 24 0000501b 065004 JMP TOGGLE ;TOGGLE LED AND REPEAT ledflash.asm Sep 21 10:09 19101 Page 2 Section synopsis 1 0000001e ( 30) ledflash.asm Sep 21 10:09 19101 Page 3 Symbol table 1 00005000 | LOOP E 1 0000500a | START E 1 00005000 | TOGGLE E 1 00005004 ledflash.asm Sep 21 10:09 19101 Page 4 Symbol cross-reference LOOP *16 23 START *7 TOGGLE *9 24

Page 5

ANSI PROGRAMMING TASKS FOR THE MC6812

1. Introduction To The User Interface

Input from the terminal keyboard and output to the terminal display can be done using the getchar(a) and putchar(a) functions. Write a simple C program to run on the MC6812 that outputs "The keyboard character is *." whenever you type a printable character, where * stands for that character. Since you will be waiting for an indefinite number of characters to be typed, use <ESC> (or ^[ key combination, where ^ = <Control>) to end the program. Display this information at the top of the screen when the program starts.

2. VT100/ANSI Terminal Control Escape Sequences

ProComm Plus and HyperTerminal use VT100/ANSI terminal emulation by default. By sending special codes to the terminal, it is possible to clear the screen, position the cursor, set terminal colors, and many other operations. These codes are called escape sequences because the first character is the <ESC> character, or $1B in ASCII (033 octal). The table on the next to last page contains some useful escape codes. Modify the C program of Part 1 to display yellow characters on a blue background. Center the program termination information on line 2. Display the keyboard response text on line 10. Change the color of the keyed in character to white (leaving the rest of the characters in yellow). Now for nonprinting characters, have the program blink the output "The keyboard character $XX is 'not

printable'." and beep, where XX are the hexadecimal digits of the nonprintable character. This line should appear at the line in the center of the screen (e.g. line 20 if 40 lines are being displayed in the terminal window). Also, although the top message may overwrite the previous message each time a new key is hit, the ‘not printable’ message should be written on the line beneath the previous line. When it writes on the last line of the screen, the terminal should scroll just the lines on the lower half of the screen. There are escape sequences that simplify these operations, which you are expected to use as much as possible. Unfortunately, the PC card in the Sun workstations does not have an external speaker so headphones are needed to hear the beep and ProComm must be used instead of HyperTerminal. The version of HyperTerminal used on the PCs does not seem to support the beep sound. NOTE: If the terminal doesn’t respond properly to escape sequences, it may no longer be in an ANSI compatible mode. Make sure the leftmost bottom parameter button in the HyperTerminal window is set to either VT100 or ANSI BBS and likewise for ProComm Plus.

Good programmer's tip: Design the program top-down. Then write the routines bottom-up. Write them one at a time and thoroughly test each one before integrating them. This way you will have isolated any errors to the routine that you are currently writing. Good programmers follow this method.

Page 6

VT100/ANSI ESCAPE SEQUENCES

Name Escape Code Hexadecimal Description Reset Device

<ESC>c $1B $63 Resets all terminal settings to default.

Enable Line Wrap

<ESC>[7h $1B $5B $37 $68

Enables wrapping text to the next line if text is longer than the display area.

Disable Line Wrap

<ESC>[7l $1B $5B $37 $6C

Disables wrapping text; text will be clipped if longer than display area.

Cursor Home <ESC>[H $1B $5B $48 Moves the cursor to the home position (upper left hand corner).

Cursor Position

<ESC>[{ROW}; {COL}H

$1B $5B ${ROW} $3B ${COL} $48

Sets the position of the cursor at ({ROW}, {COL}).

Cursor Up <ESC>[{NUM}A $1B $5B ${NUM} $41

Moves the cursor up {NUM} rows; {NUM} defaults to 1 if omitted.

Cursor Down <ESC>[{NUM}B $1B $5B ${NUM} $42

Moves the cursor down {NUM} rows; {NUM} defaults to 1 if omitted.

Cursor Left <ESC>[{NUM}D $1B $5B ${NUM} $44

Moves the cursor left {NUM} columns; {NUM} defaults to 1 if omitted.

Cursor Right

<ESC>[{NUM}C $1B $5B ${NUM} $43

Moves the cursor right {NUM} columns; {NUM} defaults to 1 if omitted.

Save Cursor <ESC>[s $1B $5B $73 Saves the current cursor position. Restore Cursor

<ESC>[u $1B $5B $75 Restores the previously stored cursor position.

Erase End of Line

<ESC>[K $1B $5B $4B Erases from the current cursor position to the end of the current row.

Erase Start of Line

<ESC>[1K $1B $5B $31 $4B

Erases from the start of the current row to the current cursor position.

Erase Line <ESC>[2K $1B $5B $32 $4B

Erases the entire current row.

Erase Down <ESC>[J $1B $5B $4A Erases from the current row down to the bottom of the screen.

Erase Up <ESC>[1J $1B $5B $31 $4A

Erases from the current row to the top of the screen.

Erase Screen

<ESC>[2J $1B $5B $32 $4A

Erases the entire screen and moves the cursor to the home position.

Scroll All <ESC>[r $1B $5B $72 Enables scrolling for the entire display. Scroll Section

<ESC>[{SRT}; {END}r

$1B $5B ${SRT} $3B ${END} $72

Enables scrolling only for rows {SRT} to {END}.

Scroll Down <ESC>D $1B $44 Scrolls the display down one line. Scroll Up <ESC>M $1B $4D Scrolls the display up one line. Attribute Mode set

<ESC>[{ATR1}; ...;{ATRn}m

$1B $5B ${ATR1} $3B ... $3B ${ATRn} $6D

Sets multiple display attribute settings; any number can be set. ATRn may be any of the following values:

Standard Values for Attribute Mode Set

0 Reset Attributes 1 Bright 2 Dim 4 Underscore 5 Blink 7 Reverse 8 Hidden

Foreground Colors 30 Black 31 Red 32 Green 33 Yellow 34 Blue 35 Magenta 36 Cyan 37 White

Background Colors 40 Black 41 Red 42 Green 43 Yellow 44 Blue 45 Magenta 46 Cyan 47 White

Page 7

// Motorola 68HC12 EVB Test Program Hello.c to demonstrate serial port I/O // This program writes a message on the console using DB12->printf(). It reads // keyboard characters using DB12->getchar(). An ANSI escape sequences is used to // clear the screen if a '2' is typed. A '1' repeats the message and the program // responds to other input characters with an appropriate message. // RPK // August 13, 2000 // // This code was written and tested using Introl C 4.0. // #includes #include <hc812a4.h> #include <introl.h> #include <dbug12.h> void __main () { char *mess = "HI"; int choice, n; while(1) { DB12->printf("Hello World!\n\n\r"); // DB12->printf("\n\r"); DB12->printf("( greetings from Russell P. Kraft )\n\n\n\r"); DB12->printf("1=repeat, 2=clear, 0=quit.\n\n\r"); // Menu of choices choice=DB12->getchar(); // DB12->putchar(choice); // select which option to run if (choice == '0') return; // exit(1); else if(choice == '1') DB12->printf("\n\nHere we go again.\n\n\r"); else if(choice == '2') // clear the screen with <ESC>[2J DB12->printf("\033[2J"); else { // inform the user how bright he is // The overwriting of the first parameter gets around a bug in the // printf function that incorrectly outputs the first value. DB12->printf("\n%c\rA %c is not a valid choice.\n\r",choice,choice); // %s doesn't seem to work at all // *mess = "HI"; // n=DB12->printf("%s\rA %s is no good\n\n\r",mess, mess); DB12->printf("A "); DB12->putchar(choice); DB12->printf(" is not a valid choice.\n\n\r"); } } }

Page 8

Page 9

Page 10

Page 11

Table 5 MC68HC812A4 Signal Descriptions (Continued)

Mnemonic Port Description BKGD — Single-wire background interface pin is dedicated to the background debug function.

During reset, this pin determines special or normal operating mode. KWD[7:0] Port D KWH[7:0] Port H

Key wakeup and general-purpose I/O; can cause an interrupt when an input transitions from high to low.

KWJ[7:0] Port J Key wakeup and general-purpose I/O; can cause an interrupt when an input transitions from high to low or from low to high.

RxD0 PS0 Serial communications interface receive pin for SCI0. TxD0 PS1 Serial communications interface transmit pin for SCI0. RxD1 PS2 Serial communications interface receive pin for SCI1. TxD1 PS3 Serial communications interface transmit pin for SCI1.

SDI/MISO PS4 Master in/slave out pin for serial peripheral interface. SDO/MOSI PS5 Master out/slave in pin for serial peripheral interface.

SCK PS6 Serial clock for SPI system. SS PS7 Slave select output for SPI master mode, input for slave mode.

IOC[7:0] Port T Input capture or output compare channels and pulse accumulator input.

Table 6 Port Descriptions

Port Name Direction Function Port A In/Out General-purpose I/O in single-chip modes. External address bus ADDR[15:8] in

expanded modes. Port B In/Out General-purpose I/O in single-chip modes. External address bus ADDR[7:0] in expanded

modes. Port C In/Out General-purpose I/O in single-chip modes. External data bus DATA[15:8] in expanded

wide modes; external data bus DATA[15:8]/DATA[7:0] in expanded narrow modes. Port D In/Out General-purpose I/O in single-chip modes and expanded narrow modes. External data

bus DATA[7:0] in expanded wide mode. As key wakeup can cause an interrupt when an input transitions from high to low.

Port E PE[1:0] In PE[7:2] In/Out

Mode selection, bus control signals and interrupt service request signals; or general-purpose I/O.

Port F In/Out Chip select and general Port G In/Out Memory expansion and general Port H In/Out Key wakeup and general Port J In/Out Key wakeup and general Port S In/Out Serial communications interface and serial peripheral interface subsystems and general Port T In/Out Timer system and general

Port AD In Analog

Page 12

Table 7 Port Pull-Up, Pull-down and Reduced Drive Summary

Enable Bit Reduced Drive Control Bit

Port Name

Resistive Input Loads

Register (Address) Bit Name Reset

State Register

(Address) Bit

Name Reset State

Port A Pull-up PUCR ($000C) PUPA Enabled RDRIV ($000D) RDPAB Full Drive

Port B Pull-up PUCR ($000C) PUPB Enabled RDRIV ($000D) RDPAB Full Drive

Port C Pull-up PUCR ($000C) PUPC Enabled RDRIV ($000D) RDPC Full Drive

Port D Pull-up PUCR ($000C) PUPD Enabled RDRIV ($000D) RDPD Full Drive

Port E:

PE7, PE3, PE2, PE0 Pull-up PUCR ($000C) PUPE Enabled RDRIV ($000D) RDPE Full Drive

PE1 Pull-up Always Enabled RDRIV ($000D) RDPE Full Drive

PE[6:4] None — RDRIV ($000D) RDPE Full Drive

PE[6:5] Pull-down Enabled During Reset — — —

Port F Pull-up PUCR ($000C) PUPF Enabled RDRIV ($000D) RDPF Full Drive

Port G Pull-up PUCR ($000C) PUPG Enabled RDRIV ($000D) RDPG Full Drive

Port H Pull-up PUCR ($000C) PUPH Enabled RDRIV ($000D) RDPH Full Drive

Port J Pull-up/down1

PULEJ ($002E) PULEJ[7:0] Disabled RDRIV ($000D) RDPJ Full Drive

Port S Pull-up SP0CR2 ($00D1) PUPS Enabled SP0CR2

($00D1) RDS Full Drive

Port T Pull-up TMSK2 ($008D) PUPT Disabled TMSK2 ($008D) RDPT Full Drive

Port AD None — —

BKGD Pull-up — — Enabled — — Full Drive 1. Pull-up or pulldown devices for each port J pin can be selected with the PUPSJ register ($002D). After reset, pulldowns are selected for all port J pins but must be enabled with PULEJ register.

Page 13

4 Register Block The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies the first 512 bytes of the 2-Kbyte block. Default addressing (after reset) is indicated in the table below. For additional information refer to 6 Operating Modes and Resource Mapping.

Table 8 MC68HC812A4 Register Map (Sheet 1 of 4)

Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA1 $0001 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB1 $0002 Bit 7 6 5 4 3 2 1 Bit 0 DDRA1 $0003 Bit 7 6 5 4 3 2 1 Bit 0 DDRB1 $0004 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTC1 $0005 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTD2 $0006 Bit 7 6 5 4 3 2 1 Bit 0 DDRC1 $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD2 $0008 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE3 $0009 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 DDRE3 $000A ARSIE PLLTE PIPOE NECLK LSTRE RDWE 0 0 PEAR4 $000B SMODN MODB MODA ESTR IVIS 0 EMD EME MODE4 $000C PUPH PUPG PUPF PUPE PUPD PUPC PUPB PUPA PUCR4 $000D RDPJ RDPH RDPG RDPF RDPE RDPD RDPC RDPAB RDRIV4 R $000E 0 0 0 0 0 0 0 0 Reserved4 $000F 0 0 0 0 0 0 0 0 Reserved4 $0010 RAM15 RAM14 RAM13 RAM12 RAM11 0 0 0 INITRM $0011 REG15 REG14 REG13 REG12 REG11 0 0 0 INITRG $0012 EE15 EE14 EE13 EE12 0 0 0 EEON INITEE $0013 EWDIR NDRC 0 0 0 0 0 0 MISC R $0014 RTIE RSWAI RSBCK 0 RTBYP RTR2 RTR1 RTR0 TICTL $0015 RTIF 0 0 0 0 0 0 0 RTIFLG $0016 CME FCME FCM FCOP DISR CR2 CR1 CR0 COPCTL $0017 Bit 7 6 5 4 3 2 1 Bit 0 COPRST $0018 ITE6 ITE8 ITEA ITEC ITEE ITF0 ITF2 ITF4 ITST0 $0019 ITD6 ITD8 ITDA ITDC ITDE ITE0 ITE2 ITE4 ITST1 $001A ITC6 ITC8 ITCA ITCC ITCE ITD0 ITD2 ITD4 ITST2 $001B 0 0 0 0 0 ITC0 ITC2 ITC4 ITST3 R $001C 0 0 0 0 0 0 0 0 Reserved $001D 0 0 0 0 0 0 0 0 Reserved $001E IRQE IRQEN DLY 0 0 0 0 0 INTCR $001F 1 1 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 HPRIO $0020 Bit 7 6 5 4 3 2 1 Bit 0 KWIED5 $0021 Bit 7 6 5 4 3 2 1 Bit 0 KWIFD5 $0022 0 0 0 0 0 0 0 0 Reserved $0023 0 0 0 0 0 0 0 0 Reserved

$0024 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PORTH $0025 Bit 7 6 5 4 3 2 1 Bit 0 DDRH $0026 Bit 7 6 5 4 3 2 1 Bit 0 KWIEH $0027 Bit 7 6 5 4 3 2 1 Bit 0 KWIFH

$0028 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PORTJ

Page 14

Table 8 MC68HC812A4 Register Map (Sheet 2 of 4)

Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0029 Bit 7 6 5 4 3 2 1 Bit 0 DDRJ $002A Bit 7 6 5 4 3 2 1 Bit 0 KWIEJ $002B Bit 7 6 5 4 3 2 1 Bit 0 KWIFJ $002C Bit 7 6 5 4 3 2 1 Bit 0 KPOLJ $002D Bit 7 6 5 4 3 2 1 Bit 0 PUPSJ $002E Bit 7 6 5 4 3 2 1 Bit 0 PULEJ $002F 0 0 0 0 0 0 0 0 Reserved $0030 0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTF

$0031 0 0 PG5 PG4 PG3 PG2 PG1 PG0 PORTG $0032 0 Bit 6 5 4 3 2 1 Bit 0 DDRF

$0033 0 0 Bit 5 4 3 2 1 Bit 0 DDRG $0034 PDA19 PDA18 PDA17 PDA16 PDA15 PDA14 PDA13 PDA12 DPAGE $0035 PPA21 PPA20 PPA19 PPA18 PPA17 PPA16 PPA15 PPA14 PPAGE $0036 PEA17 PEA16 PEA15 PEA14 PEA13 PEA12 PEA11 PEA10 EPAGE $0037 DWEN PWEN EWEN 0 0 0 0 0 WINDEF $0038 0 0 A21E A20E A19E A18E A17E A16E MXAR $0039 0 0 0 0 0 0 0 0 Reserved $003A 0 0 0 0 0 0 0 0 Reserved $003B 0 0 0 0 0 0 0 0 Reserved $003C 0 CSP1E CSP0E CSDE CS3E CS2E CS1E CS0E CSCTL0 $003D 0 CSP1FL CSPA21 CSDHF CS3EP 0 0 0 CSCTL1 $003E 0 0 SRP1A SRP1B SRP0A SRP0B STRDA STRDB CSSTR0 $003F STR3A STR3B STR2A STR2B STR1A STR1B STR0A STR0B CSSTR1 $0040 0 0 0 0 LDV11 LDV10 LDV9 LDV8 LDV $0041 LDV7 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0 LDV $0042 0 0 0 0 RDV11 RDV10 RDV9 RDV8 RDV $0043 RDV7 RDV6 RDV5 RDV4 RDV3 RDV2 RDV1 RDV0 RDV $0044 0 0 0 0 0 0 0 0 Reserved $0045 0 0 0 0 0 0 0 0 Reserved $0046 0 0 0 0 0 0 0 0 Reserved $0047 LCK PLLON PLLS BCSC BCSB BCSA MCSB MCSA CLKCTL $0048– $005F 0 0 0 0 0 0 0 0 Reserved

$0060 0 0 0 0 0 0 0 0 ATDCTL0 $0061 0 0 0 0 0 0 0 0 ATDCTL1 $0062 ADPU AFFC AWAI 0 0 0 ASCIE ASCIF ATDCTL2 $0063 0 0 0 0 0 0 FRZ1 FRZ0 ATDCTL3 $0064 0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATDCTL4 $0065 0 S8CM SCAN MULT CD CC CB CA ATDCTL5 $0066 SCF 0 0 0 0 CC2 CC1 CC0 ATDSTAT $0067 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATDSTAT $0068 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 ATDTEST $0069 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 ATDTEST

$006A– $006E 0 0 0 0 0 0 0 0 Reserved

$006F PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 PORTAD $0070 Bit 7 6 5 4 3 2 1 Bit 0 ADR0H $0071 0 0 0 0 0 0 0 0 Reserved

$0072 Bit 7 6 5 4 3 2 1 Bit 0 ADR1H

Page 15

Table 8 MC68HC812A4 Register Map (Sheet 3 of 4)

Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0073 0 0 0 0 0 0 0 0 Reserved $0074 Bit 7 6 5 4 3 2 1 Bit 0 ADR2H $0075 0 0 0 0 0 0 0 0 Reserved $0076 Bit 7 6 5 4 3 2 1 Bit 0 ADR3H $0077 0 0 0 0 0 0 0 0 Reserved $0078 Bit 7 6 5 4 3 2 1 Bit 0 ADR4H $0079 0 0 0 0 0 0 0 0 Reserved $007A Bit 7 6 5 4 3 2 1 Bit 0 ADR5H $007B 0 0 0 0 0 0 0 0 Reserved $007C Bit 7 6 5 4 3 2 1 Bit 0 ADR6H $007D 0 0 0 0 0 0 0 0 Reserved $007E Bit 7 6 5 4 3 2 1 Bit 0 ADR7H $007F 0 0 0 0 0 0 0 0 Reserved $0080 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS $0081 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 CFORC $0082 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7M $0083 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 OC7D $0084 Bit 15 14 13 12 11 10 9 Bit 8 TCNT $0085 Bit 7 6 5 4 3 2 1 Bit 0 TCNT $0086 TEN TSWAI TSBCK TFFCA PAOQE T7QE T1QE T0QE TSCR $0087 PAOQB PAOQA T7QB T7QA T1QB T1QA T0QB T0QA TQCR $0088 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 TCTL1 $0089 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 TCTL2 $008A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3 $008B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4 $008C C7I C6I C5I C4I C3I C2I C1I C0I TMSK1 $008D TOI 0 TPU TDRB TCRE PR2 PR1 PR0 TMSK2 $008E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1 $008F TOF 0 0 0 0 0 0 0 TFLG2 $0090 Bit 15 14 13 12 11 10 9 Bit 8 TC0 $0091 Bit 7 6 5 4 3 2 1 Bit 0 TC0 $0092 Bit 15 14 13 12 11 10 9 Bit 8 TC1 $0093 Bit 7 6 5 4 3 2 1 Bit 0 TC1 $0094 Bit 15 14 13 12 11 10 9 Bit 8 TC2 $0095 Bit 7 6 5 4 3 2 1 Bit 0 TC2 $0096 Bit 15 14 13 12 11 10 9 Bit 8 TC3 $0097 Bit 7 6 5 4 3 2 1 Bit 0 TC3 $0098 Bit 15 14 13 12 11 10 9 Bit 8 TC4 $0099 Bit 7 6 5 4 3 2 1 Bit 0 TC4 $009A Bit 15 14 13 12 11 10 9 Bit 8 TC5 $009B Bit 7 6 5 4 3 2 1 Bit 0 TC5 $009C Bit 15 14 13 12 11 10 9 Bit 8 TC6 $009D Bit 7 6 5 4 3 2 1 Bit 0 TC6 $009E Bit 15 14 13 12 11 10 9 Bit 8 TC7 $009F Bit 7 6 5 4 3 2 1 Bit 0 TC7 $00A0 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI PACTL $00A1 0 0 0 0 0 0 PAOVF PAIF PAFLG $00A2 Bit 15 14 13 12 11 10 9 Bit 8 PACNT $00A3 Bit 7 6 5 4 3 2 1 Bit 0 PACNT

Page 16

Table 8 MC68HC812A4 Register Map (Sheet 4 of 4)

1. Port A, port B, port C and data direction registers DDRA, DDRB, and DDRC are not in map in expanded and peripheral

modes. 2. Port D and DDRD not in map in wide expanded modes and peripheral mode; also not in map in narrow special expanded

mode with EMD set. 3. Port E and DDRE not in map in peripheral mode; also not in map in expanded modes with EME set. 4. Registers also not in map in peripheral mode. 5. Key wake-up associated with port D not in map in wide expanded modes; also not in map in narrow special expanded mode

with EMD set.

Address Bit 7 6 5 4 3 2 1 Bit 0 Name $00A4– $00AC 0 0 0 0 0 0 0 0 Reserved

$00AD 0 0 0 0 0 0 TCBYP PCBYP TIMTST $00AE PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PORTT $00AF Bit 7 6 5 4 3 2 1 Bit 0 DDRT $00B0– $00BF 0 0 0 0 0 0 0 0 Reserved

$00C0 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC0BDH $00C1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC0BDL $00C2 LOOPS WOMS RSRC M WAKE ILT PE PT SC0CR1 $00C3 TIE TCIE RIE ILIE TE RE RWU SBK SC0CR2 $00C4 TDRE TC RDRF IDLE OR NF FE PF SC0SR1 $00C5 0 0 0 0 0 0 0 RAF SC0SR2 $00C6 R8 T8 0 0 0 0 0 0 SC0DRH $00C7 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 SC0DRL $00C8 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC1BDH $00C9 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC1BDL $00CA LOOPS WOMS RSRC M WAKE ILT PE PT SC1CR1 $00CB TIE TCIE RIE ILIE TE RE RWU SBK SC1CR2 $00CC TDRE TC RDRF IDLE OR NF FE PF SC1SR1 $00CD 0 0 0 0 0 0 0 RAF SC1SR2 $00CE R8 T8 0 0 0 0 0 0 SC1DRH $00CF R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 SC1DRL $00D0 SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF SP0CR1 $00D1 SPFQE SPFQB SPFQA 0 PUPS RDS 0 SPC0 SP0CR2 $00D2 0 0 0 0 0 SPR2 SPR1 SPR0 SP0BR $00D3 SPIF WCOL 0 MODF 0 0 0 0 SP0SR $00D4 0 0 0 0 0 0 0 0 Reserved $00D5 Bit 7 6 5 4 3 2 1 Bit 0 SP0DR $00D6 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PORTS $00D7 Bit 7 6 5 4 3 2 1 Bit 0 DDRS

$00D8– $00DF 0 0 0 0 0 0 0 0 Reserved

$00E0– $00EF 0 0 0 0 0 0 0 0 Reserved

$00F0 1 1 1 1 1 1 PROTLCK EERC EEMCR $00F1 1 BPROT6 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 EEPROT $00F2 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 EETST $00F3 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM EEPROG

$00F4– $01FF 0 0 0 0 0 0 0 0 Reserved

Page 17

LED Display Board

A/D Converter Input Voltage Board