G. CONTIN, P. RIEDLER, A . RIVETTI

Update on Strip R&DITS upgrade - 11.10.2011

G. Contin - Strip R&D Update

2

Outline

11/10/2011

Dummy sensor masksSensor performance simulationsMicrocables developmentSensor layout

3

Dummy sensor and chips

11/10/2011G. Contin - Strip R&D Update

Dummy sensor mask submitted to FBK 2 rows of 20 mm strip per side 2 dummy chip included in the wafer

128 channels nominal size: 5900 um X 6250 um input pad pitch: 42.5 um

256 channels nominal size: 11850 um X 6250 um input pad pitch: 44.5 um

production expected for end 2011 15 sensors 400 chips w/ 128 ch. 350 chips w/ 256 ch.

microcables bonding test

draft

Good and ghost points - present configuration

Simulation:● present layout● 500 MeV/c pions● normal to the sensor● realistic signal-to-noise ratio● 2D points with only geometric considerations

11/10/2011 G. Contin - Strip R&D Update 4

Miljenko Šuljić, Stefano. Giacomo

Good and ghost points - new configuration

Simulation:● half-length strip layout● 500 MeV/c pions● normal to the sensor● realistic signal-to-noise ratio● 2D points with only geometric considerations

11/10/2011 G. Contin - Strip R&D Update 5

Miljenko Šuljić, Stefano. Giacomo

G. Contin - Strip R&D Update

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11/10/2011

Miljenko Šuljić, Stefano. Giacomo

G. Contin - Strip R&D Update

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SSD micro-cables

11/10/2011

Specifications: Kapton-Aluminum Thickness: 10 mm + 14 mm Pitch: 44 mm (chip) / 47.5 mm (sensor) Length: ~ 25 mm / ~ 50 mm

Assembly and folding TAB bonding technique Bonding windows facing sensor/chip different hybrid layouts for P/N side

G. Contin - Strip R&D Update

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Microcable specifications

Chipcable layout

Cable-to-hybrid

bonding area

Cable-to-Chip bonding area (output

pads)

Cable-to-Chip bonding area (input

pads)

Transmitting area

Cable-to-sensor bonding area

Trace pitch, um 136 136 44 47.5 47.5Trace width, um

~ 80 ~ 50 ~30 ~22 ~30

Trace quantity, pcs

43 43 128 128 128

Bonding pads one row one row two rows (staggered)

- two rows (staggered)

Technological area(electrical test pads, bond test

elements)

Work area

Work area

• Chipcable developed for assembling to ALICE 128 dummy chips• Material: an aluminum-polyimide adhesive-less foiled dielectric FDI-A20 • Thickness: Al 10um, Polyimide 10um

11/10/2011

SE SRTIIE - Karkhov

G. Contin - Strip R&D Update

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Microcable prototypes

Automatic test equipmentfor chipcables and tabbed dummy chips testing

Contact device based on

YAMAICHI socket for TAB-70 frames

First manufactured chipcables in TAB-70 frame

Work area

Work area

•Prototypes dimension adapted to TAB-70 frames:• Allows automatic test of cables and tabbed chips (cable-to-chip

assembly)• 2 cables per sample

•Shorter transmitting area wrt design to fit the TAB-70 frame•Cable width corresponds to the ALICE 128 dummy chip width

11/10/2011

SE SRTIIE - Karkhov

10

In the pipeline…

11/10/2011G. Contin - Strip R&D Update

New simulations Point reconstruction with p-n charge matching Spatial resolution as a function of the stereo angle

Manufacturing of microcables with different layouts

Bonding / assembly test of chip-cables-sensorComplete module design

Hybrid layout Cooling pipes placement Space for support holders in cables/hybrids Cable folding on sensor

G. Contin - Strip R&D Update

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BACKUP

11/10/2011

G. Contin - Strip R&D Update

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ASIC development

11/10/2011

ASIC specs HAL25 (Present SSD)

Upgrade target

CMOS technology 0.25 µm 0.13 µm (?)

Input pitch 80 µm ~44 µmOn 2 staggered rows (?)

ASIC size 3.65 x 11.90 mm2 5-6 x 6 mm2 (?)

Dynamic range 1MeV~290000 e-

≿1.3MeV (15 Mip)~360000 e-

Charge resolution ~1 keV~290 e-

~1 keV (0.1 Mip)~290 e-

Noise (ENC for 5 pF load cap.)

< 300 e- < 300 e-

Investigating for available solutions for strip ASIC front-end chip: contacts with UK and CERN Groups

Specification definition in progress:

G. Contin - Strip R&D Update

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ASIC specifications

11/10/2011

ASIC specs HAL25 (Present SSD)

Upgrade target

Peaking time 1.4 – 2.2 µs ≤1 µs

Readout & Format Serial, analogue Digital (?)

ADC Off-detector On chip (?)

Common Mode correction

Off-detector On chip (?)

Power dissipation per channel[µW]

<1ms> : 265 - 360Readout: 680 - 759Acquisition: 290 – 355

Less than present

# channels per chip 128 128

Total # of channels 2.6 M ~1 – 5 M (?)

Expected Dose/Hadron Fluence (10 years)

// 30 kRad (TID)6*1011 cm -2 (hadron fluence in 1MeV n)