Undergraduate Research Project

Hybrid Gate Driver Parasitic Extraction

Sponsor: CPES

George Suárez MartínezAdvisors: Manuel Jiménez & Miguel Vélez-Reyes

University of Puerto Rico-Mayagüez

#XX

20032003

Introduction Parasitic extraction plays a central role in the design of Integrated Power Electronics Modules (IPEMs) [1]. This is mainly due to the impact of parasitic inductances and capacitances on circuit performance, efficiency, EMI, and frequency of operation [2]. An IPEM consists of two MOSFET’s mounted on one side of an Aluminum Oxide Direct Bonded Copper (DBC) board and activated by an hybrid gate driver [1]. The gate driver is the device of interest for this project. Through simulation we aim at extracting its parasitic capacitances, inductances, and resistances. Figure 1 shows a picture of an IPEM, where the gate driver is located in the top center rectangle, while Figure 2 shows its schematic diagram.

A gate driver is a triggering circuit used to activate one of the MOSFETS’s of the IPEM at a time. It uses a low voltage signal to switch between the two MOSFET’s, which operate at relatively higher voltages. This particular gate driver consists of an IR2113S (High and Low Side Driver) represented by U1, two MIC4422BM (9A-Peak Low-Side MOSFET Driver) shown as U2 and U3, in addition to eight capacitors and a diode. Figure 3 shows a picture of a gate drive, while Figure 4 provides the corresponding schematic diagram.

Parasitic Extraction using Maxwell Q3D Extractor 4

A rigorous procedure needs to be followed in order to extract the parasitic components of a gate driver using Maxwell Q3D. After specifying the parameters to be extracted the Maxwell model must be constructed with the physical and geometrical characteristics of the device [3]. Figure 5 shows the Maxwell model of the gate driver layers and materials composition while Figure 6 shows the complete model. This model shows all the components of the gate driver, emphasizing the board and conduction paths needed for analysis purposes.

ResultsSo far we have extracted the parasitic ac inductance and resistance, dc inductance and resistance, and capacitance for the Hybrid Gate Driver of a second generation IPEM. The ac inductances range from 10-6 to 10-9 (mH), 10-6 to 10-9 (Ohms) for the ac resistance, 10-6 to 10-9 (mH) for the dc inductance, 10-6 to 10-9 (Ohms) for the dc resistance, and 10-6 to 10-9 (pF) for the capacitance. 

Setting up the materials is an important part of the parameter extraction process. This includes specifying the correct materials for each part. The equations to be solved use these values in the extraction process [3]. The gate driver is composed of gold conducting paths, a silver top pad, an FR4 epoxy board, silver vias, a bottom trace, and an aluminum oxide (Al2O3) layer.

 

Figure 1 – IPEM Generation II Figure 2 – IPEM Generation II schematic

Figure 5 – Gate Driver layout Maxwell model Figure 6 –Gate Driver Maxwell model

Top Trace (Gold)

Top Pad (Silver)

Vias (Silver)

Dielectric(FR4 Epoxy)

Bottom Trace(Silver)

Al2O3

Figure 3 – Gate Driver Figure 4 – Gate Driver schematic

 Currents flow directions are required in order to complete the parasitic inductance and resistance extraction. Maxwell Q3D manages the current flows as sources and sinks [3]. It is important to specify a source or sources to a unique sink for each piece of the silver bottom trace and also for the other conducting paths that do not interconnect with the bottom layer. Figure 7 shows the gate driver current flows diagram.

Vss

LD

EN LG LS

HS

HG

Figure 7 – Gate Driver Maxwell Model currents flow assignment

Capacitance (pF)

0

10

20

30

40

50

60

Bott

om

_tr

ace

Bott

om

_tr

ace1

Bott

om

_tr

ace2

EN

HD

HG

LD

LG t1 t7

Bottom_trace Bottom_trace1

Bottom_trace2 EN

HD HG

LD LG

t1 t7

DC Inductance (mH)

0.00E+00

2.00E-06

4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

Botto

m_tra

ce:vc

c_in

Botto

m_tra

ce1:v

ss_in

Botto

m_tra

ce2:H

S_in

Botto

m_tra

ce2:v

cc_D

_in EN:E

N_in

HD:H

D_in

HG:H

G_in

LD:LD

_in

LG:LG

_in

t1:U1

-U3_

in

Bottom_trace:vcc_in

Bottom_trace1:vss_in

Bottom_trace2:HS_in

Bottom_trace2:vcc_D_in

EN:EN_in

HD:HD_in

HG:HG_in

LD:LD_in

LG:LG_in

t1:U1-U3_in

AC Resistance (Ohms) at 100 MHz

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Botto

m_t

race

:vcc_

in

Botto

m_t

race

1:vs

s_in

Botto

m_t

race

2:HS

_in

Botto

m_t

race

2:vc

c_D_

in

EN:E

N_in

HD:H

D_in

HG:H

G_in

LD:L

D_in

LG:L

G_in

t1:U

1-U3

_in

Bottom_trace:vcc_in

Bottom_trace1:vss_in

Bottom_trace2:HS_in

Bottom_trace2:vcc_D_in

EN:EN_in

HD:HD_in

HG:HG_in

LD:LD_in

LG:LG_in

t1:U1-U3_in

DC Resistance (Ohms)

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

Botto

m_t

race

:vcc_

in

Botto

m_t

race

1:vss

_in

Botto

m_t

race

2:HS_

in

Botto

m_t

race

2:vcc

_D_in EN

:EN_

in

HD:H

D_in

HG:H

G_in

LD:LD

_in

LG:L

G_in

t1:U

1-U3

_in

Bottom_trace:vcc_in

Bottom_trace1:vss_in

Bottom_trace2:HS_in

Bottom_trace2:vcc_D_in

EN:EN_in

HD:HD_in

HG:HG_in

LD:LD_in

LG:LG_in

t1:U1-U3_in

Figure 8-1 Gate Driver ac parasitic inductances Figure 8-2 Gate Drive parasitic dc inductances

Figure 8-3 Gate Driver ac parasitic resistances Figure 8-4 Gate Driver dc parasitic resistances

Figure 8-5 Gate Driver dc parasitic resistances

AC Inductance (mH)

0.00E+00

1.00E-06

2.00E-06

3.00E-06

4.00E-06

5.00E-06

6.00E-06

7.00E-06

8.00E-06

9.00E-06

1.00E-05

Botto

m_t

race

:vcc_

in

Botto

m_t

race

1:vs

s_in

Botto

m_t

race

2:HS

_in

Botto

m_t

race

2:vc

c_D_

in EN:E

N_in

HD:H

D_in

HG:H

G_in

LD:L

D_in

LG:L

G_in

t1:U

1-U3

_in

Bottom_trace:vcc_in

Bottom_trace1:vss_in

Bottom_trace2:HS_in

Bottom_trace2:vcc_D_in

EN:EN_in

HD:HD_in

HG:HG_in

LD:LD_in

LG:LG_in

t1:U1-U3_in

Abstract 

As part of the development of a methodology to produce layouts of gate drivers for Integrated Power Electronics Modules, parasitic extraction and minimization is an important aspect in this design process. Working on the design of a hybrid gate driver of a second generation IPEM , we explore how to use Maxwell Q3D Extractor 4 for parasitic extraction.

Conclusions & Future Work The parasitic extraction of a gate driver for a Gen. II IPEM was completed. Capacitances as well as DC and AC resistances and inductances were obtained for frequencies up to 200KHz for AC components. Future work includes model validation at different frequencies.

References 

[1] Jonah Z. Chen, Yingxiang Wu, Dushan Borojevich and Jan H. Bøhn, “Integrated Electrical and Thermal Modeling and Analysis of IPEMs” , CPES Procedure Book 2000, page 170-173.[2] Jonah Z. Chen, Ying Feng Pang, Dushan Boroyevich, Elaine P. Scott and Karen A. Thole. “Electrical and Thermal Layout Design Considerations For Integrated Power Electronic Modules[3] Maxwell Q3D Extractor Version 4.0, Ansoft Corporation, Pittsburgh, PA, http://www.ansoft.com.