Ultrathin InAs-Channel MOSFETs on Si Substrates

Cheng-Ying Huang1, Xinyu Bao2, Zhiyuan Ye2, Sanghoon Lee1, Hanwei Chiang1, Haoran Li1, Varistha

Chobpattana3, Brian Thibeault1, William Mitchell1, Susanne Stemmer3, Arthur Gossard1,3, Errol

Sanchez2, and Mark Rodwell1

1ECE, University of California, Santa Barbara2Applied Materials, Santa Clara

3Materials Department, University of California, Santa Barbara

VLSI-TSA 2015HsinChu, Taiwan

Why InGaAs/InAs FETs?• III-V channel: low electron effective mass, high velocity, high

mobility higher current at lower VDD

• Problems:- Devices: low bandgap high BTBT leakage

high permittivity worse electrostatics, large SS and DIBL- Materials: Integration of III-V on Si, High-K dielectrics on III-V• Goal: Fabricate ultrathin channel III-V FETs on Si

2

-0.4 -0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/m

)I DS (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2V

DS = 0.1 to 0.7 V

0.2 V increment

C. Huang et al., DRC 2014

Record III-V FETs on InP substratesS. Lee et al., VLSI 2014

310 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014 J . Lin, IEDM 2013 T. Kim, IEDM 2013 Intel, IEDM 2009 J . Gu, IEDM 2012 D. Kim, IEDM 2012

I on (

mA

/m

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/m

-0.3-0.2-0.1 0.0 0.1 0.2 0.3 0.4 0.510-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/

m)

Curr

ent D

ensi

ty (m

A/

m)

Gate Bias (V)

0.0

0.5

1.0

1.5

2.0

2.5

3.0L

g = 25 nm

SS~ 72 mV/dec.

SS~ 77 mV/dec.

Ion= 500 A/m at Ioff

=100 nA/mand V

D=0.5V

Vertical Spacer

N+ S/D

MOSFET: 2.5nm ZrO2/ 1nm Al2O3 / 2.5nm InAs

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

eak

age|

(A

/cm

2)

Cu

rren

t D

ensi

ty (

mA

/m

)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse SweepSolid: Forward SweepL

g = 1 m

61 mV/dec Subthreshold swing at VDS=0.1 V

Negligible hysteresis 4

Applied Materials III-V buffer on Si

Rq=3.1 nm RHEED in MBE

5

UCSB III-V FET epitaxy

Rq= 6.9 nm

Surface roughness is degraded after FET epitaxy.

6

UCSB Gate Last Process Flow

7

Channel

HfO2

III-V BarrierSi substrate

N+ S/D

IsolationStrip dummy gate Digital etchDeposit dielectricFGA anneal

Channel

Ni

III-V BarrierSi substrate

N+ S/D

Lift-off gate metal

Channel

Ni

III-V BarrierSi substrate

N+ S/D

Ti/Pd/Au

DepositS/D contacts

Channel

HSQ

III-V BarrierSi substrate

Pattern dummy gate

Channel

III-V BarrierSi substrate

MBE/MOCVD grown device epilayer

Channel

HSQ

III-V BarrierSi substrate

N+ S/D

MOCVD source/drain regrowth

TEM images of III-V FET on Si

Lg~20nm8

Lg~20nm

Short gate length: Lg-20 nm

-0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/m

)I D (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

SS ~ 142.4 mV SS ~ 100.8 mV

VDS

= 0.1 to 0.7 V, step 0.2 V

• High Gm~2.0 mS/μm at VD=0.5 V.• SS~140 mV/dec. at VD=0.5 V and 101 mV/dec. at VD=0.1 V

• High Ion >1.4 mA/um at VGS=1V.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.5

1.0

1.5

I D (m

A/

m)

VDS

(V)

Ron

= 294 Ohm-m

at VGS

= 1.0 V

VGS

= -0.2 V to 1.0 V

0.2 V increment

9

• SS~74 mV/dec. for Lg-1 μm devices.• Off-state leakage dominated by band-to-band tunneling.• Negligible buffer leakage.

Long gate length: Lg-1 μm

-0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/m

)I D (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

SS ~ 78.1 mV SS ~ 74.7 mV

VDS

= 0.1 to 0.7 V, step 0.2 V

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

0.0

0.5

1.0

1.5

I D (m

A/

m)

VDS

(V)

Ron

= 2210 Ohm-m

at VGS

= 1.0 V

VGS

= -0.2 V to 1.0 V

0.2 V increment

10

On-state characteristics

0.01 0.1 10.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

VDS

= 0.5 V

Gate length (m)

[1] UCSB 2.5nm InAs FETs on InP AMAT-UCSB_3.5nm InAs FETs on Si

Pea

k G

m (m

S/

m)

0.0 0.2 0.4 0.6 0.8 1.00

1000

2000

3000

4000

5000

0 5 10 15 20 250

200

400

600

800

1000

TLM on S/D

Res

ista

nce

(O

hm

m)

Gap (m)

Y3031XR

sh~31 sq

c~7.3 m2

VGS

= 1 V

On R

esis

tance

(O

hm

-m

)Gate length (m)

AMAT-UCSB III-V FET-on-Si

Ron

~247 m at zero Lg

• Long Lg devices show similar Gm to record FETs comparable mobility to 2.5 nm InAs on InP.

• ~25% degradation on S/D sheet resistance and contact resistance. • Thicker channel and degraded RS/D decrease Gm at short Lg. 11

Subthreshold Characteristics

0.01 0.1 160

80

100

120

140

160

180

200

Gate length (m)

Subth

resh

old

Sw

ing (m

V/d

ec)

VDS

=0.1 V, UCSB VLSI 2014 [1]

VDS

=0.5 V, UCSB VLSI 2014 [1]

VDS

=0.1 V, InAs FETs on Si

VDS

=0.5 V, InAs FETs on Si

0.01 0.1 10

50

100

150

200

250

300

350

Vth at 1 A/m

DIB

L (m

V/V

)Gate length (m)

[1] UCSB 2.5nm InAs FETs on InP AMAT-UCSB_3.5nm InAs FETs on Si

• SS and DIBL are degraded due to thicker channel.

• Higher SS at long Lg: higher interface trap density.

12

Within-wafer uniformity:Lg-45nm devices

Gm~1.82 mS/μm

SS~123mV/dec

13

Benchmark of III-V FETs on Si

0 100 200 3000

100

200

300

400

500 [1] UCSB(InP) [2] Intel(Si) [6] HKUST(Si) [7] UTokyo(InAs-OI) [8] UCB(InAs-OI) this work(Si)

VDD

= VGS

-Vt=0.5 V

Vt at 100 nA/m

I on (A

/m

)

Gate Length (nm)

Further improved material quality reduces Ron and increases Ion. Further improved surface roughness allows further thinning thechannel, and improves Cg, SS and Ion.

Ion~235μA/μm @100nA/μm Ioff

14

Summary

15

• Demonstrated high performance, and high yield III-V UTB-FETs on Si substrates using the combination of MOCVD and MBE growth, featuring 3.5~4 nm ultrathin channel and Lg~20 nm.

• Achieved high Gm ~ 2.0 mS/μm at VD =0.5V and high Ion~1.4 mA/m at VGS=1V and Lg~20 nm.

• Improving channel surface roughness will allow further channel thickness scaling, and improve SS and Ion.

• Improving material quality will reduce Ron and increase Gm and Ion.

Thank you! Question?

(backup slides follow)

Within-wafer uniformity: Vth of Lg-45 nm devices

0.070

0.045

0.074

0.043

0.020

0.085

0.054

0.063

0.044

0.054

0.041

0.102

0.047

0.056

0.055

Vt, lin (V) @ 1 μA/μm, VDS=0.1V20 mm

12 mmA

B

C

1 2 3 54

-0.00

3

-0.04

1

0.022

-0.02

0

-0.04

9

0.036

-0.00

6

0.008

-0.04

2

-0.00

6

-0.03

2

0.042

-0.02

6

0.003

-0.02

0

20 mm

12 mmA

B

C

1 2 3 54

Vt,sat (V) @ 1 μA/μm, VDS=0.5V

Hero device: VLSI 2014 late news (Sanghoon Lee)

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

eak

age|

(A

/cm

2)

Cu

rren

t D

ens

ity

(mA

/m

)Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse SweepSolid: Forward SweepL

g = 1 m

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.50.0

0.2

0.4

0.6

0.8

1.0

gm (

mS

/m

)

Cu

rren

t D

ensi

ty (

mA

/m

)

Gate Bias (V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8L

g = 25 nm

Ion

= 500 A/m

(at Ioff

=100 nA/m, VDD

=0.5 V)

VDS

= 0.1 to 0.7 V

0.2 V increment

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 76 mV/V

VT = -85 mV at 1 A/m

SSmin

~ 72 mV/dec. (at VDS

= 0.1 V)

SSmin

~ 77 mV/dec. (at VDS

= 0.5 V)

Lg = 25 nm

VDS = 0.1 to 0.7 V

0.2 V increment

Cu

rre

nt

De

ns

ity

(mA

/m

)

Gate Bias (V)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Cu

rren

t D

ensi

ty (

mA

/m

)Drain Bias (V)

Ron

= 303 Ohm-m

at VGS

= 0.7 V

VGS

= -0.4 V to 0.7 V

0.1 V increment

Courtesy of Sanghoon Lee (UCSB) 18

Reducing leakage (3): Ultra-thin channel

1910 100

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

S. Lee, VLSI 2014 J . Lin, IEDM 2013 T. Kim, IEDM 2013 Intel, IEDM 2009 J . Gu, IEDM 2012 D. Kim, IEDM 2012

I on (

mA

/m

)

Gate Length (nm)

VDS

= 0.5 V

Ioff

=100 nA/m

S. L

ee e

t al.,

VLS

I 201

4

-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 76 mV/V

VT = -85 mV at 1 A/m

SSmin

~ 72 mV/dec. (at VDS

= 0.1 V)

SSmin

~ 77 mV/dec. (at VDS

= 0.5 V)

Lg = 25 nm

VDS = 0.1 to 0.7 V

0.2 V increment

Cu

rre

nt

De

ns

ity

(mA

/m

)

Gate Bias (V)

Record III-V MOS

MOSFET: 2.5nm ZrO2/ 1nm Al2O3 / 2.5nm InAs

-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Ga

te L

eak

age|

(A

/cm

2)

Cu

rren

t D

ensi

ty (

mA

/m

)

Gate Bias (V)

10-5

10-4

10-3

10-2

10-1

100

101

SSmin

~ 61 mV/dec.

(at VDS

= 0.1 V)

SSmin

~ 63 mV/dec.

(at VDS

= 0.5 V)

Dot : Reverse SweepSolid: Forward SweepL

g = 1 m

61 mV/dec Subthreshold swing at VDS=0.1 V

Negligible hysteresis 20

Compared to Intel 14nm finFET

Ioff=10nA/mm, Ion=0.45mA/mm @VDS=0.5V per mm of fin footprint

Re-normalizing to fin periphery: ~0.24 mA/mm

S. Natarajan et al, IEDM 2014, December, San Francisco

21

Reducing leakage (5): Recessed InP S/D spacer

22

12 nm InGaAs spacer 5 nm Recessed InP spacer

-0.2 0.0 0.2 0.4 0.610-910-810-710-610-510-410-310-210-1100101

|IG|

gm (m

S/m

)

I D, |I G

| (m

A/

m)

VGS

(V)

ID

0.0

0.4

0.8

1.2

1.6

2.0

2.4

SS ~ 80.1 mV SS ~ 72.5 mV

VDS

= 0.1 to 0.7 V, 0.2 V step

-0.2 0.0 0.2 0.4 0.610-910-810-710-610-510-410-310-210-1100101

ID

|IG|

SS ~ 77.8 mV SS ~ 75.2 mV

gm (m

S/m

)

I D, |I G

| (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4V

DS = 0.1 to 0.7 V, 0.2 V step

Lg-60 nm

4.5 nm InGaAs

Ni/AuTi/Pd/Au Ti/Pd/Au

ZrO2

10 nm N+InP

50 nm N+InGaAs 50 nm N+InGaAs

10 nm N+InP

3 nm5 nm U.I.D InP 5 nm U.I.D InP

Ni/Au

10 nm N+InP

Back Barrier

4.5 nm InGaAsBack Barrier

1.5 nm InGaAs10 nm U.I.D InGaAs

1.5 nm InGaAsZrO2

50 nm N+InGaAs

10 nm U.I.D InGaAs

50 nm N+InGaAs

Ti/Pd/Au Ti/Pd/Au

Ni/Au

C-Y Huang, 2014 Les Eastman Conference

Reducing leakage (6): Doping-graded InP spacer

Doping-graded InP spacer reduces parasitic source/drain resistance and improves Gm.

Gate leakage limits Ioff~300 pA/μm.23

-0.2 0.0 0.2 0.4 0.610-910-810-710-610-510-410-310-210-1100101

gm (m

S/m

)

I D, |I G

| (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4

|IG|

VDS

= 0.1 to 0.7 V

0.2 V increment

ID

Ron at zero Lg

(Ω∙μm)

5 nm UID InP

13 nmUID InP

Doping graded InP

~199 ~364 ~270

Lg-30 nm, 30Å ZrO2

4.5 nm InGaAs

50 nm InAlAs U.I.D buffer

S.I. InP substrate

2 nm 1E19 cm-3 N+InAlAs

Ni/AuTi/Pd/Au Ti/Pd/Au

250 nm 1E17 cm-3 P-InAlAs100 nm InAlAs U.I.D. buffer

5 nm InAlAs U.I.D. spacer

ZrO2

50 nm N+InGaAs 50 nm N+InGaAs

3 nm

10 nm N+InP

8 nm doping-graded InP

5 nm U.I.D InP5 nm U.I.D InP

Ni/Au

10 nm N+InP8 nm doping graded InP

C-Y Huang, 2014 IEDM

Reducing leakage (7): Thicker Dielectric

-0.6 -0.3 0.0 0.3 0.610-910-810-710-610-510-410-310-210-1100101

gm (m

S/m

)

I D, |I G

| (m

A/

m)

VGS

(V)

ID

|IG|

0.0

0.4

0.8

1.2

1.6

2.0

2.4V

DS = 0.1 to 0.7 V

0.2 V increment

Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm

100:1 smaller Ioff compared to InGaAs spacer

InP graded spacer

24

60 pA/μm

38Å ZrO2

-0.2 0.0 0.2 0.4 0.610-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

gm (m

S/m

)I D (m

A/

m)

VGS

(V)

0.0

0.4

0.8

1.2

1.6

2.0

2.4V

DS = 0.1 to 0.7 V

0.2 V increment

InGaAs spacer

C-Y Huang, 2014 IEDM