ultrafast optoelectronic packet processing for asynchronous, optical-packet-switched networks...

Ultrafast optoelectronic packet processing forasynchronous, optical-packet-switched networks

[Invited]

R. Takahashi, T. Nakahara, K. Takahata, H. Takenouchi, T. Yasui,N. Kondo, and H. Suzuki

NTT Photonics Laboratories, 3-1 Morinosato Wakamiya, Atsugi-shi Kanagawa, 243-0198, Japan

[email protected]

RECEIVED 16 AUGUST 2004;REVISED 4 NOVEMBER 2004;ACCEPTED4 NOVEMBER 2004;PUBLISHED 29 NOVEMBER 2004

We describe hybrid optical–electrical systems that perform header processingand buffering of ultrafast, asynchronous optical packets. Our systems are enabledby three key, novel devices: an all-optical serial-to-parallel converter, an opticalclock-pulse generator, and a photonic parallel-to-serial-converter. These devicesallow utilization of complementary metal-oxide semiconductor technology forcompact, highly functional optical packet processing. A simplified node archi-tecture for asynchronous, optical-packet-switched networks is made possibleby these systems with all the necessary node functions integrated compactly.We also demonstrate an optical label swapper and a photonic random accessmemory for 40-Gbit/s, 16-bit, asynchronous optical packets. © 2004 OpticalSociety of America

OCIS codes:060.4510, 230.1150, 250.3140.

1. Introduction

1.A. Background

The growth of the Internet and Internet-related services has caused Internet protocol (IP)data traffic to overtake voice traffic faster than predicted by the well-known Moore’s law.To cope with this explosive growth of IP traffic, we must not only increase link capacity byusing WDM technology but also improve throughput at the nodes. In addition, the entirenetwork must be optimized for IP data traffic and the underlying IP support protocols. Theoptimization must take into consideration three fundamental requirements: flexibility ofresource allocation and reallocation, scalability of network topologies and algorithms, andcost effectiveness.

Photonic multiprotocol label switching (MPLS) technologies [1–7] such as generalizedMPLS (GMPLS), optical burst switching (OBS), and optical packet switching (OPS) haveemerged as promising solutions that meet the above requirements because they eliminatethe asynchronous transfer mode (ATM) and synchronous optical network and synchronousdigital hierarchy (SONET/SDH) layers and integrate an IP layer with a photonic layer. GM-PLS uses wavelengths as labels and operates based on circuit-switching technology. Allpacket-forwarding decisions are made at the edge nodes, which means that only switch-ing tasks are carried out at the core nodes, alleviating the burden on them significantly.However, GMPLS suffers from several limitations because its data granularity is too large(wavelength capacity). There are too few wavelengths to accommodate all the light pathsrequired, which means poor network scalability and poor flexibility to support new appli-cations and services.

OPS can overcome the above-mentioned granularity because it provides arbitrary gran-ularity at the packet level. Since good time-domain statistical multiplexing performance

© 2004 Optical Society of AmericaJON 5048 December 2004 / Vol. 3, No. 12 / JOURNAL OF OPTICAL NETWORKING 914

can be achieved with fine granularity, OPS has the potential to maximize fiber capacityutilization when it is combined with WDM technology. However, severe difficulties relatedto label processing and contention resolution are encountered at every node.

1.B. Optical Packet Switching

In standard IP networks, all forwarding decisions are based on the destination-orientedrouting protocol with destination information contained in the IP packet header, which im-poses limitations on routing functionality and traffic engineering. On the other hand, anOPS network utilizes labels that are carried in the packet. The label is used to identify aforwarding equivalence class (FEC), i.e., a set of packets that is forwarded over the samepath through the network. Packets are assigned to FECs depending on their source anddestination, quality-of-service (QoS) requirements, and other parameters. This is particu-larly advantageous because various applications and new services can be added by simplymodifying how packets are assigned to FECs, tremendously increasing network flexibility.In addition, the number of address entries in the forwarding table can be reduced to sev-eral hundred, which is minute compared with the more than 500,000 entries required instandard IP networks.

Another advantage of OPS networks is that the control and forwarding componentsare completely separated, thus enabling each component to be developed and modifiedindependently. The control component uses the standard IP routing protocol to exchangeinformation with other label-switched routers (LSRs) and thereby build and maintain aforwarding table. The forwarding component is based on a label-swapping forwarding al-gorithm. That is, when a labeled packet arrives at a core LSR, the label is checked againstthe entries in the forwarding table with an exact-match algorithm, and the output label andthe outgoing interface are retrieved. The forwarding component then updates or swaps thelabel and directs the packet to the outgoing interface across the optical switch fabric [7]. Atthe egress LSR the label is discarded and the packet is forwarded to the standard IP networkby use of the conventional longest-match IP routing algorithm.

OPS networks use either a synchronous (slotted) or asynchronous (unslotted) networkstrategy [6]. In a synchronous network, all packets have a fixed length and are placed in afixed time slot. Fixed-length packets imply the need to segment variable-length IP packetsat the ingress LSRs and reassemble them at the egress LSRs. In addition, packets frommultiple input ports must arrive simultaneously at the switch fabric [8]. Maintaining suchinput synchronization would be a severe task in the optical domain because packet arrivaltimes vary as a result of different propagation distances, chromatic dispersion in opticalfibers, and environmental temperature changes. On the other hand, asynchronous networkscan handle packets with variable lengths and do not require packet segmentation and re-assembly at the edge LSRs, which makes the network more suitable for native IP packets.Furthermore, a simpler node architecture is possible because no burdensome input syn-chronization mechanism is needed. However, the unpredictable behavior of asynchronouspackets increases the probability of packet contention, which reduces network throughputand increases the packet loss ratio. Contention resolution can be achieved with optical fiberdelay line (FDL) buffers, but the large, fixed granularity of the optical FDL buffer oftenproduces a long gap or void between the output packets, resulting in further reduction ofthe network throughput.

In light of the foregoing, except for the difficulty in implementing the forwarding com-ponent, asynchronous OPS is potentially the best technology among the various types ofphotonic MPLS methods. In this paper, we review our recent work on asynchronous OPS.In Section2, we describe our systems for optical header processing and buffering and anasynchronous OPS node architecture that makes optimal use of optics and electronics. InSection3, we describe three key devices: an all-optical serial-to-parallel converter, an op-


tical clock-pulse generator, and a photonic parallel-to-serial converter. In Section4, wedemonstrate an optical label swapper and a photonic random access memory (RAM) for40-Gbit/s, 16-bit asynchronous optical packets.

2. Hybrid Optical–Electrical Approach to Asynchronous, Optical-Packet-SwitchingNetworks

2.A. Optical Header Processing

2.A.1. Label Transmission Schemes

Among several proposed label transmission schemes for OPS networks, subcarrier multi-plexing [9] is attractive for packets at 10 Gbit/s or less. This approach enables the labelrecognition and swapping procedures to be performed either electrically or optically. How-ever, the subcarrier frequency must usually be higher than the payload data rate so that itdoes not overlap the baseband signal. This means that expensive high-speed microwavecomponents are required, and the payload data rate is limited to rates that are lower thanthe operating speed of the microwave electronic devices.

A method of transmitting a low-bit-rate label at a different wavelength from that ofthe payload has also been proposed [10]. The procedure of packet insertion and erasure atedge LSRs is simplified by use of passive wavelength multiplexing–demultiplexing. How-ever, this approach suffers from the chromatic dispersion of optical fiber, and it wastes thewavelength resources in WDM systems, since each wavelength channel requires a differentwavelength for the label.

Another approach is to transmit the label and payload serially on the same wavelength.With this technique, low-bit-rate labels, baseband labels, or optical code-division multi-plexed (OCDM) labels can be used. The low-bit-rate labels can be easily processed with-out burdening the electronic label-processing circuits. However, if the label bit rate is toolow, the occupation ratio of the label within the packet increases, especially in a high-speedshort packet, reducing throughput. In addition, retrieval of label information takes longer.The OCDM labels are high-bit-rate optical codes [5]. Label recognition is performed inan all-optical fashion with passive optical devices, leading to short processing times. Abaseband label is transmitted at the same bit rate as the payload. Several all-optical pattern-matching techniques have been proposed to process baseband labels, including a passiveoptical correlator composed of an array of fiber Bragg gratings as tunable reflectivity mir-rors [9], an all-optical comparator that uses a spin-polarized semiconductor optical switch[11], and an all-optical AND gate based on a semiconductor optical amplifier [12]. Thesemethods require as many devices as the number of address entries. Alternative solutionshave been proposed that use active time-to-wavelength [13] or time-to-space mapping [14]techniques. Since these methods convert an input high-speed serial label into parallel bits,label recognition can be performed on a bit-level basis by electronic means. Several newapproaches have begun using optical digital-to-analog conversion [15], time-to-space con-version [16], and angular multiplexed spectral holograms [17], to check two or more entrieswith one device.

2.A.2. Ultrafast Optical Header Processing

As discussed above, baseband serial labels without preambles may be the best among var-ious label-transmission schemes, considering the scalability of the payload data rate, lowoccupation ratio of the label field, and tolerance of chromatic dispersion. Furthermore, in-formation assigned to different fields in the header may need to be retrieved from eachpacket, such as the time-to-live (TTL) value (number of hops to live), in addition to theaddress information of the label [18]. To retrieve different fields by all-optical, pattern-matching methods, the header processor would require a tremendously large number of


pattern-matchers, making it bulky and expensive. Meanwhile, the often-mentioned draw-back of the conventional electronic system is its high power consumption. However, it isGaAs-based high-speed electronic devices that consume most of the power. In contrast,silicon CMOS devices consume very little power. In addition, the silicon industry is verymature and can provide large-scale processors and memories having high functionality atvery low cost. The only drawback of the CMOS is its limited operating speed. Therefore, ifinterface devices with low power consumption between ultrafast asynchronous packets andCMOS circuits could be created, a breakthrough in highly functional processing of ultra-fast asynchronous optical packets would be achieved. This is the core concept behind ourresearch efforts. Here we describe a novel header processor that can recognize and updateeach field in the baseband serial header of ultrafast asynchronous optical packets withoutpreambles.

Figure1 shows our approach to header processing for ultrafast, asynchronous opticalpackets [19]. The module shown is composed basically of electrical and optical clock-pulsegenerators (ECGs and OCGs, respectively) [20], an all-optical serial-to-parallel converter(SPC) [21, 22], a photonic parallel-to-serial converter (PSC) [23], and a CMOS circuit.The header of the input packet is separated from the payload by the ECG and a 1× 2optical switch and fed into the OCG. The OCG generates a single short optical pulse ac-curately synchronized with the input header. With the optical pulse as a pump pulse, theSPC converts the header from a high-speed serial signal to multiple parallel signals (serial-to-parallel conversion). The parallel optical pulses are then converted into slow electricalpulses with a low-speed photodetector (PD) array and launched into a CMOS processor,where each field is retrieved. Within the CMOS circuit, the TTL field is decremented by1, and the output label and output port are decided. The updated header is output from theprocessor in the form of parallel electrical data and reconstructed into a high-speed, serialoptical header by the PSC with an optical pulse from the OCG. Finally, by simply couplingthe new header and the separated payload that is passed through a fixed delay line, theheader-swapped packet can be formed with the payload remaining in the optical domain.

Old header

PD array

H

1x2SW

HP

H H’

H’

H’P

Pump TriggerECG

New header

Payload

PhotonicPSC

All-opticalSPC

OCG

CMOScircuit

Control signal

Ultrafast asynchronous optical packet

Fig. 1. Optical header processor.

Another often-cited drawback of electronic systems is the long time it takes to findan entry matching an input label. In the standard IP router, the header processing time isindeed fairly long because the entry bank is large. However, in the OPS nodes, since thenumber of entries is small (a few hundred), the CMOS processor can check the input headersimultaneously against all the entries in parallel and in one try by use of an AND gate arraywith a processing time of only a few tens of nanoseconds (a 10-ns delay corresponds toa 2-m length of fiber). The internal clock rate of the CMOS processor, not the processing


time, limits the repetition rate (more than several hundred megahertz) of the input packets.

2.B. Contention Resolution

2.B.1. Comparison of Contention Resolution Methods

Contention resolution methods can be divided into three categories: buffering, deflectionrouting, and wavelength conversion [6]. Buffering, which exploits the time domain, is fun-damental for contention resolution. It is widely used in today’s electronic routers, in whichcontention is usually resolved by a store-and-forward technique that uses silicon RAM.This provides many advantages, including large capacity, long-term storage, random ac-cess at an arbitrary timing, low cost, compactness, reliability, controllability, and low powerconsumption. However, since silicon RAM is slow, processing high-speed optical packetsrequires high-speed, GaAs-based electronic devices at the input and output interfaces of thesilicon RAM. Furthermore, the conventional electronic approach requires a long preambleon the packet, and the packet bit rate is limited by the operating speed of the electroniccomponents, their susceptibility to electromagnetic interference, and their large power con-sumption.

Unfortunately, all-optical RAM does not currently exist. Therefore, the only viabletechnique available for buffering in the optical domain is to use FDLs [24, 25]. Operationis based on strict first-in–first-out queues with fixed delays. FDL buffers provide opticalpaths of various discrete lengths, restricting the packet to either a fixed length or a multipleof it. Moreover, they have almost none of the inherent advantages of silicon RAM. Theyare bulky and expensive and do not provide large capacity, long-term storage, or randomaccess at an arbitrary timing. They also suffer from large insertion loss and accumulationof amplifier noise in the fiber loops. This reduces multihop capability because of degrada-tion of optical signal quality. FDL buffers also require complicated control hardware andalgorithms.

Deflection routing is a technique that resolves contention by exploiting the space do-main [26]. However, the deflected packets suffer from longer delays than with buffering.In addition, this approach may disturb the sequence of packets, could cause routing loops,and it increases the load on the entire network. Therefore, deflection routing without buffersusually results in severe performance penalties in throughput, latency, latency distribution,and probability of packet loss.

The wavelength domain can also be utilized for contention resolution [27]. All contend-ing packets with the same wavelength except for one are converted to unused wavelengthswith tunable-optical-wavelength converters (TOWCs). By spreading the traffic load overseveral wavelength channels, the need for buffering is minimized. However, this requires alarge number of TOWCs because one TOWC is needed for each wavelength channel.

2.B.2. Photonic Random Access Memory

To review, contention resolution based on buffering seems ideal because of increased flex-ibility, high throughput, and low packet loss rates. However, FDL buffers are bulky andrequire very complex control hardware and algorithms. Moreover, it is difficult to use themin an asynchronous network. Meanwhile, we cannot expect an all-optical RAM anytimesoon. Therefore, it seems essential to develop a “photonic RAM” that can read and writeultrafast, asynchronous optical packets freely. We use the term photonic RAM for a RAMthat handles input and output packets in the optical domain whether stored data are electri-cal or optical.

Figure2shows the concept of our photonic RAM [28]. Its configuration is similar to thatof the optical header processor described above. The differences are that the CMOS pro-cessor is replaced by a CMOS RAM and that the entire packet (rather than just the header)


must be processed. To achieve full-packet processing, the optical pulse generated from theOCG is first converted into a low-repetition optical pulse train by an optical pulse traingenerator (PTG). The pulse train period isn times the bit interval of the input packet, andits duration is equal to the packet length. Then the all-optical SPC carries out parallel con-version of the optical packet at everyn-bit interval successively. After optical-to-electricalconversion these data are stored in the silicon CMOS RAM. A stored packet is retrievedby specifying the appropriate address, and trigger signals with a period ofn times the bitinterval of the output packet are input in order to outputn-parallel slow electrical signalssimultaneously from the memory. These signals are then reconstructed into a high-speedoptical packet by the photonic PSC using an optical pulse train. Thus, we can freely readand write ultrafast, asynchronous optical packets of arbitrary length.

Si:RAM

Optical PTG

Trigger for writing

PD array

Trigger for reading

Optical PTG

Output packet

Optical pulse source

All-OpticalSPC

OCG

PhotonicPSC

Ultrafast asynchronous optical packet

HP HP

Fig. 2. Conceptual diagram of the photonic RAM.

The photonic RAM has various advantages over FDL buffers—compactness, randomaccess at arbitrary timing, long-term storage, large capacity, and easy control—and over anall-electrical system that uses GaAs-based, high-speed demultiplexers and multiplexers—high-speed operation at over 40 Gbit/s, low power consumption, asynchronous operation,and compactness. Furthermore, whereas the FDLs provide only buffering, the photonicRAM can also provide header processing, wavelength conversion, 3R regeneration, andpacket compression–decompression.

2.C. Node Architecture

Figure3 shows a conceptual diagram of the proposed node architecture for asynchronousOPS networks. Incoming WDM optical packets to the input ports are separated by wave-length with arrayed-waveguide gratings (AWGs). In the header processor, each packet’sheader is retrieved and updated according to a forwarding table while the payload is main-tained in the optical domain, as shown in Fig.1. At this time some information, such asthe outgoing port, QoS, packet length, and arrival timing are sent to a forwarding con-troller (not shown) for managing the traffic. The packets are processed separately for everywavelength layer, thus allowing the use of small-scale optical space switches. Most of thepackets are then passed to the appropriate outgoing port through the optical switch fab-ric, unless packet contention occurs. When contention occurs, the contending packets arestored in a shared buffer (photonic RAM) as shown in Fig.2, switched to a less-crowdedwavelength layer with the CMOS circuit, and sent into the switch fabric again with propertiming through the PSCs with a different wavelength-pulse source. Spreading the trafficload over several wavelength layers is effective in reducing packet contention probabilityand enhancing network throughput.


IP packets to be added to the OPS network from a connected metropolitan or clientnetwork are retrieved by use of a network layer header and assigned their initial labels.Because of its long and unpredictable nature, this procedure is carried out with an electricalrouter, as shown. The labeled packets are then added to any less-crowded wavelength layerthrough the shared buffer. At this time these packets are easily compressed, for example,by being switched from a SPC for 10-Gbit/s operation to a PSC for 40- or 160-Gbit/soperation. Meanwhile, the packets to be dropped are sent to the shared buffer across theswitch fabric, decompressed to 10 Gbit/s or less, and sent to the electrical router. Suchpacket compression–decompression (PCD) capability [29, 30] is also effective in reducingpacket contention and enhancing network throughput.

SPC

SPCPSC

PSC

SPC

SPC

SPC

PSC

PSC

PSC

Optical Space SwitchHeader Processor

IP packet

λ1

λ2

λ3

λ4

λ1

λ2

λ3

λ4

AWG AWG

AddDrop

RAMSwitch

3R

WC

PCD Add/drop

λ1

λ2

λ3

λ4

λ1

λ2

λ3

λ4

Input port Output portCMOS

Fig. 3. Node architecture.

This node architecture provides various advantages. First, the shared buffer includes 3Rregeneration function. When the optical signal quality is degraded after multiple hops be-cause of insertion loss and amplifier noise, the degraded packets can be restored by passingthem through the shared buffer regardless of packet contention. Furthermore, if all the func-tions required in the node are achieved separately by all-optical means, the entire node willbecome very complex, bulky, and expensive. Our system allows various functions (RAM,3R regeneration, PCD, wavelength conversion, and add–drop) to be integrated, thus reduc-ing the number of optical components and increasing controllability of the entire node.For each wavelength layer, the number of output ports connected from the optical spaceswitch to the shared buffer will be reduced (to many fewer than the number of input ports)when utilizing deflection routing as well as the PCD and engineering traffic among severalwavelength layers, as described above. In addition, to deal easily with a large number ofwavelength layers, the layers can be bundled in groups with a shared buffer for each group.Different data rates–formats can then be assigned to each layer or group, and an additionalwavelength layer or group can be easily added without interrupting node operation.


3. Device Description

3.A. All-Optical Serial-to-Parallel Converter

Figure 4 shows the concept of our all-optical SPC, which utilizes ultrafast, surface-reflection, all-optical switches. An incomingN-bit optical packet is split intoN packetsthat are then coupled intoN different delay lines. Each line has a different amount of de-lay such that thenth line has a delay of(n−1) times the bit separationτ. This creates atime window that encloses allN bits. The optical packets from the fiber array are colli-mated with a two-dimensional microlens array and divided by a polarizing beam splitter(PBS) into two orthogonal, linearly polarized beams whose energies vary according to theinput polarization. The beams are focused to a spot on each optical switch called a LO-TOS (low-temperature-grown, surface-reflection, all-optical switch) [31]. The LOTOS isbasically a saturable absorber that relies on a carrier-induced change in the excitonic ab-sorption of the compressively strained InGaAs−InAlAs multiple quantum wells (MQWs).Ultrafast switching (250 fs) was obtained by growing the MQW region at a low tempera-ture of 200 °C and doping it with Be. Meanwhile, a circularly polarized pump pulse (whichis generated by the OCG described below) is launched into the center of the PBS and di-vided into two linearly polarized pulses having the same amount of energy. After beingconverted into circularly polarized pulses withλ/4 plates, the two pump pulses are also fo-cused to the same spot on each optical switch, and the reflectivity during the time windowis increased. As a result only the pulses within the time window are simultaneously outputin parallel. Handling the two orthogonal components of the signal pulses at two differentswitches makes the SPC insensitive to polarization.

Micro-lens arrayFiber arrayDelay lines

λ/4 plate

All-opt ical switch(LOTOS)

0τ

2τ3τ

Micro-lens arrayFiber arrayDelay lines

λ/4 plate

All-opt ical switch(LOTOS)

0τ

2τ3τ

Fig. 4. Conceptual diagram of all-optical, serial-to-parallel conversion scheme.

The parallel, output optical signals are converted into slow parallel electrical signalswith a PD array. To obtain high contrast for the electrical output signals, an extremely highon/off ratio is required for the optical switch because the residual outputs of the opticalpulses outside the time window accumulate in the slow PD. Therefore, we utilized a spin-polarization scheme to improve the on/off ratios, as described below.

In quantum wells, the spin selection rule indicates that only spin-down (or spin-up) car-riers are excited by a circularly polarized pulse whose wavelength is tuned to the heavy-holeexciton. Under this pumped condition, a linearly polarized signal pulse passing through theMQW changes into a rotated, elliptically polarized pulse. This results because the linearpolarization is composed of right- and left-hand circular polarizations. Only the signalcomponent with the same circular polarization as the pump pulse can see the absorption


saturation and refractive-index change due to spin-dependent, phase space filling, and theoppositely polarized component cannot see the changes at all. On the other hand, the signalpulse shows no polarization change without a pump pulse. Therefore, the pulses outside thetime window can be perfectly cut off by the PBS, while the pulses within the time windowcan pass through the PBS, dramatically improving the switch on/off ratio.

To realize the SP converter described above, it is necessary to achieve precise delays foreachN-split packet. Furthermore, the fiber array must be accurately positioned such thatall beams are focused to one spot. Planar-lightwave-circuit (PLC) technology allows us toput on one chip a splitter, extremely precise delay lines, and two-dimensionally arranged45° mirrors with precise placement. Figure5(a) shows the all-optical SPC module thatutilizes the surface-emitting PLC. The PLC we used here was designed for 16-parallelconversion of 40-Gbit/s optical packets, and is only 32 mm× 73 mm in size, which resultsin a compact SPC module. The 40-Gbit/s, 16-bit incoming optical packets are branched into16 different paths by the PLC and passed through delay lines. The 16 split packets and thepump pulse are output in a two-dimensional array from the PLC surface by the 45° mirrorsand converge to a single point on the LOTOS, resulting in successful parallel conversionwith very high contrast ratios, as shown in Fig.5(b). The pulse energies of the pump andthe 16-split packet input into the LOTOS were about 20 and 0.25 pJ, respectively. Here themodule has only one optical switch, so it does not provide polarization insensitivity. Theall-optical SPC has various advantages: parallel-conversion capability for packet bit ratesup to 1 Tbit/s, scalability of the number of output channels, polarization insensitivity (whenusing two optical switches [32]), low pump power, and compactness. Furthermore, sincethe LOTOS provides an extremely high on/off ratio of more than 30 dB as a result of thespin-polarization scheme, the SPC has high tolerance to input-packet intensity fluctuations.This is an essential feature because packet intensity often changes with the traffic load.

Micro-lens Array

PLC

pump pulse

Optical packet

PBSpump pulse

λ/4 plate

Surface-reflectionall-optical switch

( LOTOS)

MirrorFiber Side view

Hexagonally arranged 45 -

angled mirrors

1.5 mmDelaylines

1:16 splitter

Top view

Parallel output signals

(a) (b-1)

(b-2)

Fig. 5. (a) All-optical, serial-to-parallel converter. (b) Camera images of parallel outputoptical signals for input packets (1) 1001011011010010 and (2) 1000111001110001.

3.B. Electrical–Optical Clock-Pulse Generator

To process asynchronous optical packets, a packet-level synchronization technique is re-quired; that is, a single optical clock pulse (timing pulse) must be created from an inputasynchronous optical packet with accurate timing. Several approaches to packet-level syn-chronization [33, 34] have been demonstrated in the optical domain with a semiconductoroptical amplifier or an optical loop mirror. However, they require preamble bits with a spe-cial format or long preamble bits on an optical packet. In addition, they are polarization


sensitive, and the intensity and polarization of the output pulse vary according to those ofthe input packet. Therefore, it is not possible to utilize these schemes for our SPC system;the SPC requires a pump pulse with a fixed polarization regardless of the input packet polar-ization. Conventional clock extraction based on phase-locked-loop (PLL) methods cannotbe used because these require a long preamble and provide only bit-level synchronization(a sequence of 1’s).

Figure 6 shows our ECG and OCG [20]. The OCG is composed of the ECG and again-switched, distributed-feedback (DFB) diode laser, while the ECG comprises a photo-conductive sample-and-hold (S–H) circuit and an electrical pulse generating circuit. TheS–H circuit consists of a metal–semiconductor–metal (MSM)-PD, a hold capacitorCh, ahigh-electron-mobility-transistor (HEMT) buffer circuit, and a resetting HEMT. With noinput packets, the resetting HEMT short-circuits theCh. When an optical packet arrives,the resetting HEMT is turned off with an electrical signal generated by detecting a fractionof the input power with a slow PD (a few nanoseconds fall time). As a result, the S–Hcircuit is activated and generates a steplike electrical signal by holding the photo-inducedcharge created in the MSM-PD by the leading pulse (which must be a 1) of the input packet(with slight delay). The step signal is then transformed into a single rectangular electricalpulse by the pulse-generating circuit. Here the pulse width is optimized by adjusting theelectrical delay (τ) in the circuit. In the ECG of Fig.1 (and Fig.8; see below) the pulsewidth is set to 600 ps (slightly longer than the length of the header) to separate the headersfrom the packets. In the OCG the output pulse is 150 ps wide and drives the gain-switchedDFB laser to output a 1.538-µm, 10-ps optical pulse. Since the slow PD keeps the resettingHEMT open for the duration of the packet (assuming no long succession of zero bits for afew nanoseconds), the S–H circuit maintains the held voltage. When the packet is finished,the output signal from the slow PD disappears during the guard band between packets, andthe S–H circuit is automatically reset to the initial condition.

DFBLD

electrical pulse

Pulse generating circuit

stepstepInput packet

Reset

MSM-PD

HEMT

buffer

OEIC

Ch

Q

QQτPD

AND

10-ps optical pulse

Time

Pulse compressor

3-ps optical pulse

ECG

Fig. 6. Electrical and optical clock-pulse generator

The ECG–OCG can thus generate a single electrical–optical pulse from an arbitrarilylong, asynchronous optical packet with no preamble bits, regardless of bit rate. Moreover,the optical–electrical–optical conversion enables input polarization and wavelength insen-sitivity. The OCG provides fixed output polarization, constant power, the desired wave-length, and accurate synchronization (within±2 ps when the leading pulse of the packethas energy greater than 0.5 pJ) in spite of 10-dB input power fluctuations. The output opti-cal pulse with a pulse width of approximately 10 ps (applicable to 40-Gbit/s SPC systemsas is) can also be compressed to 3 ps by performing linear chirp compensation with acompact pulse compressor (not used in the following experiments), enabling processing of100-Gbit/s optical packets with the SPC systems.


3.C. Photonic Parallel-to-Serial Converter

Figure7 shows the photonic PSC [23] that performs the reconstruction and generation ofthe output optical packets from the stored data. It consists of four electrical PSCs fabri-cated on one chip, a surface-emitting PLC with a 1:16 splitter and delay lines, and fourelectroabsorption modulators (EAMs). A pulse from an optical pulse source is split intothree pulses: a trigger pulse for reading data, a trigger pulse for the electrical PSCs, and asource pulse for the output packet. The optical trigger pulse is input to read 16-parallel elec-trical data signals from the CMOS processor. These bits are bundled in groups of four witheach group passed to a 4-to-1, electrical, parallel-to-serial converter circuit. The optically-triggered, electrical PSC comprises four MSM-PDs placed at 250-µm intervals along atransmission line, with the MSM-PD biased by the output data from the CMOS proces-sor. In this scheme, p-i-n type PDs cannot be used because they generate an output signaleven when no bias voltage is applied. MSM-PDs are suitable because they have no pho-toresponse in the absence of a bias voltage. However, ordinary MSM-PDs exhibit a longtail because of small-hole mobility. The fall-time problem has been tackled by fabricatingMSM-PDs on low-temperature-grown material or by utilizing narrow electrode spacings.However, these MSM-PDs sacrifice sensitivity and ease of fabrication.

Fig. 7. Photonic parallel-to-serial converter.

In our electrical PSC, simply by adding an input resistorRin and a hold capacitorCh,the fall time of the ordinary MSM-PD can be drastically reduced, to∼ 3 ps [35], withoutsacrificing sensitivity or ease of fabrication. An input electrical signal slowly charges thehold capacitorCh with a time constant ofChRin, while an optical trigger pulse incidenton the MSM-PD rapidly discharges the capacitor with a time constant ofCh (Ron+Rd)without a long tail. HereRon is the switch ON resistance andRd the load resistance. Eachelectrical PSC thus generates a 10-Gbit/s, 4-bit serial electrical signal when the four MSM-PDs are optically triggered in order at 100-ps intervals. This serial electrical signal drivesan EAM to modulate a 10-Gbit/s, 4-bit optical pulse train created by an optical multiplexer.Finally, the modulated optical signals are interleaved with a bit separation of 25 ps, resulting


in the generation of the desired 40-Gbit/s, 16-bit optical packet. The photonic PSC hasseveral advantages: The number of parallel input ports and the operating speed (up to afew hundreds Gbit/s) are scalable as a result of the effective combination of electrical andoptical multiplexing; it generates ultrafast burst optical packets from much slower electricaldata; and it can be driven by a low-cost, CMOS-logic IC with low power consumption.

4. Experimental Demonstrations

4.A. Optical Label Swapper

Figure 8 shows the experimental setup for 16-bit label swapping and 1× 4 self-routing[19]. Figure9 shows photographs of (a) a CMOS processor with an all-optical SPC moduleand (b) a prototype label swapper in which the OCG, SPC, PSC, and CMOS processorare compactly integrated. An input packet stream consisting of two alternating 40-Gbit/s,33-bit packets A (La,0,Pa) and B (Lb,0,Pb) at a packet rate of 42 MHz is created by usingtwo different PLC-based optical multiplexers and 2-ps optical pulses from a fiber laser, asshown in Fig.10(a). L andP represent the 16-bit label and payload, respectively (La =Pa = 1001011011010010 andLb = Pb = 1000111001110001). A guard band of one 0 bitis inserted between the label and payload to allow separation of the label from the inputpacket with a 20-Gbit/s, LiNbO3,1×2 optical switch. As shown in Figs.10(b) and10(c)the input label and payload are separated by a 600-ps-long electrical pulse generated fromthe ECG. The separated label is converted in parallel by the SPC and fed to the CMOS labelprocessor [made with a field-programmable gate array (FPGA)] containing a forwardingtable with many 16-bit address entries and their routing information. The input label ischecked against all of the address entries in one try. The processor then outputs a new labelin the form of 16-parallel, slow electrical signals and 2-channel forwarding-control signalsto drive the LiNbO3, 1×4 optical switches.

CMOScircuit

All-opticalSPC

PhotonicPSC

PD array andlimiting amps

Lb

La’Pa

Lb’Pb

Lb’

Pa

La La’

Pa Pb

Payload

Old label New label

New-label insertion Packet A’

Packet B’

Label swapper Output packets

Pump Source

H

L

H

L

H

L

OCG

La LbPa Pb

Packet A Packet B

40-Gbit/s 33-bit input packets

Fiberlaser

40-Gbit/s 16-bit MUX

2 ps21 MHz

425 ps

(Packet rate: 42 MHz)A

B

La LbPa Pb

Packet A Packet B

40-Gbit/s 33-bit input packets

Fiberlaser

40-Gbit/s 16-bit MUX

2 ps21 MHz

425 ps

(Packet rate: 42 MHz)A

B

2-ch. control

1x4 routing switch

Electrical signal

Optical signal

Electrical signal

Optical signal

ECG

1x2SW

Old-label separation

Fig. 8. Experimental setup for optical label swapping and 1×4 self-routing.

In case (i) of Fig.11, the forwarding table was set to produce new-label signals ofL′a = 1010001010110011 andL′b = 1100111010011000 and control signals of (H, L) and(L, H) for input labelsLa and Lb, respectively. As shown in Figs.10(d) and10(e) the


new labels match the forwarding table instructions, confirming successful operation of theSPC, PSC, and label processor. Figure11 shows the input packet stream, control signals,and output packets, respectively, of the 1×4 switch. As a result of correct control signalgeneration, packetsA′ andB′ were properly routed to ports 2 and 3, respectively. In case (ii),when the forwarding table was rewritten to different settings, the label, control signals, andoutput ports for packetsA′′ andB′′ were properly changed according to the new forwardingtable. The latency (from label input to new label output) of the CMOS processor is less than30 ns. In addition, since the control signals remain constant until a packet with a differentlabel is input and can switch within 3 ns, the label swapper can handle asynchronous opticalpackets of any arbitrary length by attaching a guard time of approximately 5 ns. In the labelswapper shown in Fig.8, one drawback is that the intensity, wavelength, and polarizationof the new label cannot track the change of the input packet because the characteristics ofthe optical pulse output from the OCG are constant. We have recently demonstrated a newtype of label swapper that solves this problem by using the leading pulse as the source pulsefor the new label [36].

CMOSprocessor(FPGA)

LOTOS

PD array

PLC16-ch.outputsignals

…

15 x 8 cm2

2-ch.controlsignals

CMOSprocessor(FPGA)

LOTOS

PD array

PLC16-ch.outputsignals

…

15 x 8 cm2

2-ch.controlsignals

ProcessorCPU

OCGSPC

PSC

(a) (b)

InputOutput26 cm

Fig. 9. Photographs of (a) a CMOS processor with an all-optical SPC module and (b) aprototype of the label swapper.

Time (100 ps/div)

La LbPa Pb

Pa Pb

La Lb

La’ Lb’

La’ Lb’Pa Pb

A B

A’ B’

0 0

0 0

(a)

(e)

(b)

(c)

(d)

Time (100 ps/div)

La LbPa Pb

Pa Pb

La Lb

La’ Lb’

La’ Lb’Pa Pb

A B

A’ B’

0 0

0 0

(a)

(e)

(b)

(c)

(d)

Fig. 10. (a) Input packets. (b) Separated old labels. (c) Separated payloads. (d) Generatednew labels. (e) Output packets with new labels. (0 is a 1-bit guard band.)


(a)

(b)

(c)

Time (10 ns/div)

Port 1

Ch. 1

Ch. 2

A B A B A B A B

A’

B’ B’

A’

A’’A’’

B’’ B’’

(i) (ii)

Port 2

Port 3

Port 4

(a)

(b)

(c)

Time (10 ns/div)

Port 1

Ch. 1

Ch. 2

A B A B A B A B

A’

B’ B’

A’

A’’A’’

B’’ B’’

(i) (ii)

Port 2

Port 3

Port 4

Fig. 11. Experimental results. (a) Input packet stream. (b) Output 2-channel control signals.(c) Output packet stream from each port.

4.B. Photonic Random Access Memory

Since no optical PTG has yet been constructed, we are not able to completely handlelong packets at present. However, with the prototype shown in Fig.9(b) (in which theRAM function in the FPGA was utilized), we experimentally confirm the basic opera-tion of the photonic RAM by processing 40-Gbit/s, 16-bit optical packets without us-ing the PTG, as shown in Fig.12. Figure13(a) shows the input packet stream at a 42-MHz rate with two different 40-Gbit/s, 16-bit optical packets A(1001011011010010) andB(1000111001110001). Once the optical packets are stored in the memory, the data arepreserved unless erased or overwritten. Therefore, the stored data can be read freely byspecifying the appropriate read address.

40-Gbit/s 16-bit optical packet

All-opticalSPC

CMOSRAM

PhotonicPSC

Trigger for writing

PD arrayTrigger for reading

Computer

Fiberlaser

Sampling oscilloscope

OCG

21-MHz trigger(to oscilloscope)

Multiplexer A

Multiplexer B

A

B

21-MHz rep. rate

21-MHz rep. rateFiber laser

40-Gbit/s 16-bit output packet

PDPD

Photonic RAM

Fig. 12. Experimental setup for the photonic RAM.

Figures13(b) and13(c) show the output packet waveforms. When all addresses werespecified, optical packets A and B were output in turn, as shown in Fig.13(b). Meanwhile,


by specifying the even addresses, only packet A was obtained, as shown in Fig.13(c). Onlypacket B was output when specifying the odd addresses (not shown). The latency and ca-pacity of the CMOS RAM used here are approximately 50 ns and 112 Kbyte, respectively.With both the SPC and PSC potentially having several hundred Gbit/s of bandwidth, theentire photonic RAM will be able to handle ultrafast, asynchronous optical packets of over100 Gbit/s once the operating speed of the CMOS RAM increases. With the same con-figuration, we have also demonstrated optical packet compression (40 Gbit/s to 80 Gbit/s)and decompression (40 Gbit/s to 10 Gbit/s) for 32-bit, asynchronous optical packets [37].Furthermore, by use of multiple components, a time-domain add–drop multiplexer and a4× 4 packet switch that have label processing, buffering, and 3R regeneration functionshave also been demonstrated [38].

(a)

(b)

(c)

Time (10 ns/div)

Packet A

Time (100 ps/div)

Packet A

Time (100 ps/div) Time (100 ps/div)

Packet B

Time (100 ps/div)

Packet B

Packet B

Time (100 ps/div)

Packet B

Time (100 ps/div)

Packet A

Time (100 ps/div)

Packet A

Time (100 ps/div)

Packet A

Time (100 ps/div)

Fig. 13. Experimental results. (a) Input packets A and B. (b) Output packets when alladdresses and (c) only even addresses were specified, respectively.

5. Conclusions

Asynchronous, optical, packet-switched networks are the most attractive networks whenconsidering flexibility, scalability, and bandwidth utilization efficiency. However, the tech-nical barriers to implementing them are still very high. In this paper, we discussed the var-ious problems and recent progress in optical packet processing. We described the conceptand advantages of our hybrid optical–electrical systems that are based on an all-opticalserial-to-parallel converter, an optical clock-pulse generator, and a photonic parallel-to-serial converter. We also reviewed our recent work on an optical label swapper and aphotonic RAM for asynchronous 40-Gbit/s, 16-bit optical packets. In our systems siliconCMOS processors play a very important role, and this enables the integration of variouscomplex functions for processing optical packets. Our current view is that the best wayto realize future OPS networks may be the hybrid optical–electrical approach in whichoptimal use of both optics and electronics is made. However, recently the developmentof various novel optical devices and hybrid or monolithically integrated devices has seensteady progress. By combining these optical technologies within a clever node architecture,transparent nodes should be possible in the future.


References and Links[1] K-I. Sato, N. Yamanaka, Y. Takigawa, M. Koga, S. Okamoto, K. Shiomoto, E. Oki, and W.

Imajuku, “GMPLS-based photonic multilayer router (Hikari router) architecture: An overviewof traffic engineering and signaling technology,” IEEE Commun. Mag.40, 96–101 (2002).

[2] A. Banerjee, J. Drake, J. P. Lang, and B. Turner, “Generalized multiprotocol label switching:an overview of routing and management enhancements,” IEEE Commun. Mag.39, 144–150(2001).

[3] M. Koga, T. Morioka, and Y. Miyamoto, “Next generation optical communication technologiesfor realizing bandwidth networking capability,” Opt. Rev.11, 87–97 (2004).

[4] K. Kitayama and M. Murata, “Versatile optical code-based MPLS for circuit, burst, and packetswitching,” J. Lightwave Technol.21, 2753–2764 (2003).

[5] D. J. Blumenthal, J. E. Bowers, L. Rau, H.-F. Chou, S. Rangarajan, W. Wang, and H. N. Poulsen,“Optical signal processing for optical packet switching networks,” IEEE Commun. Mag.41,S23–S29 (2003).

[6] S. Yao, B. Mukherjee, and S. Dixit, “Advances in photonic packet switching: an overview,”IEEE Commun. Mag.38, 84–94 (2000).

[7] G. I. Papadimitriou, C. Papazoglou, and A. S. Pomportsis, “Optical switching: switch fabrics,techniques, and architecture,” J. Lightwave Technol.21, 384–405 (2003).

[8] T. Sakamoto, A. Okada, M. Hirayama, Y. Sakai, O. Moriwaki, I. Ogawa, R. Sato, K. Noguchi,and M. Matsuoka, “Optical packet synchronizer using wavelength and space switching,” IEEEPhoton. Technol. Lett.14, 1360–1362 (2002).

[9] A. E. Willner, D. Gurkan, A. B. Sahin, J. E. McGeehan, and M. C. Hauer, “All-optical addressrecognition for optically-assisted routing in next-generation optical networks,” IEEE Commun.Mag.41, 38–44 (2003).

[10] A. Takada and J. H. Park, “Architecture of ultrafast optical packet switching ring network,” J.Lightwave Technol.20, 2306–2315 (2002).

[11] T. Yasui, R. Takahashi, and H. Suzuki, “Ultrafast all-optical pattern matching using differentialspin excitation,”European Conference on Optical Communications (ECOC2003)(IEEE, NewYork, 2003), Vol. 4, pp. 994–995.

[12] O. Moriwaki, T. Sakamoto, A. Okada, and M. Matsuoka, “Demonstration of optical label pro-cessing with timing pulse generator,” Electron. Lett.39, 730–731 (2003).

[13] K. Chan, F. Tong, C. K. Chan, L. K. Chen, and W. Hung, “An all-optical packet header recogni-tion scheme for self-routing packet networks,”Optical Fiber Communication, Vol. 70 of 2002OSA Technical Digest Series (Optical Society of America, Washington, D. C., 2002), pp. 284–285.

[14] K-H. Park and T. Mizumoto, “A packet header recognition assigning the position of a signal inthe time axis and its application to all-optical self-routing,” J. Lightwave Technol.19, 1076–1084 (2001).

[15] H. Uenohara, T. Seki, and K. Kobayashi, “High-speed optical packet switch with an opticaldigital-to-analog conversion-type header processor,” Opt. Rev.11, 113–118 (2004).

[16] H. Furukawa, T. Konishi, Y. Oshita, W. Yu, K. Itoh, and Y. Ichioka, “Design of header recogni-tion filter for binary phase shift keying in header recognition unit using time-space conversion,”Opt. Rev.11, 119–125 (2004).

[17] N. Kawakami, K. Shimizu, N. Wada, F. Kubota, and K. Kodate, “All-optical holographic labelprocessing for photonic packet switching,” Opt. Rev.11, 126–131 (2004).

[18] J. E. McGeehan, S. Kumar, D. Gurkan, S. M. R. M. Nezam, A. E. Willner, K. R. Parameswaran,M. M. Fejer, J. Bannister, and J. D. Touch, “All-optical decrementing of packet’s time-to-live(TTL) field and subsequent dropping of a zero-TTL packet,” J. Lightwave Technol.21, 2746–2752 (2003).

[19] T. Nakahara, R. Takahashi, H. Takenouchi, K. Takahata, and H. Suzuki, “Time-domain 16-bitlabel swapping and self-routing of 40-Gbit/s optical packets,” IEEE Photon. Technol. Lett.16,2153–2155 (2002).

[20] T. Nakahara, R. Takahashi, H. Takenouchi, and H. Suzuki, “Optical single-clock-pulse generatorusing a photoconductive sample-and-hold circuit for processing ultrafast asynchronous opticalpackets,” IEEE Photon. Technol. Lett.14, 1623–1625 (2002).


[21] R. Takahashi, T. Nakahara, H. Takenouchi, T. Yasui, and H. Suzuki, “Ultrafast all-optical serial-to-parallel conversion and its application to optical label processing,” Opt. Rev.11, 98–105(2004).

[22] R. Takahashi and H. Suzuki, “1-Tb/s, 16-b all-optical serial-to-parallel conversion using asurface-reflection optical switch,” IEEE Photon. Technol. Lett.15, 287–289 (2003).

[23] K. Takahata, H. Takenouchi, T. Nakahara, R. Takahashi, and H. Suzuki, “Electrical parallel-to-serial converter using MSM-PDs for optical communication networks,” inPhotonic IntegratedSystems, L. A. Eldada, A. R. Pirich, P. L. Repak, R. T. Chen, and J. C. Chon, eds., Proc. SPIE4998, 76–84 (2003).

[24] D. K. Hunter, M. C. Chia, and I. Andnovic, “Buffering in optical packet switches,” J. LightwaveTechnol.16, 2081–2094 (1998).

[25] T. Sakamoto, A. Okada, O. Moriwaki, M. Matsuoka, and K. Kikuchi, “Performance analysis ofvariable optical delay circuit using highly nonlinear fiber parametric wavelength converters,” J.Lightwave Technol.22, 874–881 (2004).

[26] M. Baresi, S. Bregni, A. Pattavina, and G. Vegetti, “Deflection routing effectiveness in full-optical IP packet switching networks,”IEEE International Conference on Communications,Vol. 2 (IEEE, 2003), pp. 1360–1364.

[27] S. Rangarajan, Z. Hu, L. Rau, and D. J. Blumenthal, “All-optical contention resolution withwavelength conversion for asynchronous variable-length 40 Gb/s optical packets,” IEEE Pho-ton. Technol. Lett.16, 689–691 (2004).

[28] R. Takahashi, T. Nakahara, K. Takahata, H. Takenouchi, T. Yasui, N. Kondo, and H. Suzuki,“Photonic random access memory for 40-Gb/s 16-b burst optical packets,” IEEE Photon. Tech-nol. Lett.16, 1185–1187 (2004).

[29] K. Seppanen, “Shared OTDM packet compressor and decompressor,” Electron. Lett.36, 2090–2092 (2000).

[30] H. Toda, F. Nakada, M. Suzuki, and A. Hasegawa, “An optical packet compressor based on afiber delay loop,” IEEE Photon. Technol. Lett.12, 708–710 (2000).

[31] R. Takahashi, “Low-temperature-grown surface-reflection all-optical switch (LOTOS),” Opt.Quantum Electron.33, 999–1017 (2001).

[32] R. Takahashi, T. Yasui, N. Kondo, and H. Suzuki, “100-Gb/s 16-bit polarization-insensitiveoptical serial/parallel converter using differential spin excitation,”European Conference on Op-tical Communications (ECOC2004), (IEEE, New York, 2004), Vol. 1, pp. 48–49.

[33] M. C. Cardakli and A. E. Willner, “Synchronization of a network element for optical packetswitching using optical correlators and wavelength shifting,” IEEE Photon. Technol. Lett.14,1375–1377 (2002).

[34] K. Vlachos, N. Pleros, C. Bintjas, G. Theophilopoulos, and H. Avramopoulos, “Ultrafast time-domain technology and its application in all-optical signal processing,” J. Lightwave Technol.21, 1857–1868 (2003).

[35] K. Takahata, R. Takahashi, T. Nakahara, H. Takenouchi, and H. Suzuki,” Ultrashort electricalpulse generation using a normal MSM-PD,”IEEE Conference on Lasers and Electro-opticsEurope 2003, CJ3-2 (IEEE, 2003).

[36] T. Nakahara, H. Takenouchi, R. Takahashi, K. Takahata, and H. Suzuki, “32-bit label swappingof 40-Gbit/s burst optical packets with intensity tracking of input label,”European Conferenceon Optical Communications (ECOC2004), (IEEE, New York, 2004), Vol. 4, pp. 938–939.

[37] H. Tackenouchi, K. Takahata, T. Nakahara, R. Takahashi, and H. Suzuki, “40-Gbit/s 32-bitoptical packet compressor/decompressor based on an optoelectronic memory,” IEEE Photon.Technol. Lett.16, 1751–1753 (2002).

[38] K. Takahata, R. Takahashi, T. Nakahara, H. Takenouchi, and H. Suzuki, “Photonic packetrouter for 40-Gbit/s 16-bit burst optical packets,”Optical Fiber Communications Conference(OFC2004), Vol. 95 of OSA Trends in Optics and Photonics Series, TuQ-3 (Optical Society ofAmerica, Washington, D. C., 2004).


ultrafast optoelectronic packet processing for asynchronous, optical-packet-switched networks...

Documents