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Download UConn CSE 241 1 CSE241: Instruction Level Architecture Base CPU/Memory Architecture Registers Fetch-Execute Cycle Instructions Addressing Modes

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  • UConn CSE 241 *CSE241: Instruction Level ArchitectureBase CPU/Memory ArchitectureRegistersFetch-Execute CycleInstructionsAddressing Modes

    UConn CSE 241 *

  • UConn CSE 241 *Basic CPU Architecture

    CPUControl Path-instruction fetchand executionsequencingData Path-user registersand ALUMARMDRMemory Data BusMemory Address Bus

    UConn CSE 241 *

  • UConn CSE 241 *CPU DivisionsControl Pathresponsible for instruction fetch and execution sequencingresponsible for operand fetchresponsible for saving resultsData Pathcontains user registerscontains ALUexecutes instructions

    UConn CSE 241 *

  • UConn CSE 241 *Control Path RegistersPC Program Counterpoints to the next instruction to be executedthus, it contains a memory addressMAR Memory Address Registercontains the address of the memory location for the current memory operationMDR Memory Data Registercontains the data to be written to or the data read from the memory location in the current memory operationIRInstruction Registercontains the current instruction being executed

    UConn CSE 241 *

  • UConn CSE 241 *Memory OrganizationData is stored as sequences of bits--basic grouping is the byte -- 8 bits

    Bytes are grouped into words--words may be 2 (older), 4 (current) or 8+ (modern)bytes long

    The byte is the basic unit for addressing memory.However, our life will be simplified if we adopt the wordas the basic unit.The size of memory (almost always in bytes) is usually given byS = 2p, where p = word size of machine(but this may be machine dependent)

    UConn CSE 241 *

  • UConn CSE 241 *Memory OrganizationWord size = 16, memory size = 65536 (64KB)Word size = 20, memory size = 1048576 (1MB)Word size = 32, memory size = 4294967296 (4GB)Word size = 64, memory size = 1.844674407x1019this is ? bytes?

    UConn CSE 241 *

  • UConn CSE 241 *Memory OrganizationMARMDR512Recall:MAR contains the address of thememory location addressed

    MDR either contains data to bewritten to that address, or dataread from that addressMemoryis viewedas an arrayof bytes.

    Addressesstart at 0 andincrease by 1up to maximumsize01

    UConn CSE 241 *

  • UConn CSE 241 *Memory operationsMemory ReadPlace address of memory location to be read into MARIssue a Memory_Read command to memoryData read from memory is placed into MDR automatically (by control logic)Memory WritePlace address of memory location to be written to into MARPlace data to be written into MDRIssue Memory_Write command to memoryData in MDR is written to memory automatically (by control logic)

    UConn CSE 241 *

  • UConn CSE 241 *Fetch-Execute CycleBasic machine cycle; repeats indefinitelyDo until haltedFetch instruction to be executed(Decode instruction)Fetch operandsPoint PC to next instruction to be executedExecute instructionSave result operand

    UConn CSE 241 *

  • UConn CSE 241 *Instruction TypesThere are 4 basic instruction types (3 basic)Data movement instructionsthese move but do not alter dataALU instructionsthese alter (operate upon) dataFlow of Control instructionsthese sequence instructionsInput-Output instructionsthese transfer data to and from the real worldnote that these may get classed as Data movement

    UConn CSE 241 *

  • UConn CSE 241 *OperandsOperands are the entities operated upon by instructionsOperands may be stored in memoryOperands may be stored in CPU registersBoth memory and CPU registers have addressesSpecifying the address of an operand in an instruction is called an addressing mode

    UConn CSE 241 *

  • UConn CSE 241 *Instruction Types by Function (Examples)data movementmov a,b a = b;ALUadd a,b a = a + b;sequencingjsr label jump to the subroutine which starts at labelI/Oin r5, portread from io port port to register 5

    UConn CSE 241 *

  • UConn CSE 241 *Instruction Types by OperandsAs well as being distinguished by type, instructions can be distinguished by the number of operands they haveTypically, instructions may have 3,2,1 or 0 operands3-operand instructions are almost always instructions which implement binary operations e.g.,adda,b,c a = b + c2-operand instructions are like 3-operand instructions, but one operand serves as both a source and a destination, e.g.adda,b a = a+b1-operand instructions are instructions which only require one operandclra a = 00-operand instructions do not operate on operands e.g.hlthalt the computer

    UConn CSE 241 *

  • UConn CSE 241 *Source and Destination OperandsAn operand is called a source operand ifit appears on the right-hand side of an expressione.g., add a,b meaning a = a + bb is a source operand, as is a

    An operand is called a destination operand ifit appears on the left-hand side of an expressione.g.,add a,b meaning a = a + ba is a destination operandSome operands may be both source and destination operands (a above)

    UConn CSE 241 *

  • UConn CSE 241 *Data encodingData (strings of bits) in a machine may representunsigned integerssigned integersinstructionscharacter datafloating point dataabstract data etc.addressesWhat any particular string of bits means depends on how that string of bits gets interpretedThe same string of bits is interpreted as an address by the MAR, an instruction by the IR, or a floating-point number by the FPU.

    UConn CSE 241 *

  • UConn CSE 241 *Instruction EncodingAn instruction must encodethe instruction itselfthe (or a partial) address of its operand(s)the addressing mode used to generate the address of its operand(s)Instructions can be encoded ina variable number of bytesa constant number of bytesthis is machine-dependent

    UConn CSE 241 *

  • UConn CSE 241 *Instruction-level architecturethe architecture of the machine at this level consists ofthe instructions and addressing modesthe user registersthis is the level of the machine that an assembly-language programmer sees.It is the first obvious place where different machines can be seen to clearly differCompare this to the application program architecture, as seen by (say) a C++ programmer; how different is a Pentium to a PowerPC at this level (discount the different OSs)

    UConn CSE 241 *

  • UConn CSE 241 *Basic Addressing ModesThere are five basic addressing modesImmediate addressingthe instruction contains the operand itselfRegister addressingthe instruction refers to a register which contains the operandDirect addressingthe instruction contains the address of the operandIndirect addressingthe instruction contains the address of the address of the operandIndexed addressingthe instruction contains a value to be added to an index register to give the address of the operand

    UConn CSE 241 *

  • UConn CSE 241 *Simple ModelSuppose we consider only 1-operand instructions

    Suppose each instruction occupies 2 32-bit words

    The first word identifies the instruction (and addressing mode)

    The second word gives the operand address

    UConn CSE 241 *

  • UConn CSE 241 *Direct AddressingBefore After

    UConn CSE 241 *

  • UConn CSE 241 *Indirect Addressingclear3447869634478696value in secondword is indirect addressof operand; value inlocation 344786 is addressof operand344786memory9696-1820Before After

    UConn CSE 241 *

  • UConn CSE 241 *Indexed AddressingBefore After

    UConn CSE 241 *

  • UConn CSE 241 *Mixed modes? Indexed indirect?It is possible to mix addressing modesWe could define an indexed indirectBut note that we could have two ways of implementing thisindexing before indirectionindexing after indirection

    UConn CSE 241 *

  • UConn CSE 241 *Indirect Indexed mode (preindexing)clear indexed R3100R35129696+=61261261296323960this is the address of theaddress of the operandBefore After

    UConn CSE 241 *

  • UConn CSE 241 *Indirect Indexed Mode (postindexing)clear indexed R3100R3512+=1024this is the address of the operand10010245120Before After

    UConn CSE 241 *