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Matsuzawa & Okada Lab. Two-Stage Band-Selectable CMOS Power Amplifier JeeYoung Hong , Daisuke Imanishi, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan 2010/09/13

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Matsuzawa& Okada Lab.

Two-Stage Band-SelectableCMOS Power Amplifier

JeeYoung Hong, Daisuke Imanishi, Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

2010/09/13

1

Matsuzawa& Okada Lab.

Contents

Introduction

PA design

Measurement results

Conclusion

2010/09/13

2

Matsuzawa& Okada Lab.

Single chip transceiver

Low costSmall area

Conventional

Single chip

Single chip transceiver is demanded because of its low cost and downsizing.

2010/09/13

3

Matsuzawa& Okada Lab.

Various wireless applications

Various wireless communication standards

DTV

RFID

cell-phone

UWB

cell-phone

0 2 4 6Frequency [GHz]

WLAN

WiMAX

WLAN

WiMAX

GPS Bluetooth

1 3 5

A broad band device (PA) is necessary to support various wireless applications.

2010/09/13

4

Matsuzawa& Okada Lab.

Conventional wideband PADistributed power amplifier

Wideband input / output matching→ Possibility of intermodulation

Lack of the optimum impedance matching→ Insufficient output power

Many inductor→ Large area2010/09/13

5

Matsuzawa& Okada Lab.

Target of proposed PA

Large output power

– High supply voltage

– Differential topology

– 2-stage configuration

– Transformer

Band-selection

– Change of impedance matching

2010/09/13

6

Matsuzawa& Okada Lab.

Schematic

2:1

Band2

To 2nd stage

VB1 VB1

GND or VB2

GND or 1.8V

To 2nd stage

VDD = 3.3V

L1C1 C1

RFin+ RFin-

Band1

1st stage

320/0.18

640/0.35

Class-A bias(1st stage), Class-AB bias(2nd stage)

Differential topology forachieving 3dB larger Pout

2010/09/13

7

Matsuzawa& Okada Lab.

Consideration for voltage stress

Cascode topology with thick gate-oxide transistor

Self-biased cascode: technique that allows RF swings at the common gate transistor. [1] T. Sowlati et al., JSSC 2003.

Reduction of voltage vgd

Prevention of transistor’s entering to triode region

Volta

ge

Vb4

VDD

Cgd

Cbypass

vg

vd

vs

VDD=3.3V

If Cgs is neglected,

dgdbypass

gdg v

CCC

v+

=

[ Conceptual diagram of voltage waveforms ]2010/09/13

8

Matsuzawa& Okada Lab.

Interstage matching

To get a sufficient gain practically→ a 2-stage configuration

To transfer power from the 1st stage to the 2nd stage→ a complex conjugate impedance matching

2010/09/13

9

Matsuzawa& Okada Lab.

Change of impedance matchingIf L-shaped matching which consists of L1&C1 is effective

ON

Current flows through only the transistors to use

Switching which consists of inductor and capacitor is realized in low-loss.

2010/09/13

10

Matsuzawa& Okada Lab.

Transformer

out

DD

sat Z

V

P

2

2 ⎟⎠⎞

⎜⎝⎛

=

Relation between Psat & Zout

Theoretical maximum output power Psat

)50412(

2332

)41(2

22

22

××

⎟⎠⎞

⎜⎝⎛ ×

⎟⎠⎞

⎜⎝⎛ ×

=

.

out

DD

sat Z

V

P• Turn ratio=2:1• Zout (50Ω)→ ¼ Zout(12.5Ω)

]dBm[4.29]W[8712.0 ==

2010/09/13

11

Matsuzawa& Okada Lab.

Transformer

Measurement and simulation results agree with each other.

-10

-8

-6

-4

-2

0

0 1 2 3 4 5Frequency [GHz]

Max

imum

Ava

ilabl

e G

ain

[dB

]

Sim.Meas.

-180

-120

-60

0

60

120

180

0 2 4 6 8 10Frequency [GHz]

Phas

e [d

egre

e]

Phase(S31) meas. Phase(S32) meas.Phase(S31) sim. Phase(S32) sim.

Coupling coefficient = 0.7Maximum Available Gain(MAG) = -1.05 dBConversion efficiency= =78.5 %10010 10 ×)-1.05dB(

2010/09/13

12

Matsuzawa& Okada Lab.

Chip micrographTSMC 0.18µm CMOS process

Transformer1:2

2ndstage

RF in+

RF in-

RF out

1.60mm

1.18mm

DC pad

DC pad

2010/09/13

13

Matsuzawa& Okada Lab.

S-parameter measurement result

0

5

10

15

20

25

30

35

0 1 2 3 4 5 6Frequency [GHz]

S21 [

dB]

Sim.Meas.

Measurement results are roughly in accordance with simulation results

2010/09/13

14

Matsuzawa& Okada Lab.

Measuring systemLarge signal measurement setup

• Input and output losses are measured separately, and are calibrated from results.

2010/09/13

15

Matsuzawa& Okada Lab.

Large signal measurement resultBand2 at 4.6GHzBand1 at 2.6GHz

-20

-10

0

10

20

30

-20 -10 0 10 20Pin [dBm]

Pout

[dB

m],

Gai

n[dB

]

0

10

20

30

40

50

PAE

[%]

PoutGainPAE

-20

-10

0

10

20

30

-30 -20 -10 0 10Pin [dBm]

Pout

[dB

m],

Gai

n[dB

]

0

10

20

30

40

50

PAE

[%]

PoutGainPAE

P1dB = 24.4 dBmPsat = 25.4 dBmPAEpeak = 20.9 %

P1dB = 24.7 dBmPsat = 27.1 dBmPAEpeak = 30.5 %

2010/09/13

16

Matsuzawa& Okada Lab.

Large signal measurement result

20

22

24

26

28

30

32

34

2 3 4 5 6Frequency [GHz]

Pou

t[d

Bm

]

3

7

11

15

19

23

27

31

35

PAE p

eak

[%]

Band 1

Band 2

PsatP1dBPAEpeak

• P1dB ≧ 21dBm• Psat ≧ 25dBm• PAEpeak ≧ 15%

2010/09/13

17

Matsuzawa& Okada Lab.

Comparison of CMOS PAs

[1] [2] [3] This workTechnology 0. 13 µm CMOS process 0.18 µm CMOS process

VDD [V] 1.5 1.5 3.3 3.3Frequency

[GHz]0.5~5.0 2.4/3.5 2.1~6.0 2.2~3.4,

4.2~5.4P1dB [dBm] 10~17 - 15~18 21~25Psat [dBm] 14~21 19 18~22 25~27

PAEpeak [%] *3~16 43 9~17 15~30Area [mm2] 3.6 1.3 0.97 1.89

* DE: Drain Efficiency

[1] H. Roderick, et al., “A 0.13µm CMOS Power Amplifier with Ultra-Wide Instantaneous Bandwidth for Imaging Applications,” IEEE ISSCC Dig. Tech. Papers, pp. 374-375, Feb. 2009

[2] M Ghajar, et al., “Concurrent Dual Band 2.4/3.5 GHz Fully Integrated Power Amplifier in 0.13µm CMOS Technology,” IEEE European Microw. Conf., pp. 1728-1731, Sep. 2009

[3] D.Imanishi, et al., “A 2-6 GHz Fully Integrated Tunable CMOS Power Amplifier for Multi-Standard Transmitters,” IEEE Asia and South Pacific Design Automation Conference, pp. 351-352, Feb. 2010

2010/09/13

18

Matsuzawa& Okada Lab.

Conclusion

2-stage band-selectable CMOS PA with high PAE

Circuit design

– Using TSMC 0.18µm CMOS process

– Switching of the inter-stage matching to change the frequency

– Use of 2-stage configuration & differential topology& transformer to obtain high PAE

Results : PA with Small size and High performance

– Frequency : 2.2 ~ 3.4, 4.2 ~ 5.4 GHz

– P1dB = 21~25dBm, Psat = 25~27dBm, PAEpeak = 15~30%

2010/09/13