CHAPTER 1

INTRODUCTION

1.1 HARMONICS

Presence of harmonics in power system causes various problems; especially the

low frequency harmonics reduce the overall efficiency of the system to a greater extent.

Fourier transformation is applied in harmonic analysis. Any periodic waveform can be

shown to be the super position of a fundamental and a set of harmonic components. By

applying Fourier transformation, magnitude of these components can be known. The

frequency of each harmonic component is an integral multiple of its fundamental.

Fig 1.1 Fourier series representation of a distorted waveform

Normally to eliminate the harmonics, filters are used. When the order of harmonics

decreases, size of the filter increases. When size of the filter increases, it occupies more

space and sometimes it needs cooling system and also it becomes costly. So it is important

to eliminate the low frequency harmonics. There are several methods to indicate the

quantity of harmonics content. The most widely used measure is the total harmonic

distortion (THD), which is defined in terms of the amplitudes of the harmonics, M h. THD

1

50 Hz(h = 1)

150 Hz(h = 3)

250 Hz(h = 5)

350 Hz(h = 7)

450 Hz(h = 9)550 Hz(h = 11)

650 Hz(h = 13)

is a measure of the effective value of the harmonic components of a distorted waveform.

That is, it is the potential heating value of the harmonics relative to the fundamental.

(1.1)

where Mh is the rms value of harmonic component h of the quantity M.

1.2 INVERTER

Dc-to-ac converters are known as inverters. The function of an inverter is to change

a dc input voltage to a symmetric output voltage of desired magnitude and frequency. The

output voltage waveforms of ideal inverters should be sinusoidal. However the waveforms

of practical inverters are non-sinusoidal and contain certain harmonics. Generally the

inverters can be classified into two types,

1) Voltage source inverters

2) Current source inverters.

Multi-level inverter falls under the category of voltage source inverter.

1.3 CONVENTIONAL TWO-LEVEL AND THREE-LEVEL VOLTAGE SOURCE

INVERTER

A half-bridge is the simplest topology, which is used to produce a two-level square

wave output waveform. A center-tapped voltage source supply is needed in such a

topology. It may be possible to use a simple supply with two-well matched capacitors in

series to provide the center tap. The full-bridge topology is used to synthesize a three level

square-wave output waveform. The half-bridge and full-bridge configurations of the

single-phase voltage-source inverter are shown in Fig. 1.2 and 1.3 respectively.

In a single-phase half-bridge inverter, only two switches are needed. To avoid

short-through fault, both switches are never turned on at the same time. S+ is turned on and

S- is turned off to give a load voltage, vo in Fig. 1.2 of +vi/2. To complete one cycle, S+ is

turned off and S- is turned on to give a load voltage of –vi/2.

2

Fig 1.2 Half-Bridge configuration

In full-bridge configuration, turning on S1+ and S2- and turning off S2+ and S1-

give a voltage of vi between point A and B (vo), in Fig. 1.3, while turning off S1+ and S2-

and turning on S2+ and S1- give a voltage of -vi. To generate zero level in a full bridge

inverter, the combination can be S1+ and S2+ ON while S1- and S2- OFF or vice verse.

Note that S1+ and S1-should not be closed at the same time, nor should S2+ and S2-.

Otherwise, a short circuit would exist across the source.

Fig 1.3 Full-Bridge configuration

The output waveforms of half-bridge and full-bridge of single-phase voltage source

inverter are shown in fig 1.4 and 1.5 respectively.

Fig 1.4 Output waveform of half-bridge configuration

3

Fig 1.5 Output waveform of full-bridge configuration

1.4 MULTI-LEVEL VOLTAGE SOURCE INVERTER

Fig 1.7 Schematic of multi-level inverter by a switch

The general structure of the multi-level inverter is to synthesize a near sinusoidal

waveform from several levels of dc voltages. As the number of levels increases, the

synthesized output waveform has more steps, which produces a staircase wave that

approaches a desired waveform. Also, as more steps are added to the waveform, the

harmonic distortion of the output waveform decreases.

Fig 1.8 Typical output voltage of a three-level multilevel inverter

4

1.5 CASCADED MULTI-LEVEL INVERTER

A cascaded multilevel inverter consists of a series of H-Bridge (single-phase, full-

bridge) inverter units. The general function of this multilevel inverter is to synthesize a

desired voltage from several separate dc sources (SDCSs), which may be obtained from

batteries, fuel cells, or solar cells. Fig 1.8 shows the basic structure of a single-phase

cascaded inverter with SDCSs. Each SDCS is connected to an H-Bridge inverter. The ac

terminal voltages of different level inverters are connected as series.

Fig 1.9 Single-phase multilevel cascaded H-bridge inverter

1.5.1 Features of Cascaded Inverter

The main features are as follows:

The cascaded inverters need separate dc sources. The structure of separate dc

sources is well suited for various renewable energy sources such as fuel cell,

photovoltaic and biomass.

It requires least number of components relatively.

5

CHAPTER 2

CONFIGURATION AND OPERATIONAL PRINCIPLE OF

PROPOSED INVERTER

2.1 CIRCUIT CONFIGURATION

Fig 2.1 Typical two-level inverter

A typical two-level H-Bridge cascaded inverter is shown in the above fig 2.1.

It has two separate voltage sources V1 & V2 and eight power electronic switches. The

desired output waveform as shown in the fig 2.2 can be produced by correctly switching on

and off the appropriate switches at correct instants.

2.2 OPERATION

This circuit can produce five different levels of output voltage. By modulating the

switches correctly we can produce a stepped sine waveform as shown in the fig 2.2. The

output voltage contains +V, +2V, 0, -V & -2V voltage levels.

To produce +V, we can either use V1 as voltage source or V2 as voltage source. If

V1 is used, switches S1S4S5S6 or S1S4S7S8 should be closed. If V2 is used as voltage

source, switches S1S2S5S8 or S3S4S5S8 should be closed.

6

Fig 2.2 Output waveform

To produce +2V, both the voltage sources should be connected in series. So

switches S1S4S5S8 are closed.

To produce 0V, the load should be short-circuited. We have four switching options

to short the load. Closing of S1S2S5S6 or S1S2S7S8 or S3S4S5S6 or S3S4S7S8 switches

short circuit the load.

To produce -V, we can either use V1 as voltage source or V2 as voltage source. If

V1 is used, switches S2S3S5S6 or S2S3S7S8 should be closed. If V2 is used as voltage

source, switches S1S2S6S7 or S3S4S6S7 should be closed.

To produce -2V, both the voltage sources should be connected in series. So

switches S2S3S6S7 are closed.

The switching sequences must be selected in such a way that both the sources are

equally utilized and also all the eight devices are equally used.

7

CHAPTER 3

FOURIER ANALYSIS AND HARMONICS ELIMINATION

3.1 FOURIER SERIES FOR PERIODIC FUNCTION

Under steady-state condition, the output voltage of power converters is,

generally, a periodic function of time defined by

vo(t) = vo (t + T) (3.1)

where T is the periodic time. If f is the frequency of the output voltage in hertz, the

angular frequency is

= 2 /T = 2f (3.2)

and Eq.(3.1) can be rewritten as

vo(t) = vo (t +2 ) (3.3)

The Fourier theorem states that a periodic function vo(t) can be described by a constant

term plus an infinite series of sine and cosine terms of frequency n where n is an integer.

Therefore, vo(t) can be expressed as

vo(t)= a0ancos nt + bnsin nt

n varies from 1 to infinity

where a0/2 is the average value of the output voltage . The constants a0, an and bn can be

determined from the following expressions:

(3.5)

(3.6)

(3.7)

If the output voltage has a half-wave symmetry, the number of

integrations within the entire period can be reduced significantly. A waveform has the half-

wave symmetry if the waveform satisfies the following condition:

vo(t) = -vo (t + ) (3.8)

In a waveform with a half-wave symmetry, the negative half-wave is a

mirror image of the positive half-wave, but phase shifted by T/2 s (or rad) from the

8

positive half-wave. A waveform with a half-wave symmetry does not have the even

harmonics (i.e., n = 2,4,6, … ) and possess only the odd harmonics (i.e., n = 1,3,5, …. ).

Due to the half-wave symmetry, the average value is zero (i.e., a0 = 0). Moreover if the

wave is symmetric about y-axis, it contains only cosine terms (i.e., bn = 0) and if the wave

is anti-symmetric, it contains only sine terms (i.e., an = 0).

3.2 HARMONICS ELIMINATION

Fig 3.1 Waveform of 2-level inverter

As shown in the fig 3.1, the output wave of a multilevel inverter can viewed

as the summation of square waves having different conducting angles.

vo(t) = va(t) + vb(t) (3.9)

Due to the quarter-wave symmetry along the x-axis, both Fourier

coefficients a0 and an are zero. We get bn as

(3.10)

(3.11)

which gives the instantaneous voltage von(t) of nth component as

9

(3.12)

The conducting angles a1 and a2 can be chosen such that the total harmonic

distortion of the output voltage is minimized. These angles are normally chosen so as to

cancel some predominant lower frequency harmonics. Here the conducting angles should

be chosen so as to eliminate the 3rd and 5th harmonics. So we must solve the following

equations.

cos 31 + cos 32 = 0 (3.13)

cos 51 + cos 52 = 0 (3.14)

3.2.1 Conduction angles calculation

Rearrange the equations 3.13 & 3.14; we can get the following equations,

2=cos-1(-cos(3*1)))/3; (3.15)

1=cos-1(-cos(5*2)))/5; (3.16)

Initially the simple gauss-siedel iteration method is used to solve the above

equations. But iteration starts oscillating between two values. So a slight change is

introduced in the normal iteration procedure. A simple C++ program is developed to solve

the above equations.

3.2.1.1 C++ Program for iteration

#include<conio.h>

#include<iostream.h>

#include<math.h>

void main()

{

float a1,a2,a11,a22;

clrscr();

cout<<"\n\tGIVE THE INITIAL GUESS\n\t";

cin>>a1;

cout<<"\n\t a1"<<"\t\t"<<" a2\n\n";

while((a1!=a11)&&(a2!=a22))

{

a11=a1;

a22=a2;

10

a2=(acos(-cos(3*a1)))/3;

a1=(acos(-cos(5*a2)))/5;

cout<<"\t"<<a1<<" \t"<<a2<<"\n";

a1=(a11+a1)/2;

}

getch();

}

Output:

Fig 3.2 Output of the program

1 = 0.20944 rad = 120 (3.17)

2 = .837758 rad = 480 (3.18)

Thus the conducting angles are successfully found.

11

CHAPTER 4

POWER MOSFET

4.1 INTRODUCTION

A power MOSFET is a voltage-controlled device and requires only a

small input current. The switching speed is very high and the switching times are of the

order of nanoseconds. Power MOSFETs find increasing applications in low-power high-

frequency converters. MOSFETs do not have problem of second breakdown phenomena as

do BJTs. However, MOSFETs have the problems of electrostatic discharge and require

special care in handling.

4.1.1 Basic structure and Operation

Fig 4.1 n-channel enhancement type MOSFET

The two types of MOSFETs are 1) depletion MOSFETs and 2)

enhancement MOSFETs. The gate is isolated from the channel by a thin oxide layer. The

three terminals are called gate, drain, and source. An n-channel enhancement-type

MOSFET has no physical channel, as shown in fig 4.1. If VGS is positive, an induced

voltage attracts the electrons in the p-layer and accumulates them at the surface beneath the

oxide layer. If VGS is greater than or equal to a value known as threshold voltage VT, a

sufficient number of electrons are accumulated to form a virtual n-channel and the current

flows from the drain to source. The polarities of VDS, IDS, and VGS are reversed for a p-

channel enhancement type MOSFET.

12

Fig 4.2 Transfer characteristics of n-channel enhancement-type MOSFET

4.1.2 SWITCHING CHARACTERISTICS

Without any gate signal, an enhancement-type MOSFET may be

considered as two diodes connected back to back or as an NPN-transistor. The gate

structure has parasitic capacitances to the source, Cgs, and to the drain, Cgd. The npn-

transistor has a reverse-bias junction from the drain to the source and offers a capacitance,

Cds.

Fig 4.3 Switching waveforms and times

The typical switching waveforms and times are shown in fig. 4.3. the turn-

on delay time td(on) is the time that is required to charge the input capacitance to threshold

voltage level. The rise time tr is the gate-charging time from the threshold level to the full

gate voltage Vg, which is required to drive the MOSFET into the saturated region. The

turn off time delay td(off) is the time required for the input capacitance to discharge from the

13

overdrive gate voltage to the pinch-off region. VGS must decrease significantly before VDS

begins to rise. The fall time tf is the time that is required for the input capacitance to

discharge from the pinch-off region to threshold voltage. If VGS<VT, the transistor turns off.

4.1.3 ON state resistance

When the MOSFET is in the on-state, the channel of the device behaves like

a constant resistance RDS(on) that is linearly proportional to the change between vDS and iD as

given by the following relation:

(4.1)

The total conduction (on-state) power loss for a given MOSFET with

forward current ID and on-resistance RDS(on) is given by

(4.2)

The value of RDS(on) can be significant and varies between tens of

milliohms and a few ohms for low-voltage and high-voltage MOSFETS, respectively. The

on-state resistance is an important data sheet parameter, because it determines the forward

voltage drop across the device and its total power losses.

4.1.4 Internal body diode

The modern power MOSFET has an internal diode called a body diode

connected between the source and the drain as shown in Fig. 4.4. This diode provides a

reverse direction for the drain current, allowing a bidirectional switch implementation.

Fig 4.4 MOSFET internal body diode

4.2 MOSFET IRF630 FP

14

Fig 4.5 MOSFET IRF630 FP

The MOSFET, which we are using now, is IRF630FP. It is manufactured by

‘STMicroelectronics’. It is an N-Channel, 200V, 9A MOSFET. It has an ON-state

resistance of 0.35 only

It has good switching characteristics. Its turn-ON time is only 34ns and its

turn-OFF time is 70ns.

Fig 4.6 Internal Schematic diagram

Fig 4.7 Output characteristics

15

1. Gate2. Drain3. Source

Fig 4.8 Transfer characteristics

Fig 4.9 Static Drain-Source ON resistance characteristics

The maximum VGS allowed is 20V. To turn ON the device, 9V is applied as

gate to source voltage using a battery.

CHAPTER 5

16

MICRO-CONTROLLER

5.1 GENERAL DESCRIPTION AND FEATURES

The micro-controller is used here to create accurate on, off pulses for all the

eight MOSFETs. Using a micro-controller for generating the switching sequence is very

advantageous in many aspects. It is very compact, occupies very less space, allows

reprogramming of time-delays, and is very reliable.

The P89V51RD2 is an 80C51 microcontroller with 64 kB Flash and 1024

bytes of data RAM.

Some features of P89V51RD2:

5 V Operating voltage from 0 to 40 MHz

Three 16-bit timers/counters

TTL- and CMOS-compatible logic levels

Low EMI mode (ALE inhibit)

Four 8-bit I/O ports

It is plastic dual in-line package. It has 40 pins.

5.2 BLOCK DIAGRAM OF P89V51RD2

The block diagram gives the architecture of micro-controller. The diagram

is self-explanatory.

Fig 5.1 Block diagram of P89V51RD2

5.3 PIN CONFIGURATION

17

Fig 5.2 Pin configuration of P89V51RD2

5.4 FUNCTIONAL DESCRIPTION

18

5.4.1 Memory organization

The device has separate address spaces for program and data memory.

There are two internal flash memory blocks in the device. We use only the Block 0. It has

64 kB and contains the user’s code. The data RAM has 1024 bytes of internal memory.

The device can also address up to 64 kB for external data memory.

5.4.2 Timers 0 and 1

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be

configured to operate either as timers or event counters. In the ‘Timer’ function, the

register is incremented every machine cycle. A machine cycle consists of six oscillator

periods. Timer 0 and Timer 1 have four operating modes from which to select.

Control bits C/T in the Special Function Register TMOD select the ‘Timer’

or ‘Counter’ function. These two Timer/Counters have four operating modes, which are

selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both

Timers/Counters. Mode 3 is different. The four operating modes are described in the table

5.1 and 5.2.

Table 5.1 TMOD Timer/counter control register bit allocation

Table 5.2 TMOD Timer/counter control register bit description

Table 5.3 TMOD Timer/counter control register M1/M0 operating mode

19

Table 5.4 TCON Timer/counter control register bit allocation

Table 5.5 TCON Timer/counter control register bit description

5.4.3 Modes of operation

5.4.3.1 Mode 0

In the mode 0 timer register is configured as a 13-bit register. The 13-bit

register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn

are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the

20

registers. Mode 0 operation is the same for Timer 0 and Timer 1. There are two different

GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

5.4.3.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register

(THn and TLn) are used.

5.4.3.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with

automatic reload; Mode 2 operation is the same for Timer 0 and Timer 1.

5.5 PROGRAMMING

5.5.1 Switching sequence selection

Switching sequence should be selected so as to equally utilize both the

voltage sources and to equally use all the eight MOSFETs. The switching sequence is

shown in fig. The MOSFETs are equally used, that is, four times per cycle.

Fig 5.3 Switching sequence

5.5.2 Delay time calculation

1. Time gap for +V output:

t1=((2-1)/360)*20 ms

=((48-12)/360)*20 ms

=2 ms

2. Time gap for +2V output:

21

t2=(((180-36-1)-2)/360)*20 ms

=(((180-36-12)-48)/360)*20 ms

=4.6667 ms

3. Time gap for 0V output:

t3=(21/360)*20 ms

=(24/360)*20 ms

=1.3333 ms

Since the waveform is half-wave symmetry and also quarter-wave with respect to

x-axis, time gap for other voltage levels can be easily calculated.

4. Time gap for -V output:

t -1 = t1

= 2 ms

5. Time gap for -2V output:

t -2 = t2

= 4.6667 ms

5.5.3 Calculation of values for timer register

‘Timer 0’ is used in 16-bit mode. The clock frequency used in micro-

controller is 11.0592 MHz. The micro-controller is used with 12-clock rate, i.e., 12 clocks

per machine cycle.

Therefore, to execute a one-machine cycle instruction, it takes,

(1/11.0592)*12 = 1.085 s

The decrementing operation in timer needs one machine cycle. Therefore

the value to be stored in the timer register can be calculated as follows,

c1 = (2/1.085)*1000

= 1843 cycles = 733H cycles

T1 = FFFFH-733H = F8CC H

c2 = (4.6667/1.085)*1000

= 4301 cycles = 10CDH cycles

T2 = FFFFH-10CDH = EF32 H

22

c3 = (1.3333/1.085)*1000

= 1288 cycles = 508H cycles

T3 = FFFFH-508H = FAF7 H

For all the above values, last 30 to 90 cycles, of the output of port 0 is

maintained at zero to avoid short-through problem, because of switching delay in opto-

coupler and MOSFET.

5.5.4 Port 0 output values

Since all the outputs are taken from port 0, it is unable to drive the opto-

coupler. To avoid this problem, anode is connected to the source voltage of micro-

controller and cathode is connected to the ports. So, to drive an opto-coupler LED, the port

pin should be at 0-level not at 1-level. The port 0 output values are calculated based on the

above idea.

Table 5.6 Port 0 output values

S8 S7 S6 S5 S4 S3 S2 S1 Port 0 output value

1 1 0 0 0 1 1 0 C6H

0 1 1 0 0 1 1 0 66H

0 1 1 0 1 1 0 0 6CH

1 1 0 0 1 1 0 0 CCH

0 0 1 1 1 0 0 1 39H

1 0 0 1 1 0 0 1 99H

1 0 0 1 0 0 1 1 93H

0 0 1 1 0 0 1 1 33H

5.5.5 Program

Device: P89V51RD2

ORG 0H;

MOV TMOD,#01;

CLR TF0;

HERE: MOV A,#0C6H;

23

MOV P0,A;

MOV TL0,#0FCH;

MOV TH0,#0F8H;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0E1H;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#66H;

MOV P0,A;

MOV TL0,#8FH;

MOV TH0,#0EFH;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0E1H;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#6CH;

MOV P0,A;

MOV TL0,#0FCH;

MOV TH0,#0F8H;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0EBH;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#0CCH;

MOV P0,A;

MOV TL0,#23H;

MOV TH0,#0FBH;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0EBH;

MOV TH0,#0FFH;

ACALL DELAY;

24

MOV A,#39H;

MOV P0,A;

MOV TL0,#0FCH;

MOV TH0,#0F8H;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0E1H;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#99H;

MOV P0,A;

MOV TL0,#6AH;

MOV TH0,#0EFH;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0E1H;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#93H;

MOV P0,A;

MOV TL0,#0FCH;

MOV TH0,#0F8H;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0EBH;

MOV TH0,#0FFH;

ACALL DELAY;

MOV A,#33H;

MOV P0,A;

MOV TL0,#25H;

MOV TH0,#0FBH;

ACALL DELAY;

MOV A,#0FFH;

MOV P0,A;

MOV TL0,#0EBH;

MOV TH0,#0FFH;

25

ACALL DELAY;

LJMP HERE;

DELAY:

SETB TR0;

AGAIN:JNB TF0,AGAIN;

CLR TR0;

CLR TF0;

RET;

END

The above program is simulated in ‘keil u-vision’ software. The output waveform for each

pin of port 0 is shown in fig 5.6

Fig 5.4 Output waveform of port 0, pins 0-7, from top to down

The fig 5.7 shows the actual ON and OFF time pulses to the opto-coupler.

Fig 5.5 ON and OFF pulses to the opto-coupler

26

CHAPTER 6

OPTO-COUPLER

6.1 INTRODUCTION

Opto-coupler is nothing but a combination of LED and a phototransistor. It

provides optical coupling between input and output. The input side has a LED. It emits

photons, when it is forward biased. The output side has a phototransistor. When the

emitted photons hit the phototransistor, it induces the base current to flow. The transistor is

switched on. When the LED is not forward biased, the transistor remains in off state.

Fig 6.1 Opto-coupler

6.2 IMPORTANCE OF OPTO-COUPLER

Opto-coupler is used to solve two main problems. One is common ground

problem, which arises because of MOSFETs, which need individual signal grounds.

Second problem is the gate driving voltage of MOSFET.

6.2.1 Common ground problem

When the signal is directly given from micro-controller, the ‘source’ of all

MOSFETs should be commonly grounded to the micro-controller ground. It makes some

MOSFETs permanently shorted as shown in fig 6.2. To avoid this problem opto couplers

are used. Each phototransistor is driven by individual dc supply.

Fig 6.2 Common ground

27

The common ground problem eliminated circuit is shown in fig 6.3

V1

9Vdc

U1PS25011

2

3

4

R1

10k

U1PS25011

2

3

4

0

Q3IRF630/TO

0

V1

9Vdc

R1

10k

Q4IRF630/TO

Fig 6.3 Signal coupling using opto-coupler

6.2.2 Gate driving voltage

The driving voltage from micro-controller is only 5V. It is not sufficient to

drive a power MOSFET IRF630. The usage of opto-coupler paves the way to increase the

gate driving voltage. A 9V dc source is used to drive the gate of the MOSFET. It is shown

in fig 6.3.

6.3 OPTO-COUPLER 817B

Fig 6.4 817B opto-coupler in a 4-pin dual in-line package

28

Fig 6.5 Pin description

It consists of a gallium arsenide infrared emitting diode driving a silicon

phototransistor. It is in dual in-line package as shown in fig 6.4 and pin description is

shown in fig 6.5.

63.1 Characteristics

The maximum Vce0 that can be applied is 70V. It can sustain a continuous

collector current of 50mA. The maximum rise time and fall time are 18 s at the load

resistance of 100

Fig 6.6 Forward voltage vs. forward current

Fig 6.7 Collector current vs. collector emitter voltage

29

CHAPTER 7

SIMULATION IN MULTISIM SOFTWARE

7.1 INTRODUCTION

MULTISIM is user-friendly simulation software. The entire circuit is

simulated in MULTISIM. But the exact components are unavailable in MULTISIM. So the

components are chosen such that their characteristics are almost similar to the originally

used components.

Fig 7.1 Circuit simulated in MULTISIM

7.2 FOURIER ANLAYSIS RESULT

30

The Fourier analysis has been done in the output (stepped) waveform using

MULTISIM software.

Fig 7.2 Fourier analysis – Magnitude of each component

Table 7.1 Magnitude of each harmonic component

CHAPTER 8

31

HARDWARE IMPLEMENTATION

8.1 THE WHOLE SETUP

Fig 8.1 The whole setup of the project

8.2 MICRO-CONTROLLER

The wires shown in fig 8.2 are output wires taken from port 0 of micro-

controller.

Fig 8.2 Micro-controller

32

8.3 CIRCUIT SETUP

Chips, which are in left-hand side in the fig 8.3, are opto-couplers. The

output of the opto coupler is given as VGS to the MOSFET.

Fig 8.3 Circuit setup

8.4 OUTPUT WAVEFORM

The output of the inverter is connected to a resistive load. The waveform is

seen using a CRO.

Fig 8.4 Output waveform

CHAPTER 9

33

CONCLUSION

The 3rd and 5th order harmonics eliminated, two-level cascaded inverter is

successfully implemented in hardware. It is giving the expected output. It is well suited for

dc-ac conversion from batteries, fuel cells and solar cells. Compared to other multilevel

inverter topologies, it requires least no of components. Since the circuit for all the levels

are same, optimized circuit layout and packaging are possible. This two-level inverter has

only 8 transitions in each cycle, but a PWM inverter of same type needs 10 transitions.

Moreover in each transition only half of the voltage is applied across the MOSFET so

switching loss is halved. Thus switching loss is substantially reduced compared to PWM

inverter

REFERENCES

34

[1] Muhammad H.Rashid (2004) “Power electronics Circuits, Devices and Applications”,

Third Edition, Prentice Hall, India.

[2] Muhammad H.Rashid (2001) “Power electronics Handbook”, Academic press.

[3] Roger C.Dugon, Mark F.McGranaghan, Surya santoso, H.Wayne Beaty (2004)

“Electrical Power Systems Quality”, Second Edition, McGraw-Hill.

[4] Muhammad Ali Mazidi, Janice Gillispe Mazidi, Rolin D.Mckinlay (2006) “The 8051

Microcontroller and Embedded Systems Using Assembly and C”, Second Edition, Prentice

Hall, India.

[5] David A.Bell (2006), “Electronic Devices and Circuits”, Fourth Edition, Prentice Hall,

India.

[6] Alberto Lega (2007) “Multilevel Converters: Dual Two-Level Inverter Scheme”, Ph.D.,

thesis, Department of Electrical Engineering, University of Bologna

[7] Zainal Salam (2003) “Design and development of a Stand-alone Multilevel Inverter For

Photovoltaic Application”, Research Report, Faculty of Electrical Engineering, UTM.

[8] Data sheets of MOSFET IRF630, OPTO-COUPLER 817B, P89V51RD2 from

www.datasheetcatalog.com

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