TUTORIAL

Task: Implement a simple 2-input logic AND gate, firstly, using VHDL, then with IP integrator. Simulate

and test both designs on FPGA development board. Connect inputs to Push Buttons or Switches and

observe output on a LED. For pin numbers check either manual or the board itself (written in

parenthesis besides each component).

Solution (VHDL) Double-click Vivado icon on the computer desktop to start the program. Select New Project option

from the File menu to start the New Project Wizard.

Figure 1. New Project Wizard 1st Window

Name the project (a directory of the same name is created to store the project files). Do not store

projects in folders, which have spaces in either name or the path. Make sure that the Create Project

Subdirectory box is checked. Press Next to proceed. Select RTL Project option in the Project Type form,

and click Next.

Figure 2. “Add sources” window

During the Add Sources step you can create or import your source files. Click on the Create File button.

You will see Create Source File dialog box. Name your VHDL file. Click OK. You can skip this step and

add the sources later by choosing Add sources in Project Manager window. Make sure that VHDL is

selected as target and simulator language.

Figure 3. “Default part” window

In the Default Part form choose the Board tab and select ZedBoard Zynq Evaluation and Development

Kit. Click Next to review the Project Summary page.

Define Module window will appear if the source file was created in the Wizard. Otherwise you will see

it after pressing Add Source in Project Manager menu. For the new source file specify the entity and

architecture names, port names, including their direction and range, if they are of vector type.

Figure 4. Define module window.

The new source file opens with the HDL Editor. The working space already contains a skeleton code. In

order to complete the task of creating a 2-input logic AND element only one line of code is needed. It

is underlined in Listing 1.

In order to test the functionality of the AND gate, it should be simulated with a test bench. Test bench

is a VHDL code, which applies stimulus to design entity during simulation. Create a new source file by

clicking on Add Sources under the Project Manager tasks of the Flow Navigator. You will see Add

Sources dialog box. Select Add or create simulation sources and click Next. Click on the Create File in

the Add or create simulation sources form. You will see Create Source File dialog box. Name your

testbench file and click OK. In Add or create simulation sources form click Finish. After you will see

Define Module form. Click OK and confirm action (click Yes). The working space again already contains

a skeleton code. Example test bench for AND gate is shown in Listing 2.

entity and_gate_tb is -- Port ( ); end and_gate_tb; architecture Behavioral of and_gate_tb is COMPONENT AND_Gate port ( A : in STD_LOGIC; B : in STD_LOGIC; O : out STD_LOGIC ); END COMPONENT; signal A, B, O : std_logic; begin uut: AND_Gate port map (A => A, B => B, O => O );

entity AND_gate is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

O : out STD_LOGIC);

end ANG_gate;

architecture Behavioral of ANG_gate is

begin

O <= A and B;

end Behavioral;

Listing 1. AND Gate

A <= '0'; B <= '0'; wait for 5 ns; A <= '1'; B <= '0'; wait for 5 ns; A <= '0'; B <= '1'; wait for 5 ns; A <= '1'; B <= '1'; wait for 5 ns; end Behavioral;

Listing 2. Testbench

Select Simulation Settings under the Simulation tasks of the Flow Navigator pane. Select the Simulation

tab, and set the Simulation Run Time value to 100ns and click OK. Click on Run Simulation > Run

Behavioral Simulation under the Simulation tasks of the Flow Navigator pane. The testbench and

source files will be compiled and the Vivado simulator will be run.

The next step is to connect input/output ports of the design to FPGA device package pins. This involves

a creation of the XDC file, which specifies constraints placed on the design. You can do this by creating

the XDC file using Add Sources option in Project Navigator and defining all constraints manually or by

using I/O Ports window which is similar to PlanAhead tool in Xilinx ISE. You can use this tool after

performing design elaboration (optional RTL Analysis step) or design synthesis.

Click on Open Elaborated Design under the RTL Analysis tasks of the Flow Navigator. Click OK in

Elaborate Design dialog box. To access I/O ports window you can switch to I/O Planning layout in

toolbar menu or select it in window menu.

Figure 5. Changing layouts

The only thing to do here is to fill the Site column with the appropriate numbers of FPGA device pins.

Expand the Scalar ports. Select Site for each port (Site is physical port on the board, written in

parenthesis besides each component). Choose F22 site for port A, G22 site for port B and T22 for port

O. LVCMOS33 in column I/O Std for each port.

Figure 6. I/O Planning

Click Save Constraints (top of the Vivado window). You will see Save Constraints dialog box. Name your

constraints file and click OK. After that you can check this file in the Sources pane.

Now all is set to begin the creation of the BIT file, which contains all configuration data, which

defines the internal logic and interconnections in the target device. The binary information in the

BIT file can then be downloaded into the FPGA device’s memory cells using Hardware Manager tool.

In Program and Debug menu of Flow Navigator click Generate bitstrem.

Figure 7. “Program and Debug” menu in “Flow Navigator”

When the generate bitstream is completed, you will see a Bitstream Generation Completed dialog box

(assuming no errors). Select Open Hardware Manager and click OK.

ZedBoard connection:

1. Now, make sure that the configure jumpers have that position. (shown below “jumpers”)

2. Connect the power jack. (1)

3. Connect the PC and the board by Micro-USB. (2)

4. Power ON the switch on the board. (3)

Figure 8. ZedBoard

Click on the Open target link and select Auto Connect. You will see Open New Hardware Target dialog

box. Click Next. Select Local server as the Connect to in the Hardware Server Settings form. Click Next.

Select Xilinx_tcf in the Select Hardware Target form. Make sure that the JTAG Clock Frequency is

15000000 and click Next. You will see the xilinx_tcf/... in the Hardware pane similar to the one shown

below. In this step, we can program FPGA. Click on the Program device link. In Program Device dialog

box click Program. When the configuration process is completed, make sure that the loaded design is

working correctly.

Figure 9. “Hardware Manager” window

Solution (IP Integrator) In order to complete the task you have to package your AND gate as an IP core. To do this select Create

and Package IP in Tools menu.

Figure 10. Create and Package IP

Create Peripheral, Package IP or Package Block Design wizard will appear. Choose Package your current

design in first windows and select a directory for your IP in the second window. The new IP core will

be created from your design after performing all steps of the wizard.

Figure 11. “Create Peripheral, Package IP or Package Block Design” wizard 1st window

Click on Create Block Design in IP Integrator menu of Flow Navigator. The diagram window of IP

Integrator will appear. Click on Setting for IP catalog icon ( ) in diagram window. In Repository

Manager of Project Setting click on “+” icon and add the directory of your IP core as a new repository

and press OK.

Figure 12. IP repository settings.

Click on Add IP icon in diagram window ( ). Search for your IP core and add it to the diagram. Right-

click on every input and output of your IP core in the diagram window and select Make external in the

drop-down menu.

Figure 13. Making ports external

Figure 14. AND_Gate IP core with external ports.

Now you have to create a top HDL file from your design. Right-click on your block design in the Sources

pane. Select Generate Output Products in the drop-down menu and when the operation is completed

select Create HDL Wrapper. Make sure that the newly created VHDL file is a top file.

Figure 15. Creating VHDL file from block diagram.

After this you can perform simulation, synthesys and implementation of the design with testbench and

constraints files created above.