ISSN 1292-862

TIMA Lab. Research Reports

TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France

Global Modeling and Simulation of System-on-Chip embedding MEMS devices

Z. JUNEIDI, K. TORKI, S. MARTINEZ, G. NICOLESCU, B. COURTOIS, A. JERRAYA

TIMA Lab., 46, Avenue Félix Viallet, 38031 GRENOBLE Cedex, France

Tel: +33 4 76 57 46 17, Fax: +33 4 76 47 38 14, Email: Zein.Juneidi@imag.fr

ABSTRACT Systems-on-Chip (SoC) and Systems-on-Package (SoP) are becoming more and more heterogeneous systems. Logic parts, Analog parts, Communication devices, and MEMS components are being integrated on the same chip. In order to validate systems containing such variety of components, global multi-domain simulation of different aspects becomes especially important. Hardware/software, analog/digital, electronic/ mechanical/optic mixed simulations must be accessible. This paper presents a methodology to establish an environment for the global modeling and simulation of systems on chip embedding MEMS devices. This methodology is illustrated into two co-simulation frameworks: The optical cross-connect co-simulation framework and the electro-thermal co-simulation framework. Keywords: Global simulation, System on Chip, MEMS, Behavioral Modeling, Thermal Co-Simulation, Optical Co-Simulation.

1. INTRODUCTION A mixed-simulation environment allows the validation of complex multi-domain systems containing logic parts (CPU, RAM, ROM), analog parts (Converters, Filters), communication devices (RF antennas), and MEMS components (sensors and actuators) on the same chip. Multilanguage modeling and co-simulation using languages such as C and VHDL is essential for the conception and validation of software and digital hardware; furthermore, behavioral languages such as VHDL-AMS, VERILOG-A and MATLAB allow creating macro-models for analog electronic subsystems and for MEMS devices. The complete set of models for the software, electronic parts and MEMS devices can be then concurrently analyzed in a co-simulation environment. Additionally, analog behavioral modeling can be used for fault simulation of the MEMS devices and for the thermal evaluation of the system package. Figure 1 shows the flow in a co-simulation framework. In this environment a multi-language/multi-engine approach is used at the high-level design description. This approach reflects the heterogeneity of systems on

chip and thus the diversity of CAD tools used in the design of such system.

Fig. 1. High level design validation A design flow as that shown in figure 1 allows heterogeneous SoCs to be validated at the high-level which represents lower costs of time and CPU. Additionally, this simulation approach must be able to produce results with high accuracy if models are properly selected. Finally this methodology allows for an architecture exploration making decisions on design and test tradeoffs for a target application.

2. OPTICAL CROSS-CONNECT CO-SIMULATION

An important example of a heterogeneous system with various multi-domain components is the optical cross-connect. Such a system allows for automatic reconfiguration of an optical network by means of micro-mirrors, which are able to establish different paths for the signals coming from the input ports and going into the output ports. The global view of the system is presented in figure 2; it is composed of three main sub-systems: • The control sub-system that will be finally mapped on

a processor. It calculates electronic orders (voltage) that command motion of the mechanical mirrors composing the optical sub-system.

VHDLAMS/ VERILOG- A

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• The electro-mechanical converter that transforms the voltage from the output of the control sub-system into mechanical orders, in terms of distance, for each of the mirrors.

• The optical sub-system that is composed of a 2x2 mirror array, two light generators (G1, G2) two beams detectors (D1, D2) and four lenses (L1-L4). Lenses L1 and L2 are used to collimate beams coming from the input fibers while lenses L3 and L4 are used to focus signals into the output fibers.

Fig. 2. Optical cross-connect

In figure 2, the switching operation is achieved through the mechanical motion of mirrors steering the data path from the inputs (G1 and G2) to the desired outputs (D1 and D2). The optical coupling between the input and output fibers can be measured and used as an input to the control system. The complete cross-connect has a CPU which contains the control algorithm; A/D and D/A converters; electronic drivers; signal conditioning circuits; electro-mechanical parts and optical devices. This is illustrated in figure 3.

A global simulation of such system involves a multi-language description (SystemC/MatLab/C++) and a multi-domain co-simulation environment (digital/analog/ mechanical/optical). The control sub-system is specified in SystemC and the electro-mechanical part in Matlab. Concerning the optical devices (mirrors, lens, beam

generators and detectors), C++ models from the libraries of Chatoyant [7] have been used. The system specification is presented in figure 4.a. For the simplicity of the explanation, only two mirrors of the mirror array are shown in the figure. Modules in the system communicate through communication channels that encapsulate simple handshake protocols. Each mirror module receives control data (i.e. the reflection command) from the electro-mechanical converter with a FIFO communication protocol. To specify the interface of the optical modules and that of the communication channels, module wrappers have internal and external ports. As shown in figure 4.a, the internal ports specific to the module are FIFO ports and the external ports connected to the communication channels are simple handshake ports.

Fig. 4. Specification and simulation models for the optical cross-connect system

To validate the system, the simulation model of the optical cross-connect is generated. Figure 4.b shows a generated simulation model of the system specification in figure 4.a. The communication interfaces that adapt the communication specific to the mirrors model, to the rest of the system are also generated. Using the presented methodology for the simulation models generation, we executed the global cosimulation of such a system, using a 2x2 mirror array that have inputs from two beams generators and outputs to two lights detectors. The simulation time was about 30 seconds. This enable a fast validation of the overall system functionality, before its implementation in a final architecture.

Control system

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Fig. 3. Optical cross-connect architecture

MATLAB

Mirror2 (C++)

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Mirrors array (C++ Chatoyant)

Hand Shake

3. GLOBAL THERMAL CO-SIMULATION The increasing component density and increasing operational speed of today’s integrated circuits raises the problem of the dissipation power density and the chip temperature increasing [10] [12]. The thermal validation of the system on package is becoming a key issue, on the other hand, the generation of dynamic thermal model for the package implies the coupling of the chip locations to the package for the use of electro-thermal simulators [9]. In this section two strongly related issues are discussed: the first is the electro thermal modeling of the package and the second is the thermal IC-package co-simulation.

Package Electro – Thermal modeling: The idea is to couple a thermal simulator to an electrical simulator. In this co-simulation framework a thermal simulator (THERMODEL [11] from MicRed) is coupled to a behavioral simulator (ELDO) by generating behavioral model of package. This is illustrated through the Figure 5.

The basic idea lies on the fact that it is possible to extract the main time constants of a linear RC system from its response function [10][12]. The thermal system (chip + package) is excited by a step-function. The thermal response function is calculated then it’s translated by THERMODEL into a RC network witch presents a thermal one-port model. The thermal/electrical analogy allows the thermal RC model (presented as THERMODEL output netlist) to be converted into a behavioral model (HDL-A, Verilog-A).

IC-package Thermal Co-simulation: All integrated circuits are designed to operate reliably within a defined temperature range. Outside this range there is no insurance that an IC continues to function correctly. In order to insure the functionality of an IC within the allowed temperature range, an accurate simulation of the dynamic temperature evaluation is needed. Such simulation could provide different thermal maps of the integrated circuit thermal behavior. By

evaluating these different thermal maps for several classes of applications, it is possible to: 1. Identify the hottest locations of the IC in function of

the current application: Because the hottest location on an IC may change from application to application, it’s important to the designer to identify these locations and then to envisage the appropriate solution to reduce the circuit’s local temperature. These solutions may vary between the dispersing of the hottest modules of the circuit into far enough positions of the layout, or by choosing an appropriate cooling package to the circuit

2. Resolve the IR (voltage) drop problem: With the use of more and more low-level power consumption technology, voltage levels are becoming more and more smaller and the voltage drops along the power and ground lines can lead to a degradation in performance or, worse, functional failure. Depending on the correlation between the thermal behavior of the circuit and its power consumption, it is possible to overcome the problem of the IR drop by analyzing the thermal maps of the IC behavior and to change the floor planning and power distribution strategies.

Fig. 6. Data flow in IC thermal simulation frame work:

(a)-. Coupled with THERMAN (b)-. Generating a stimulus for ELDO.

Thermal response of a package

THERMODEL

Ladder model of the package

HDL-A model C1

R1

C2 C3 Cn

R2 R3

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Time constants and their magnitudes

Fig. 5. One-Input-Thermal behavioral Model

Until now most of designers estimate the thermal circuit behavior by simplistic formula on a spreadsheet. This simplistic guess work approach may lead to inefficiencies or worse, non-working or unreliable silicon. Other designers use electrical simulators at the transistor level (Spice-like simulations). Those kinds of simulations are very CPU consuming and, worse, in the case of large scale circuits simulations this type of simulations becomes unrealistic. A new methodology is needed to evaluate the dynamic thermal behavior of the different modules of integrated circuits. Since the main factor which defines the thermal behavior of an integrated circuit is its power consumption, this last one depends directly on the signals switching of the different nodes in the different blocks of the IC. Hence it is necessary to calculate the switching activities of each node based on a set of test vectors in order to get an accurate evaluation of the power consumption. At the chip level a worst case can be modeled on the data for each module or an operation depending switch number can be calculated basing on the operation of each module. The dissipated energy by every module or by each cell is proportional to this number and the fanout load. Two tasks are especially important to achieve such simulations: the first is to characterize the basic cells to have their basic power number, the second is to scan the timing netlist file (.sdf) to get the fanout load for each instantiated cell ( See figure 6). In this section a methodology of integrated circuit thermal behavior simulation is illustrated. This methodology is based on the switching activities calculation at the gate level. Two ways of thermal simulations are proposed, the first is on-line interactively with the Verilog simulation of the circuit (TCF Toggle Count File). And the second is computed off-line by post processing the sign-off simulation database results (VCD Value Change Dump file). Finally the results of those computations are exploited in two manners: a) Cell level thermal map and chip level thermal map:

The result of the thermal activity is back-annotated to the design layout in two ways. The first is a direct illustration by color on top of the standard cells allowing the precise identification of the power activity at cell level. The second is a smoothing of the last result by the use of a thermal simulator (THERMAN [11]) allowing to show the real thermal distribution in the design at chip level. This kind of smoothing illustrates the substrate capacity and resistance to dissipate or distribute the thermal activity produced by each individual cell.

b) Package level thermal simulation: The input stimulus which allows the thermal behavior activation of the package is the direct sum of the total energy produced by each individual cell in the IC design. This stimulus can be generated from the same calculation done in the previous section.

This stimulus presents the total dynamic power dissipated by the whole IC design.

4. CONCLUSION

In this paper, a methodology of multi-domain and multi-language co-simulation has been demonstrated. This methodology enables the automatic generation of simulation models for the homogeneous specifications where the different modules may use different communication concepts or may be described in different languages. This methodology has been applied to the co-simulation of two complex heterogeneous multi-domains applications: an optical cross-connect co-simulation and a global thermal simulation of system on package.

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