the tunnel vision syndrome: fpl fellow massively delaying ... · the tunnel vision syndrome:...
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[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 1
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
The Tunnel Vision
Syndrome:
Massively Delaying
Progress
1
Reiner Hartenstein
VIPSI-2012 MONTENEGRO
Hotel Splendid in Becici Dec 31, 2012 to Jan 1, 2013
IEEE fellow
FPL fellow
SDPS fellow
Kaiserslautern University of Technology
The George Washington University, 5-7 June 2013, Washington, DC
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
•Preface
•History of Computing
•The Systolic Array
•The Kress Array
•The Xputer Paradigm
•The Twin Paradigm Approach
•More Tunnel Vision
•We must Reinvent Computing
•Conclusions
Outline
2
http://www.uni-kl.de
[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 2
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
3
IEEE 7th ISCA, La Baule, France, May 6-8, 1980
M. J. Foster and H. T. Kung: The Design of Special-Purpose VLSI Chips ...
Systolic Arrays (1)
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
http://www.fpl.uni-kl.de/papers/publications/karl-steinbuch.html
4
why not general purpose ?
M. J. Foster and H. T. Kung: “The Design of Special-
Purpose VLSI Chips ... “ Karl Steinbuch
It is not sufficient to invent something. You need to recognize, that you have invented something.
Systolic Arrays (3)
[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 3
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
5
What Synthesis Method?
of course algebraic! (linear projection)
Rainer Kress replaced it by simulated annealing*:
supports also any irregular & wild form pipe networks
1995:
supports only applications with strictly regular data dependencies
*) KressArray [ASP-DAC-1995]
http://kressarray.de/
( Mathematics Point of View )
(as my student)
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
The Data Streams ?
x x x
x x x
x x x
| | |
x x x x
x x
x x x
- - -
x x x x
x x
x x x
- - -
- - -
- - -
- - -
x x x
x x x
x x x
| | |
| | |
| | |
| |
|
6
*) and receives
[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 4
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
“It’s not our job”
x x x
x x x
x x x
| | |
x x x x
x x
x x x
- - -
x x x x
x x
x x x
- - -
- - -
- - -
- - -
x x x
x x x
x x x
| | |
| | |
| | |
| |
|
7 *) or receives
Another Tunnel Vision Symptom
without a sequencer: missed to invent a new machine paradigm
7
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
8
Who generates
the data streams?
http://xputer.de/ http://data-streams.org/
*) publ. 1989
8
[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 5
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
Duality of procedural Languages
Flowware Languages
read next data item
goto (data address)
jump to (data address)
data loop
data loop nesting
data loop escape
data stream branching
yes: internally parallel loops
9
Software Languages
read next instruction
goto (instruction address)
jump to (instruction address)
instruction loop
instruction loop nesting
instruction loop escape
instruction stream branching
no: internally parallel loops
But there is an AsymmetryAsymmetry But there is an AsymmetryAsymmetry
program counter: data counter(s):
more simple:
no ALU tasks
MoPL state register(s):
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
10
Heterogeneous Taxonomy
The extension into this huge design space is mainly
ignored by curricula and even by most R&D scenes
10
[email protected] 18 February 2014
Featured Invited Talk; The 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), 5-7 June 2013, Washington, DC, USA 6
Reiner Hartenstein, TU Kaiserslautern, Germany http://hartenstein.de
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
11
The tunnel vision of
the pre-manycore age
11
© 2012, [email protected] http://hartenstein.de
TU Kaiserslautern
Conclusions
12
We must disruptively reivent CS education
Disruptive research is urgently required and
We need by orders of magnitude more parallelism and power-efficiency
fundamental issues have to be revisited
We must overcome the von Neumann syndrome and the widespread Tunnel Vision dementia
A reductionist attitude of most R&D areas massively delays the solution of urgent problems