the integrated circuit yield statistics integrated circuit...

PROCEEDINGS OF THE IEEE, VOL. 71, NO. 4, APRIL 1983

Integrated Circuit Yield Statistics

CHARLES H. STAPPER, SENIOR MEMBER, IEEE, FREDERICK M. ARMSTRONG, AND K I Y O T m SAJI

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INTRODUCTION

1 N THE MANUFACTURE of semiconductor integrated circuits, millions of electronic devices are produced simultaneously in a series of very complex processing steps. The

integrated circuits themselves typically contain thousands of such devices. A large number of these circuits are grouped on chips to perform specific electronic functions for which the chip is designed. Chips with more than a hundred thousand electronic devices, such as transistors and diodes, are now being manufactured. The chance that all such devices and their interconnections will function according to the design depends on the control exercised in their manufacture. The fraction of chips that, upon completion of manufacture, can meet a set of very stringent final test requirements is called the yield.

This paper deals with integrated circuit yield statistics. Such statistics are of importance in controlling the actual semiconductor manufacturing yields and for projecting the yield of future semiconductor products. Since the necessity for additional personnel, new factories, and other large capital investments depends on such yield projections, the correct approach to the yield problem is of great importance.

The yields associated with integrated circuit manufacturing can be divided into three parts. The first part deals with chips and wafers which never reach final test. This can be caused by the breakage of wafers, or it may be the result of process errors, such as the wrong process sequence or simply leaving processing steps out, and the like. We will not treat this type of yield loss in this paper. Instead we will analyze the second part, known as the “final test yield.” This is the yield that takes localized process defects into account. This yield can be categorized in two classes. One class contains the “gross defects” which have a “gross yield” associated with them. We will discuss these yields first. The second class of final test yields contains the “random defects” and is known as the random defect yield. The greater part of this paper is about the methods and models needed for estimating the random defect

Manuscript received July 27, 1981;revised February 15,1983. C. H. Stapper is with the IBM General Technology Division, Easex

F. M. Armstrong and K. Saji are with the IBM General Technology Junction, VT 05452.

Division, East Fishkill, NY.

453

Fig. 1. Gross yields affect whole wafers or parts of wafers. The black chips are functioning; the white ones are defective and do not work.

yields. The third part of the integrated circuit yield has to do with packaging. This packaging yield, which depends on the accuracy of the automated wire bonding equipment, will not be covered in this paper.

GROSS YIELDS Gross yields are usually caused by manufacturing errors that

cause parts of wafers or entire wafers t o have no functioning chips. An example of such failures is shown in the wafer map of Fig. 1. The functional chips are colored black, the faulty chips are indicated by the chip locations that are left blank. Wafer maps like these have been described in detail by Ham [ 1 1. A number of processing problems, which we will describe here, usually result in this type of yield loss.

The production of semiconductor devices such as bipolar and fieldeffect transistors is the key to manufacturing integrated circuits. The properties of these devices depend critically on timing and temperatures of the socalled “hot process” steps like diffusions, ion implants, epitaxial silicon growth, or insulator deposition processes. It is in these processes that the collector, base, and emitter of each bipolar transistor is made. Similarly, for the fieldeffect transistors these are the process steps that form the sources, drains, channels, and gate insulators. Excessive variations in process timing and temperature will cause faulty device parameters such as gain, breakdown voltage, resistance, transconductance, and threshold voltage. Entire wafers with integrated circuits will fail when these parameters do not have the correct values. In marginal cases parts of wafers will fail because of these types of process

0018-9219/83/0400-0453$01.00 0 1983 IEEE

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PROCEEDINGS OF THE IEEE, YOLo 71, NO.4, APRIL 1983

Integrated Circuit Yield Statistics

CHARLES H. STAPPER, SENIOR MEMBER, IEEE, FREDERICK M. ARMSTRONG,AND KIYOTAKA SAlI

453

Abmvct- The nndom failule statistics for the yield of mlll-ProducedleIIlicoIlductc. iRtepated circuitI lie derived by COIlIideriDI defect IIldfault formation dtuiJII the mmufacturiJII procelL 'Ibis approIdI. allows the deYeIopmeDt of • yield theoIy 1hat indudeI mIRy mocIeIa thathaft been lIIecl )mI'rioaIly ad a1Io mults in • pnctical control moclelfor intepated cimdt maaafacturiD&- Some simpler formulatiolll ofyield theory that haft been deIcdbecl in the literature lie compuecl tothe model. AppIicatioIII of the model to yield management &Ie disauIIld IIld examples giftn.

INTRODUCTION

lfN THE MANUFACTURE of semiconductor integrated cirJL cuits, millions of electronic devices are produced simulta-

neously in a series of very complex processing steps. Theintegrated circuits themselves typically contain thousands ofsuch devices. A large number of these circuits are grouped onchips to perform specific electronic functions for which thechip is designed. Chips with more than a hundred thousandelectronic devices, such as transistors and diodes, are nowbeing manufactured. The chance that all such devices andtheir interconnections will function according to the design depends on the control exercised in their manufacture. The fraction of chips that, upon completion of manufacture, can meeta set of very stringent final test requirements is called the yield.

This paper deals with integrated circuit yield statistics. Suchstatistics are of importance in controlling the actual semiconductor manufacturing yields and for projecting the yield offuture semiconductor products. Since the necessity for additional personnel, new factories, and other large capital investments depends on such yield projections, the correct approachto the yield problem is of great importance.

The yields associated with integrated circuit manufacturingcan be divided into three parts. The first part deals with chipsand wafers which never reach final test. This can be caused bythe breakage of wafers, or it may be the result of process errors, such as the wrong process sequence or simply leaving processing steps out, and the like. We will not treat this type ofyield loss in this paper. Instead we will analyze the secondpart, known as the "final test yield." This is the yield thattakes localized process defects into account. This yield can becategorized in two classes. One class contains the "gross defects" which have a "gross yield" associated with them. Wewill discuss these yields first. The second class of final testyields contains the "random defects" and is known as the ran,,"om defect yield. The greater part of this paper is about themethods and models needed for estimating the random defect

Manuscript received July 27, 1981;revised February 15,1983.C. H. Stapper is with the IBM General Technology Division, Essex

Junction, YT 05452.F. M. Armstrong and K. Saji are with the IBM General Technology

Division, East Fishkill, NY.

Fig. 1. Gross yields affect whole wafers or parts of wafers. The blackchips are functioning; the white ones are defective and do not work.

yields. The third part of the integrated circuit yield has to dowith packaging. This packaging yield, which depends on theaccuracy of the automated wire bonding equipment, will notbe covered in this paper.

GROSS YIELDS

Gross yields are usually caused by manufacturing errors thatcause parts of wafers or entire wafers to have no functioningchips. An example of such failures is shown in the wafer mapof Fig. I. The functional chips are colored black, the faultychips are indicated by the chip locations that are left blank.Wafer maps like these have been described in detail by Ham[I]. Anumber of processing problems, which we will describehere, usually result in this type of yield loss.

The production of semiconductor devices such as bipolarand field-effect transistors is the key to manufacturing integrated circuits. The properties of these devices depend critically on timing and temperatures of the so<alled "hot process"steps like diffusions, ion implants, epitaxial silicon growth,or insulator deposition processes. It is in these processes thatthe collector, base, and emitter of each bipolar transistor ismade. Similarly, for the field-effect transistors these are theprocess steps that form the sources, drains, channels, and gateinsulators. Excessive variations in process timing and temperature will cause faulty device parameters such as gain, breakdown voltage, resistance, transconductance, and thresholdvoltage. Entire wafers with integrated circuits will fail whenthese parameters do not hav~ the correct values. In marginalcases parts of wafers will fail because of these types of process

0018-9219/83/0400-0453$01.00 © 1983 IEEE

Glenn

Sticky Note

Stapper, C.H.; Armstrong, F.M.; Saji, K., "Integrated circuit yield statistics," Proceedings of the IEEE , vol.71, no.4, pp. 453-470, April 1983 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1456887&isnumber=31324

454

errors. The resulting failures will not cause the chips to fail in random patterns on the wafer. This is why we call them gross failures, and their associated yield, a gross yield. Since the losses are associated with the resulting device parameters, we have coined the word “parameter limited yield” for this problem.

Measuring the parameter limited yield is usually easy. The chips on each wafer have to be spaced some distance apart. This space, known as the kerf or streak, allows for the width of the diamond saws that eventually will dice the wafer into chips. It is in this unused space that test structures and devices can be made at the same time as the product. By testing such devices at appropriate points in the process, a manufacturer will know if the device parameters will meet the requirements for the proper functioning of the integrated circuits. The range of parameters that will allow these circuits t o function is known as the “process window.” If the failing devices in Fig. 1 failed because of device parameters, the test devices in the adjacent kerfs will show this. The fraction of kerf devices with parameter values within the process window therefore equals the parametric yield.

The key to parametric yield analysis is the establishment of the process window. This window can be calculated with computer simulation programs that use circuit designs as input. Results, however, are often unreliable. Experimental techniques such as those described by Gangatirkar et al. have given far better results [ 21 .

There are alternative methods for determining parametric yields. The distribution in Fig. 2 shows the relative number of fieldeffect transistors that have threshold voltages within the values indicated on the horizontal axis. These data are the result of day-today and lot-to-lot variations of this parameter during two months of manufacturing. The fraction of percentage of devices that have parametric values inside the process window is equal to the parametric yield. Elaborate computer simulations have been developed to predict parameter distributions like the one in Fig. 2. The inputs t o these models are process data such as the temperature variations in diffusion steps, the distribution of wafer resistivities, and variations in device dimensions. Excellent results have been reported with such models [ 31, [ 41. These models are of great value t o manufacturers who sort their product by performance, such as gain, access time, power dissipation, and the like. However, for welldesigned and well-planned products this should not be necessary, and very little product should be lost by the day-today fluctuations in parameters. An example of this is shown in the bar chart of Fig. 3. This chart shows relative yield losses occuring in the manufacture of a 64-kbit random-access memory chip. The actual values of the yield losses are proprietary information and cannot be given here. The parametric yield accounts for less than 5 percent of the total yield loss. The associated yield is too high to require these intricate models.

Sometimes gross yield losses are caused by the photolithographic processes. In these processes, the semiconductor device and interconnection patterns are defined by exposing a layer of photosensitive resist with a mask. The photoresist is developed to allow the required patterns to be etched into the conductive or insulator layers underneath. Over- or underexposure, over- or underetching as well as misalignment of the patterns will cause gross yield losses. Visual inspection of newly developed photoresist patterns has been used to control such problems. Measurement and control of misalignment can


I I I I I I I I I I I y I I

L , ~ ~ ! ~ “ ’ ’ ’ ’ ‘ ’ ~ ~ ~ - I

0.8 0.8 1.0 1.2 1.4 1.8 1.8 2.0 VOLTS

Fig. 2. Distribution of field-effect transiptor threshold voltages measured on kerf devices during two months of manufacturing. Devices outside the process window are associated with failing chips.

GROSS YIELD LOSSES

RANDOM DEFECT LOSSES

Yl LI

L!

icon PARAMETERS TESTlClRCUm

MISCELLANEOUS , ALIGNMENT

RANDOY PHOTO DEFECTS

RANDOM PINHOE DEFECTS

RAN- LEAWGE DEFECTS

MtSCELLANEOUS RANDOM DEFECTS

D

-4

Fig. 3. Relative yield l o s s e s on a logarithmic scale. Random defects cause most of the losses.

also be done with electrical test structures [SI -[ 81. Results from both the visual inspection and alignment monitors have made it possible to virtually eliminate these yield losses [9 1, [IO].

RANDOM DEFECT YIELD MODEL AFTLICATION FOR LINE CONTROL

In the early days of manufacture of discrete diodes, bipolar transistors, and fieldeffect transistors, the cause for failing devices was determined by failure analysis of the faulty ones. It was possible, in this way, t o find many of the failure mechanisms and assign a yield to each of them. This method is still used today, but it has its limitations. The manufacturing process for integrated circuit chips is far more complex than that for discrete devices. Chips, therefore, spend more than twice as much time in a manufacturing line as do discrete transistors.


454 PROCEEDINGS OF THE IEEE, VOL. 71, NO.4, APRIL 1983

';"

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VOLTS

Fig. 2. Distribution of field-effect transistor threshold voltages measured on kerf devices during two months of manufacturing. Devicesoutside the process window are associated with failing chips.

YIELDLOSS(LOG.SCALE)

Fig. 3. Relative yield losses on a logarithmic scale. Random defectscause most of the losses.

RANDOM PINHOLEDEFECTS

MISCELLANEOUSRANDOM DEFECTS

RANDOM PHOTODEFECTS

100%PARAMETERS

TESTICIRCUITS

MISCELLANEOUSALIGNMENT

RANDOM LEAKAGE1----1 DEFECTS

I---PROCESS WINOOW--!IIIIIIIIIIIIIIII

GROSSYIELDLOSSES

RANDOMDEFECTLOSSES

20

10

also be done with electrical test structures (5) -[ 8). Resultsfrom both the visual inspection and alignment monitors havemade it possible to virtually eliminate these yield losses (9),(10) .

RANDOM DEFECT YIELD MODEL APPLICATIONFOR LINE CONTROL

In the early days of manufacture of discrete diodes, bipolartransistors, and field-effect transistors, the cause for failing devices was determined by failure analysis of the faulty ones. Itwas possible, in this way, to find many of the failure mechanisms and assign a yield to each of them. This method is stillused today, but it has its limitations. The manufacturing process for integrated circuit chips is far more complex than thatfor discrete devices. Chips, therefore, spend more than twice asmuch time in a manufacturing line as do discrete transistors.

errors. The resulting failures will not cause the chips to fail inrandom patterns on the wafer. This is why we call them grossfailures, and their associated yield, a gross yield. Since thelosses are associated with the resulting device parameters,we have coined the word "parameter limited yield" for thisproblem.

Measuring the parameter limited yield is usually easy. Thechips on each wafer have to be spaced some distance apart.This space, known as the kerf or streak, allows for the widthof the diamond saws that eventually will dice the wafer intochips. It is in this unused space that test structures and devicescan be made at the same time as the product. By testing suchdevices at appropriate points in the process, a manufacturerwill know if the device parameters will meet the requirementsfor the proper functioning of the integrated circuits. Therange of parameters that will allow these circuits to functionis known as the "process window." If the failing devices inFig. 1 failed because of device parameters, the test devices inthe adjacent kerfs will show this. The fraction of kerf deviceswith parameter values within the process window thereforeequals the parametric yield.

The key to parametric yield analysis is the establishment ofthe process window. This window can be calculated with computer simulation programs that use circuit designs as input.Results, however, are often unreliable. Experimental techniques such as those described by Gangatirkar et al. have givenfar better results [2) .

There are alternative methods for determining parametricyields. The distribution in Fig. 2 shows the relative number offield-effect transistors that have threshold voltages within thevalues indicated on the horizontal axis. These data are the result of day-to-day and lot-to-lot variations of this parameterduring two months of manufacturing. The fraction of percentage of devices that have parametric values inside the processwindow is equal to the parametric yield. Elaborate computersimulations have been developed to predict parameter distributions like the one in Fig. 2. The inputs to these models areprocess data such as the temperature variations in diffusionsteps, the distribution of wafer resistivities, and variations indevice dimensions. Excellent results have been reported withsuch models [3], [4]. These models are of great value tomanufacturers who sort their product by performance, such asgain, access time, power dissipation, and the like. However,for well-designed and well-planned products this should not benecessary, and very little product should be lost by the day-today fluctuations in parameters. An example of this is shownin the bar chart of Fig. 3. This chart shows relative yield lossesoccuring in the manufacture of a 64-kbit random-access memory chip. The actual values of the yield losses are proprietaryinformation and cannot be given here. The parametric yieldaccounts for less than 5 percent of the total yield loss. Theassociated yield is too high to require these intricate models.

Sometimes gross yield losses are caused by the photolithographic processes. In these processes, the semiconductor device and interconnection patterns are deimed by exposing alayer of photosensitive resist with a mask. The photoresist isdeveloped to allow the required patterns to be etched into theconductive or insulator layers underneath. Over- or underexposure, over- or underetching as well as misalignment of thepatterns will cause gross yield losses. Visual inspection ofnewly developed photoresist patterns has been used to controlsuch problems. Measurement and control of misalignment can

STAPPER et al.: IC YIELD STATISTICS 4 5 5

Both the process complexity and the increased length of time result in an increased likelihood that something will go wrong in the line. A manufacturer could, therefore, find most of his manufacturing line full of useless product if he relied only on failure analysis and a final test t o tell him what is going on. In- tegrated circuit manufacturing lines, therefore, require monitoring techniques that can function as early warning systems. To make such monitors effective, it is necessary that their data can be used to estimate the percentage of product that is or is not defective. We have already given an example of this in the discussion on gross yields. For random defects the situation is somewhat more complex. This is where random defect yield models are needed. For example, such models are used with visual inspection of photoresist patterns, or newly etched patterns. Inspectors have been trained to examine these patterns in order to count and classify the defective patterns that occur. Due to the complexity of modem integrated circuit chips, it is impossible for the inspector t o tell whether the defects they observe will cause actual chip failures. The yield, therefore, cannot be directly obtained from these inspection data.

The problem is solved with engineering failure models that determine the probability with which each defect type can cause a failure. This is known as the “probability of failure.” It can be multiplied by the number of defects in the corresponding category to obtain the average number of failures or faults per chip. This has to be done for each defect type. Fail- ure models for different defects are described in the next section. The estimation of the yield for each defect type requires one more step. This is done with the statistical models that are the subject of subsequent sections [ 1 1 1 , [ 121 .

Conductors in integrated circuit chips are made with semiconductor diffusions, polycrystalline silicon, or metal. Missing or extra patterns of such conductors can be measured with electronic defect monitors. Such monitors consist of serpentine or interdigitated patterns that are sensitive to specific defect types. An example of such a structure is shown in Fig. 4. It consists of two very long conductive lines which can be tested for open circuits or missing conductive patterns. Extra patterns or short circuits can be detected between the two lines. Failure models are needed to scale from the number of failures in a defect monitor to the number of failures expected on the product. This result is then used in a statistical model t o estimate the equivalent product yield. The random defect yields on the bar chart in Fig. 3 were obtained with yield model estimates from visual inspections and electronic defect monitor data. The data from in-line visual inspection and defect monitors can be compared with failure analysis data collected over a long period. Results have shown that the three measurements can be in very good agreement when the right models are used [ 121.

FAILURE MODELS The data in Fig. 3 show that gross yields account for 16.5

percent of the yield losses. This contrasts with the 83.5 percent of the losses that are due to random defects. The random defects, therefore, cause five times more chips to fail than the gross defects. Data such as these are typical for most manufacturing environments. Random defect models are, therefore, an important factor in planning and controlling the integrated circuit manufacturing yields.

The random defect model has to be broken up into two

H

I

-u a a

Fig. 4. A defect monitor consisting of two long conductors for d e

is a short circuit detector for extra patterns. tecting missing patterns or open circuits. The space between the lines

parts. The first part is the theory that deals with the average number of failures or faults that can be caused by a large number of different defect mechanisms. Several models developed for this purpose will be described in this section of the paper. The second part of the random defect model is the statistical distribution of the number of faults per chip. The statistics used are the topic of the next sections.

The simplest defect model is the one for dielectric pinholes. Such pinholes are microscopic defects in insulators-like silicon dioxide, silicon nitride, quartz, and polyimide-which are used between the conductive layers of integrated circuit chips. These defects will cause short circuits between the conductors on different levels, thus causing chip failures. The area sensitive to the pinholes is the area where conductors cross each other. The sum of all such overlap areas on a chip is the pinhole critical area for that chip. The model for calculating the average number of failures has the form

Xi = AiDi (1)

where X i is the average number of failures or faults caused by a defect type indicated by the indices i. The quantity Ai is the critical area. The designations sensitive area and susceptible area have been used by some authors for the same connotation. The defect density is designated by Di and has the units of defects per unit area. Each defect mechanism has its own defect density. Quartz pinholes, for instance, are different from thin-oxide pinholes, and they will, therefore, have different defect densities. The index i will also have a different value for each of these.

Pinhole defect densities can be measured with relatively simple defect monitors. All that is needed is the insulator under test sandwiched between two conductive layers. Defect monitors of this type are made on special monitor wafers or some-


STAPPER et al.: IC YIELD STATISTICS

Both the process complexity and the increased length of timeresult in an increased likelihood that something will go wrongin the line. A manufacturer could, therefore, fmd most of hismanufacturing line full of useless product if he relied only onfailure analysis and a final test to tell him what is going on. Integrated circuit manufacturing lines, therefore, require monitoring techniques that can function as early warning systems.To make such monitors effective, it is necessary that their datacan be used to estimate the percentage of product that is or isnot defective. We have already given an example of this in thediscussion on gross yields. For random defects the situation issomewhat more complex. This is where random defect yieldmodels are needed. For example, such models are used withvisual inspection of photoresist patterns, or newly etched patterns. Inspectors have been trained to examine these patternsin order to count and classify the defective patterns that occur. Due to the complexity of modern integrated circuitchips, it is impossible for the inspector to tell whether the defects they observe will cause actual chip failures. The yield,therefore, cannot be directly obtained from these inspectiondata.

The problem is solved with engineering failure models thatdetermine the probability with which each defect type cancause a failure. This is known as the "probability of failure."It can be multiplied by the number of defects in the corresponding category to obtain the average number of failures orfaults per chip. This has to be done for each defect type. Failure models for different defects are described in the next section. The estimation of the yield for each defect type requiresone more step. This is done with the statistical models thatare the subject of subsequent sections [II] , [12] .

Conductors in integrated circuit chips are made with semiconductor diffusions, polycrystalline silicon, or metal. Missingor extra patterns of such conductors can be measured withelectronic defect monitors. Such monitors consist of serpentine or interdigitated patterns that are sensitive to specific defect types. An example of such a structure is shown in Fig. 4.It consists of two very long conductive lines which can betested for open circuits or missing conductive patterns. Extrapatterns or short circuits can be detected between the twolines. Failure models are needed to scale from the number offailures in a defect monitor to the number of failures expectedon the product. This result is then used in a statistical modelto estimate the equivalent product yield. The random defectyields on the bar chart in Fig. 3 were obtained with yieldmodel estimates from visual inspections and electronic defectmonitor data. The data from in-line visual inspection and defect monitors can be compared with failure analysis data collected over a long period. Results have shown that the threemeasurements can be in very good agreement when the rightmodels are used [I 2] .

FAILURE MODELS

The data in Fig. 3 show that gross yields account for 16.5percent of the yield losses. This contrasts with the 83.5 percent of the losses that are due to random defects. The randomdefects, therefore, cause five times more chips to fail than thegross defects. Data such as these are typical for most manufacturing environments. Random defect models are, therefore,an important factor in planning and controlling the integratedcircuit manufacturing yields.

The random defect model has to be broken up into two

455

H

(~................

a a

Fig. 4. A defect monitor consisting of two long conductors for detecting missing patterns or open circuits. The space between the linesis a short circuit detector for extra patterns.

parts. The first part is the theory that deals with the averagenumber of failures or faults that can be caused by a large number of different defect mechanisms. Several models developedfor this purpose will be described in this section of the paper.The second part of the random defect model is the statisticaldistribution of the number of faults per chip. The statisticsused are the topic of the next sections.

The simplest defect model is the one for dielectric pinholes.Such pinholes are microscopic defects in insulators-like silicon dioxide, silicon nitride, quartz, and polyimide-which areused between the conductive layers of integrated circuit chips.These defects will cause short circuits between the conductorson different levels, thus causing chip failures. The area sensitive to the pinholes is the area where conductors cross eachother. The sum of all such overlap areas on a chip is the pinhole critical area for that chip. The model for calculating theaverage number of failures has the form

(I)

where }..i is the average number of failures or faults caused bya defect type indicated by the indices i. The quantity Ai is thecritical area. The designations sensitive area and susceptiblearea have been used by some authors for the same connotation. The defect density is designated by D i and has the unitsof defects per unit area. Each defect mechanism has its owndefect density. Quartz pinholes, for instance, are differentfrom thin-oxide pinholes, and they will, therefore, have different defect densities. The index i will also have a differentvalue for each of these.

Pinhole defect densities can be measured with relatively simple defect monitors. All that is needed is the insulator undertest sandwiched between two conductive layers. Defect monitors of this type are made on special monitor wafers or some-

456 PROCEEDINGS OF THE BEE, VOL. 71, NO. 4, APRIL 1983

times in the kerfs on wafers with the product chips. Extensive studies of pinhole defect densities as a function of insulator thickness have been made in the Soviet Union, as, for instance, in the work of Kovchavtsev and Frantsuzov [ 131.

Scaling between the average number of faults in a test structure or defect monitor and the average number of faults in a product is straightforward. If the defects affect the monitor in the same way they affect the product, then the defect density for both will be the same. The ratio between the number of product faults and the number of monitor faults will, therefore, be the same as the ratio of critical areas. The average number of faults X,i in the product caused by a defect of type i can, therefore, be calculated with

X p i = XrniApilArni (2)

where Apt is the product critical area, Ami the monitor critical area, and Ami the average number of faults caused by the defect type i in the monitor.

Turley and Herman reported an interesting phenomenon that they observed when measuring pinhole defect densities [ 141. It appeared that their edge pinhole monitors, consisting of long overlapping metal lines, showed a higher incidence of failure than the parallel-plate structures. This suggested to them that there existed a pinhole defect mechanism that was length related. Such defects can be modeled with

X i = LiDi (3)

where Li is the critical length and Di the number of defects per unit length. Many pinhole models should consist of a combination of (2) and (3), as the data by Saito et al. suggest [ 15 1.

The model in (3) was also implied in the work of Ipri and Sarace, who evaluated yield of various conductors as a function of line length [ 161, [ 171. Monitors like the ones they described can be used to determine the defect densities in (1) and (3). Ipri and Sarace also studied yield as a function of the number of conductor crossovers and the number of contacts. A model for such a case can be expressed in terms of the number of crossovers or contacts Ni as

Xi = NiXoi (4)

where X o i is the average number of faults per crossover or contact.

Defects in the junctions area of diodes can cause such devices to conduct unwanted current when a reverse bias is applied. Currents like these are known as "junction leakage." The model in (2) has been used successfully for ten years at IBM by Stapper to model diode failures. In the strictest sense, however, this leakage is caused by defects in depletion layers. Since the depletion layer has both area and width, junction leakage should, therefore, be modeled with

In this case, we have a critical depletion-layer volume Vi and a defect density per unit volume Dl. In a junction leakage yield model for an entire chip, the critical volume will be the sum of the volume of all depletion layers on the chip. The depletion- layer width, with which these volumes are determined, must be the one that corresponds to the maximum reverse bias that will occur at each junction during normal chip operation.

The modeling of photo defects is more complex. This is caused by the varying sensitivity of photolithographic patterns

OF FAILURE PROBABILITY

a 2a+b 4a+3b (4

DEFECT SIZE x

PROBABILITY OF FAILURE

DEFECT SIZE x

6 ) Fig. 5. Probability of failure as a function of defect size. The curves

in (a) and (b) are analytically derived and correspond to the defect monitor in Fig. 4. The curve in (c) is for a complex design. Such curves are obtained by computer simulation.

t o defects of different size. The theory that we will describe here was developed from earlier work by Lawson [ 181, Den- nard [ 191, and Chang [ 201. The key to the photo defect model is the probability of failure, which we will designate by Oi(x), a function of defect size x . Typical probability-offailure curves are shown in Fig. 5. Notice that these curves show that very small defects cause no failure and, therefore, have a probability of failure equal to zero. For very large defects, the probability of failure is one, which implies that when defects of this size occur in the circuit they will always cause a failure. The probability-of-failure curves in Fig. 5(a) and (b) were analytically determined for the defect monitor shown in Fig. 4. The one in Fig. S(a) is for missing patterns or open circuits, while the curve in Fig. 5(b) is for short circuits or extra patterns. The probabilityaf-failure curve in Fig. 5(c) is typical for a more complex circuit. Computer simulation programs exist t o determine these curves for missing or extra patterns on each mask level of a chip. Such programs are particularly convenient t o use when the chips are laid out with computer-aided design techniques.

We can defme a critical area as a function of defect size by multiplying the probability of failure by the appropriate chip



where Li is the critical length and Di the number of defects perunit length. Many pinhole models should consist of a combination of (2) and (3), as the data by Saito et al. suggest [15].

The model in (3) was also implied in the work of Ipri andSarace, who evaluated yield of various conductors as a function of line length [16] , [17]. Monitors like the ones they described can be used to determine the defect densities in (1)and (3). Ipri and Sarace also studied yield as a function of thenumber of conductor crossovers and the number of contacts.A model for such a case can be expressed in terms of the number of crossovers or contacts Ni as

DEFECT SIZE x

DEFECT SIZE x

(b)

(a)

9(x)

PROBABILITYOF FAILURE

9(x)

PROBABILITYOF FAILURE

9(X)

PROBABILITY OFFAILURE

0.5

----------;:.--------

DEFECT SIZE x(c)

Fig. 5. Probability of failure as a function of defect size. The curvesin (a) and (b) are analytically derived and correspond to the defectmonitor in Fig. 4. The curve in (c) is for a complex design. Suchcurves are obtained by computer simulation.

(3)

(4)

times in the kerfs on wafers with the product chips. Extensivestudies of pinhole defect densities as a function of insulatorthickness have been made in the Soviet Union, as, for instance,in the work of Kovchavtsev and Frantsuzov [13] .

Scaling between the average number of faults in a test structure or defect monitor and the average number of faults in aproduct is straightforward. If the defects affect the monitor inthe same way they affect the product, then the defect densityfor both will be the same. The ratio between the number ofproduct faults and the number of monitor faults will, therefore, be the same as the ratio of critical areas. The averagenumber of faults Api in the product caused by a defect of typei can, therefore, be calculated with

Api = AmiApi/Ami (2)

where Api is the product critical area, Ami the monitor criticalarea, and Ami the average number of faults caused by the defect type i in the monitor.

Turley and Herman reported an interesting phenomenonthat they observed when measuring pinhole defect densities[14]. It appeared that their edge pinhole monitors, consistingof long overlapping metal lines, showed a higher incidence offailure than the parallel-plate structures. This suggested tothem that there existed a pinhole defect mechanism that waslength related. Such defects can be modeled with

In this case, we have a critical depletion-layer volume Vt and adefect density per unit volume Dt. In a junction leakage yieldmodel for an entire chip, the critical volume will be the sum ofthe volume of all depletion layers on the chip. The depletionlayer width, with which these volumes are determined, mustbe the one that corresponds to the maximum reverse bias thatwill occur at each junction during normal chip operation.

The modeling of photo defects is more complex. This iscaused by the varying sensitivity of photolithographic patterns

where AOi is the average number of faults per crossover orcontact.

Defects in the junctions area of diodes can cause such devices to conduct unwanted current when a reverse bias is applied. Currents like these are known as '~unction leakage."The model in (2) has been used successfully for ten years atIBM by Stapper to model diode failures. In the strictest sense,however, this leakage is caused by defects in depletion layers.Since the depletion layer has both area and width, junctionleakage should, therefore, be modeled with

Ai = ViDi· (5)

to defects of different size. The theory that we will describehere was developed from earlier work by Lawson [18], Dennard [19], and Chang [20]. The key to the photo defectmodel is the probability of failure, which we will designateby 8t (x), a function of defect size x. Typical probability-offailure curves are shown in Fig. 5. Notice that these curvesshow that very small defects cause no failure and, therefore,have a probability of failure equal to zero. For very large defects, the probability of failure is one, which implies that whendefects of this size occur in the circuit they will always cause afailUre. The probability-of-failure curves in Fig. 5(a) and (b)were analytically determined for the defect monitor shown inFig. 4. The one in Fig. 5(a) is for missing patterns or open circuits, while the curve in Fig. 5(b) is for short circuits or extrapatterns. The probability-of-failure curve in Fig. 5(c) is typicalfor a more complex circuit. Computer simulation programsexist to determine these curves for missing or extra patterns oneach mask level of a chip. Such programs are particularly convenient to use when the chips are laid out with computer-aideddesign techniques.

We can defIne a critical area as a function of defect size bymultiplying the probability of failure by the appropriate chip

STAPPER et 01.: IC YIELD STATISTICS 451

A RELATIVE PROBABILITY

\ \ \ \ \

0.625 1.25 1.875 2.5 3.125 3.75 4.375 5 5.625 6.25 6.875 7.5 8.125 8.75 9.375 10

DEFECT SIZE IN MICRONS

Fig. 6. The defect size distribution. The smooth distribution is deduced from monitor data. The stepped distribution is the result of visual inspections. Divergence between the two is caused by measurement inaccuracies.

or circuit area. Thus if A is the chip or circuit area, then AOi(x) is the critical area as a function of defect size. This quantity will have to be combined with a defect size distribution to calculate the average number of faults.

The defect size distribution can be determined with test sites like the ones described by Ipri and Sarace [ 161 . These authors used a number of serpentine lines with different widths, spaces, and lengths. Data from such monitors can be analyzed for defect size distributions, although Ipri and Sarace did not do so. The smooth curve in Fig. 6 was obtained from such data.

Visual inspections, like those described by Maeder et al. [ 1 1 1 , have also been used to this effect. Such measurements have produced the distribution with steps shown in Fig. 6. A divergence between these data and a continuous curve, also shown in the same T i e , can be seen for defects that are smaller than 5 pm. This is the result of increasing measurement inaccuracies when counting small defects visually. The falloff in the number of defects with sizes below 1.25 pm, however, is real. It results from the resolution limits of the photolithographic techniques. Small defects just could not be resolved.

Data of the size distribution can be approximated by a continuous probability distribution function. If, for a defect of type i, such a distribution is designated by hi(x) , and the average defect density by Di, then the defect size distribution as a function of defect size x is given by Dihi(x). This can now be combined with the critical area as a function of defect size by integration to obtain the number of faults

hi = lm Aei(x) Dihi(x) dx. (6)

Defining an average probability of failure

then leads to

x i = AD^.

Thus with the definition for the average critical area

Ai = giA

the photo defect problem is reduced to the simplicity of the pinhole model (1 ).

At this point, the reason for the use of what we have called faults should become clear. No matter how complicated or how simple the defect mechanism is, the ultimate defectrelated quantity we want to determine is the average number of faults h per chip or circuit. Any models that allow us to estimate the contributions to this quantity are useful. Fur- thermore, basic quantities such as defect densities per unit area, defects per unit length, defects per unit volume, and faults per contact or crossover can be measured with test structures. Yield modeling can, therefore, be approached scientifically. The only limits to such models are the statistical confidence limits on the data and the use of the correct statistics. The statistical theories for random faults are the subject of the rest of this paper.

AMATHEMATICAL BASIS FOR RANDOM FAULT THEORY

Most work in random defect yield modeling has been axiomatic. This had led to disputes in the literature about the correct model. Price maintained that integrated circuit defects should follow Bose-Einstein statistics [21] . Others thought they should follow Maxwell-Boltzmann statistics 1221, [231. An attempt by Hu [ 241 to derive a random defect yield model from a simple argument led him to conclude that yield models by Murphy [25 I , Okabe et 01. [ 261, Stapper [ 271, Turley and Herman [ 141, Bernard [ 281, and Paz and Lawson [ 291 were mathematically incorrect. This was a hard pill to swallow, especially since these models were the most successful ones for fitting actual data. We will try to end this dilemma in this paper by investigating the conditions that will lead to Poisson, generalized negative binomial, and binomial statistics for random defect yield models. It will be shown that under the right assumption, each one of these statistics is equally fundamental to yield theory. Therefore, the correct one should be the one that fits the data best.

A theory that appears particularly well suited for integrated circuit yield analysis is one that has been developed by Rogers for modeling the distribution of retail establishments in cities [301. Rogers approached his problem by dividing city maps into squares and counting the number of shops or stores of a given type that were located in each square. An easy translation can be made from Rogers’ work by realizing that his squares in city maps correspond to the chips on a wafer, the stores correspond to faults or failures, and the type of store corresponds to the type of defect causing the failure.

The objective of the model is to describe mathematically how the distribution of the number of faults per chip is formed during the manufacturing process. The distribution is designated by p(x , t) , where there are x faults per chip at time t. It has associated with it a distribution generating function C(s; t ) defined by

G(s; t ) = p ( x , t ) sx m

x =o

where s is a dummy variable. This function derives its name



RELATIVEPROBABILITY

0.625 1.25 1.675 2.5 3.125 3.75 4.375 5 5.625 6.25 6.875 7.5 8.125 8.75 9.375 10

DEFECT SIZE IN MICRONS

Fig. 6. The defect size distribution. The smooth distribution is deduced from monitor data. The stepped distribution is the result ofvisual inspections. Divergence between the two is caused by measurement inaccuracies.

457

Thus with the defmition for the average critical area

AI = 6j A

the photo defect problem is reduced to the simplicity of thepinhole model (I ).

At this point, the reason for the use of what we have calledfaults should become clear. No matter how complicated orhow simple the defect mechanism is, the ultimate defectrelated quantity we want to determine is the average numberof faults A per chip or circuit. Any models that allow us toestimate the contributions to this quantity are useful. Furthermore, basic quantities such as defect densities per unitarea, defects per unit length, defects per unit volume, andfaults per contact or crossover can be measured with test structures. Yield modeling can, therefore, be approached scientifically. The only limits to such models are the statistical confidence limits on the data and the use of the correct statistics.The statistical theories for random faults are the subject of therest of this paper.

or circuit area. Thus if A is the chip or circuit area, thenA8 j (x) is the critical area as a function of defect size. Thisquantity will have to be combined with a defect size distribution to calculate the average number of faults.

The defect size distribution can be determined with test siteslike the ones described by Ipri and Sarace [16]. These authorsused a number of serpentine lines with different widths,spaces, and lengths. Data from such monitors can be analyzedfor defect size distributions, although Ipri and Sarace did notdo so. The smooth curve in Fig. 6 was obtained from suchdata.

Visual inspections, like those described by Maeder et al.[Ill , have also been used to this effect. Such measurementshave produced the distribution with steps shown in Fig. 6. Adivergence between these data and a continuous curve, alsoshown in the same fIgure, can be seen for defects that aresmaller than 5 p.m. This is the result of increasing measurement inaccuracies when counting small defects visually. Thefalloff in the number of defects with sizes below 1.25 p.m,however, is real. It results from the resolution limits of thephotolithographic techniques. Small defects just could not beresolved.

Data of the size distribution can be approximated by a continuous probability distribution function. If, for a defect oftype i, such a distribution is designated by hl(X), and the average defect density by DI , then the defect size distribution as afunction of defect size x is given by Djhj(x). This can now becombined with the critical area as a function of defect size byintegration to obtain the number of faults

A MATHEMATICAL BASIS FOR RANDOMFAULT THEORY

Most work in random defect yield modeling has been axiomatic. This had led to disputes in the literature about the correct model. Price maintained that integrated circuit defectsshould follow Bose-Einstein statistics [21]. Others thoughtthey should follow Maxwell-Boltzmann statistics [22], [23].An attempt by Hu [24] to derive a random defect yield modelfrom a simple argument led him to conclude that yield modelsby Murphy [25], Okabe et al. [26], Stapper [27], Turley andHerman [14], Bernard [28], and Paz and Lawson [29] weremathematIcally incorrect. This was a hard pill to swallow,especially since these models were the most successful ones forfItting actual data. We will try to end this dilemma in thispaper by investigating the conditions that will lead to Poisson,generalized negative binomial, and binomial statistics for random defect yield models. It will be shown that under the rightassumption, each one of these statistics is equally fundamentalto yield theory. Therefore, the correct one should be the onethat fits the data best.

A theory that appears particularly well suited for integratedcircuit yield analysis is one that has been developed by Rogersfor modeling the distribution of retail establishments in cities[30]. Rogers approached his problem by dividing city mapsinto squares and counting the number of shops or stores of agiven type that were located in each square. An easy translation can be made from Rogers' work by realizing that hissquares in city maps correspond to the chips on a wafer, thestores correspond to faults or failures, and the type of storecorresponds to the type of defect causing the failure.

The objective of the model is to describe mathematicallyhow the distribution of the number of faults per chip isformed during the manufacturing process. The distribution isdesignated by p(x, t), where there are x faults per chip at timet. It has associated with it a distribution generating functionG(s; t) defined by

DefIning an average probability of failure

6j = 100

8j(x) hl(x) dxo

then leads to

(6)

(7)00

G(s; t) = L p(x, t) s:X:x =0

(9)

(8) where s is a dummy variable. This function derives its name

458 PROCEEDINGS OF THE IEEE, VOL. 71, NO. 4, APRIL 1983

from the relationship to the distribution function p ( x , t ) as follows:

It also has the property that the yield Y is given by

Y = C(0; t ) = p ( 0 , t ) (1 1)

which implies that the distribution generating function C(s; t) is just as closely related to the integrated circuit yield Y as the fault distribution p ( x , t).

Rogers showed that the probability generating function G(s; r) must satisfy a different equation. This equation is derived in Appendix I. It has the form

where f(x, r) is a probability distribution function that describes how the faults are formed on a chip during the manufacturing process. The quantity f ( x , r) dt is defined as the probability that, during the time interval r t o r + dr, a fault will occur on a chip which already has x faults caused by defects. The distribution generating function C(s; r) and the fault distribution p ( x , t ) will depend completely on the nature of this function f ( x , r). Its meaning will become clearer in the sections that follow.

POISSON STATISTICS: A RANDOM FAULT MODEL The objective of this paper is to find out how yield statistics

are influenced by different assumptions for the probability distribution function of fault formation f(x, r). The f m t assumption that will be investigated is the condition that the probability of a fault occurring on a chip is completely independent of the number of faults already on that chip. In that case

f(x, r) = f ( r ) (13)

and (1 2) becomes

This is a firstarder linear differential equation with the solution c(s; r) = eNS-1) (15)

where

X = J * f ( r ) d(r). (16)

The results in (15) is the probability distribution generating function for Poisson statistics. It must, therefore, be concluded that these statistics hold when fault formation in the factory is independent of the number of faults already on the chip. The yield in this case can be expressed by

Y = e - A . (17)

This result has been used as a starting point for yield theory by Hofstein and Heiman [ 3 1 1, Murphy [25], Lawson [ 181, and more recently by Saito et (12. [ 151, [32]. The formula for the

fault distribution associated with (1 7) and expressions for the fault mean and the variance are given in Appendix 11.

COMF'ONENTS OF THE R A N D O M DEFECT YIELD

The integral in (1 6) shows that the rate at which faults accumulate on the wafers in time does not have to be constant. It is only the sum total, expressed by the integral, that leads to the average number of faults A.

It has been proven very useful t o break integral (16) up into the sum of a number of integrals for different time periods. Each such time period is made to correspond to a specific process step. The integral that corresponds to such a step, therefore, will have a value equal to the average number of faults per chip that are collected at that process step. For m process steps this gives

X = Xi m

i -1

where the average number of faults collected during process step i can be calculated with

X i = I" f ( r ) dr. (1% t i - I

This process step starts at time and is completed at time ti. With summation (1 8), the yield expression becomes

Y = exp (- 2 X i ) i = 1

i = 1

It is possible to associate a yield Yi that corresponds to the average number of faults for process step i . Thus if

the total yield

m Y = n Yi

~~

i = 1

is now expressed in terms of its yield components. This concept forms the basis for yield control in integrated circuit manufacturing. Elaborate schemes with visual inspections and defect monitor techniques are often employed to estimate the number of faults and the yield of these components [ 1 11, [121, [141, [271, [281, [321-[341.

MIXED AND COMPOUND POISSON STATISTICS

The integral (1 9) for obtaining the average number of faults per chip Ai has another inferesting consequence. Consider the yield Yi for the ith defect type. If this yield is to be estimated for a given period of time, say a month, then different values of and ti will occur for each batch. The function f i ( r ) must, therefore, be appropriately time shifted for each batch. However, will the value of Xi then be the same for each batch? Experimental evidence suggests that it will not. Batch-tobatch yield variations are usually far greater than would be expected statistically. It has also been shown experimentally



from the relationship to the distribution function p(x, t) asfollows:

which implies that the distribution generating function G(s; 0is just as closely related to the integrated circuit yield Y as thefault distribution p(x, t).

Rogers showed that the probability generating functionG(s; t) must satisfy a different equation. This equation is derived in Appendix I. It has the form

fault distribution associated with (17) and expressions for thefault mean and the variance are given in Appendix II.

COMPONENTS OF THE RANDOM DEFECT YIELD

The integral in (16) shows that the rate at which faults accumulate on the wafers in time does not have to be constant.It is only the sum total, expressed by the integral, that leads tothe average number of faults A-

It has been proven very useful to break integral (16) up intothe sum of a number of integrals for different time periods.Each such time period is made to correspond to a specific process step. The integral that corresponds to such a step, therefore, will have a value equal to the average num ber of faultsper chip that are collected at that process step. For m processsteps this gives

(18)m

A= L A;;=1

(10)

(12)

(11)

o coa G(I; 0 = (I - 1) L p(x, t) f(x, t) sXt x=o

_ ~ oXG(I; t) Ip(x, t)-, aJC •

x. of .r=o

It also has the property that the yield Y is given by

Y =G(O; t) =p(O, t)

POISSON STATISTICS: A RANDOM FAULT MODEL

The objective of this paper is to find out how yield statisticsare influenced by different assumptions for the probabilitydistribution function of fault formation f(x, 0. The first assumption that will be investigated is the condition that theprobability of a fault occurring on a chip is completely independent of the number of faults already on that chip. In thatcase

where f(x, t) is a probability distribution function that describes how the faults are formed on a chip during the manufacturing process. The quantity f(x, 0 dt is defined as theprobability that, during the time interval t to t + dt, a faultwill occur on a chip which already has x faults caused by defects. The distribution generating function G(s; 0 and thefault distribution p(x, t) will depend completely on the natureof this function f(x, t). Its meaning will become clearer in thesections that follow.

where the average number of faults collected during processstep i can be calculated with

This process step starts at time t; -1 and is completed at timet;. With summation (18), the yield expression becomes

(19)

(20)= Ii e-~;.i= I

It;

Ai = f(T) dT.ti -1

Y= exp (- 1. Ai);=1

It is possible to associate a yield Y; that corresponds to theaverage number of faults for process step i. Thus if

Y; = e-~; (21)(13)f(x, 0 = f(O

and (12) becomes

oG(s; t)ot = (s - l) f(t) G(s; 0. (14)

the total yield

mY= n Yi

i= I

(22)

This is a first~rder linear differential equation with the solution

G(s;O=e~(.r-I) (15)

where

(16)

The results in (15) is the probability distribution generatingfunction for Poisson statistics. It must, therefore, be concluded that these statistics hold when fault formation in thefactory is independent of the number of faults already on thechip. The yield in this case can be expressed by

Y=e-~. (17)

This result has been used as a starting point for yield theory byHofstein and Heiman [311, Murphy [25], Lawson [18], andmore recently by Saito et al. [151, [321. The formula for the

is now expressed in terms of its yield components. This concept forms the basis for yield control in integrated circuitmanufacturing. Elaborate schemes with visual inspections anddefect monitor techniques are often employed to estimate thenumber of faults and the yield of these components [II],[12], [14], [27], [28], [321-[341.

MIXED AND COMPOUND POISSON STATISTICS

The integral (19) for obtaining the average number of faultsper chip A; has another inferesting consequence. Consider theyield Yi for the ith defect type. If this yield is to be estimatedfor a given period of time, say a month, then different valuesof t;-1 and t; will occur for each batch. The function f;(T)must, therefore, be appropriately time shifted for each batch.However, will the value of A; then be the same for each batch?Experimental evidence suggests that it will not. Batch-tobatch yield variations are usually far greater than would be expected statistically. It has also been shown experimentally

STAPPER et al.: IC YIELD STATISTICS 459

that there exist wafer-to-wafer variations [ 271, [ 291 , and over the wafer variations [ 231, [ 291, [ 331 of the values of the average number of faults per chip Xi. This suggests that the function f ( t ) continually changes in semiconductor processes. The picture, therefore, appears far more complex than suggested by (1 9). In fact, the yield for the ith defect type should really be expressed as

where there are m regions. Each one of these regions has its own average number of faults per chip Xi1 as well as a constant ci. The value of ci equals the surface area of region j divided by the total wafer surface area considered.

The number of regions can become very large in (23). For example, in one of the factories known to us, wafers are divided up into nine predesignated regions. The average number of faults per chip for each region is determined by visual inspection and failure analysis. For 1000 wafers, the yield model in (23) will have 9000 terms for each defect type. Yield models with as many as 30 random defect types do exist, thus requiring a yield model with 270 000 terms. This makes it prohibitively difficult to do yield scaling between products and to project the yield for future products.

This problem can be solved by using mixed or compound Poisson statistics. For instance, the sum in (22) can be approximated as infinite. It then is possible to approximate the constants ci in (23) by probabilities of discrete distributions. If a linear relationship is assumed between the index j and the values of Xii, a set of yield equations, given in Appendix I11 can be derived. These equations have not yet found any use in the literature. Nevertheless, Armstrong and Saji found that some of the distributions, associated with these yield equations, gave excellent agreement with actual fault, defect, and contamination distributions.

Another method for dealing with a large number of terms was used by Feller [351, [361. The sum in (23) can be approximated by an integral [ 371. The yield is then given by

OD

Yi = 1 e-;*‘g(Xi) d& (24)

where &Xi) is a probability distribution function for faults per chip that are caused by defect types designated by i. This distribution is known as the compounder, while the statistics associated with (24) are known as compound Poisson statistics. The result is basically the same as a yield model proposed by Murphyin 1964 [251.

Murphy used a triangular and a uniform distribution for &Xi). The yield formulas he derived this way are given in Ap- pendix 111. Using these results, Murphy showed that the yield of larger or more complex chips would be higher than was expected from plain Poisson statistics. His prediction has since been proven correct, but his formulas have not found much use in subsequent theories. This is primarily caused by the low values that his fault distributions have for the ratio of standard deviation to the mean, also known as the coefficient of variation. Actual data subsequently shown by Seeds [38] , [39] , Ansley [401, Moore [411, Stapper [271, [331, (421, [431, and Paz and Lawson [291 suggested higher values for this

ratio, leading to even more optimistic yields for large chips than Murphy had anticipated.

A more suitable compounder for use in (24) was originally proposed by Okabe, Nagata, and Shimada [26] . They used Erlang and gamma distributions and obtained a yield expression of the form

The parameter ai in this formula depends on the spread of the fault distribution caused by defects of the type indicated by index i. The coefficient of variation in this case is equal t o

The formula in (25) was found to give a good fit t o data by Stapper et al. [271, 1331, [42] , [43] , Turley et al. [ 141, and Paz and Lawson [ 291.

The statistics associated with (25) were first developed by Greenwood and Yule in the theory of contagion [44] . They were rediscovered by Polya-Eggenberger under whose name the associated distribution is often quoted [45] , This distribution is also known as the negative binomial distribution. Its formula, along with the mean and variance, is given in Appendix 11.

In a strict sense, the negative binomial distribution is only defined for integer values of ai 2 1. The yield model in (25) has no such restrictions and is well defined for all real values of a > 0. We will, therefore, use the nomenclature “generalized negative binomial distribution” and “generalized negative binomial statistics” for this model in this paper.

The generalized negative binomial distribution can also be derived in other ways. The method that we used in the previous sections for deriving Poisson statistics is also applicable in this case. The way this is done is the topic of the next sections.

DEFECT AND FAULT CLUSTERING IN SEMICONDUCTOR MANUFACTURING

To derive Poisson statistics it had to be assumed that the probability distribution function of fault formation f (x , t ) varied only as a function of time. To ascertain the real nature of this function in a manufacturing process is difficult. The major reason for this is that the faults are not detected until the chips are completed and tested at the end of the process. There are, however, in-line visual inspections of the newly developed and etched photo patterns. Inspectors catagorize and count the defective patterns. According to Maeder et al. [ 111, as well as the failure models previously described in this paper, the number of defects appear t o be directly proportional to the number of faults on a chip. It seems, therefore, reasonable to assume that the nature of the formulation of the defective pattern is the same as the nature of fault formation.

Photo pattern inspection has given engineers and technicians the impetus t o track down the sources of defects. In most cases the random defects are caused by minute particles. These particles are deposited on wafers in various process steps. They are carried in the gases, vapors, solvents, photoresists, and other chemicals that are used to manufacture integrated circuits. All kinds of filtering techniques are used to keep the number of such particles low. Furthermore, to assure that the particular “contamination” does not get out of hand, manufacturers have installed particle counting tools.

Particles can be seen on wafers with high-intensity light beams that are obliquely reflected from the wafer surface.

1 1 6


(23)


that there exist wafer-to-wafer variations [27J, [29J, and overthe wafer variations [23], [29J, [33J of the values of the average number of faults per chip Ai. This suggests that the function f(t) continually changes in semiconductor processes. Thepicture, therefore, appears far more complex than suggestedby (19). In fact, the yield for the ith defect type should reallybe expressed as

~ -AifYi = £.J cfe

f=1

where there are m regions. Each one of these regions has itsown average number of faults per chip Aif as well as a constantcf. The value of cf equals the surface area of region j dividedby the total wafer surface area considered.

The number of regions can become very large in (23). Forexample, in one of the factories known to us, wafers are divided up into nine predesignated regions. The average numberof faults per chip for each region is determined by visual inspection and failure analysis. For 1000 wafers, the yieldmodel in (23) will have 9000 terms for each defect type.Yield models with as many as 30 random defect types doexist, thus requiring a yield model with 270 000 terms. Thismakes it prohibitively difficult to do yield scaling betweenproducts and to project the yield for future products.

This problem can be solved by using mixed or compoundPoisson statistics. For instance, the sum in (22) can be approximated as infinite. It then is possible to approximate theconstants cf in (23) by probabilities of discrete distributions.If a linear relationship is assumed between the index j and thevalues of Ai/> a set of yield equations, given in Appendix IIIcan be derived. These equations have not yet found any use inthe literature. Nevertheless, Armstrong and Saji found thatsome of the distributions, associated with these yield equations, gave excellent agreement with actual fault, defect, andcontamination distributions.

Another method for dealing with a large number of termswas used by Feller [35J, [36]. The sum in (23) can be approximated by an integral [37]. The yield is then given by

(24)

where g(Ai) is a probability distribution function for faults perchip that are caused by defect types designated by i. This distribution is known as the compounder, while the statistics associated with (24) are known as compound Poisson statistics.The result is basically the same as a yield model proposed byMurphy in 1964 [25 J .

Murphy used a triangular and a uniform distribution forg(Ai). The yield formulas he derived this way are given in Appendix III. Using these results, Murphy showed that the yieldof larger or more complex chips would be higher than was expected from plain Poisson statistics. His prediction has sincebeen proven correct, but his formulas have not found muchuse in subsequent theories. This is primarily caused by the lowvalues that his fault distributions have for the ratio of standarddeviation to the mean, also known as the coefficient of variation. Actual data subsequently shown by Seeds [38J, [39],Ansley [40], Moore [41], Stapper [27], [33], [42], [43],and Paz and Lawson [29J suggested higher values for this

459

ratio, leading to even more optimistic yields for large chipsthan Murphy had anticipated.

A more suitable compounder for use in (24) was originallyproposed by Okabe, Nagata, and Shimada [26J. They usedErlang and gamma distributions and obtained a yield expression of the form

(25)

The parameter Cti in this formula depends on the spread of thefault distribution caused by defects of the type indicated byindex i. The coefficient of variation in this case is equal toI/VCii.

The formula in (25) was found to give a good fit to data byStapper et al. [27], [33], [42], [43], Turley etal. [14], andPaz and Lawson [29].

The statistics associated with (25) were first developed byGreenwood and Yule in the theory of contagion [44]. Theywere rediscovered by Polya-Eggenberger under whose namethe associated distribution is often quoted [45]. This distribution is also known as the negative binomial distribution.Its formula, along with the mean and variance, is given inAppendix II.

In a strict sense, the negative binomial distribution is onlydermed for integer values of Cti ~ 1. The yield model in (25)has no such restrictions and is well defined for all real values ofCt> O. We will, therefore, use the nomenclature "generalizednegative binomial distribution" and "generalized negative binomial statistics" for this model in this paper.

The generalized negative binomial distribution can also bederived in other ways. The method that we used in the previous sections for deriving Poisson statistics is also applicable inthis case. The way this is done is the topic of the next sections.

DEFECT AND FAULT CLUSTERING IN

SEMICONDUCTOR MANUFACTURING

To derive Poisson statistics it had to be assumed that theprobability distribution function of fault formation f(x, t)varied only as a function of time. To ascertain the real natureof this function in a manufacturing process is difficult. Themajor reason for this is that the faults are not detected untilthe chips are completed and tested at the end of the process.There are, however, in-line visual inspections of the newly developed and etched photo patterns. Inspectors catagorize andcount the defective patterns. According to Maeder et al. [11 J,as well as the failure models previously described in this paper,the number of defects appear to be directly proportional tothe number of faults on a chip. It seems, therefore, reasonableto assume that the nature of the formulation of the defectivepattern is the same as the nature of fault formation.

Photo pattern inspection has given engineers and techniciansthe impetus to track down the sources of defects. In mostcases the random defects are caused by minute particles. Theseparticles are deposited on wafers in various process steps.They are carried in the gases, vapors, solvents, photoresists,and other chemicals that are used to manufacture integratedcircuits. All kinds of filtering techniques are used to keep thenumber of such particles low. Furthermore, to assure thatthe particular "contamination" does not get out of hand,manufacturers have installed particle counting tools.

Particles can be seen on wafers with high-intensity lightbeams that are obliquely reflected from the wafer surface.


Q 0 . .* . . . . ..*

.. Fig. 7. Particle locations on ‘Wrty” wafers show a tendency towards

clustering.

This is sometimes known as “bright light” inspection [ 121. Particles on the wafer scatter the light and can thus be counted by operators or with electronic detection techniques. The six wafers in F i g . 7 show the particle locations on each wafer for a somewhat “dirty” process. It is clear that the particles on these wafers are clustered. This is typical for semiconductor manufacturing processes, and clustered faults and defects have been described in detail in the literature [29], 1331, [37] - [391, [411.

The clustering of particles is believed to be caused by aggregates of particles that have collected in the manufacturing machinery. When shaken loose by vibrations, pressure changes, or gas flow changes, these clumps of particles will form clouds in the gasses or liquids used for processing. Where such clouds reach the wafer surface, particles will be clustered.

There are other reasons for clustering. Between process steps, wafers are often carried in plastic boxes. On the inside of these boxes are grooves similar to those in a slide projector tray. This allows the wafers t o be slid into the box on edge and parallel t o each other. Similar modes of wafer positioning are also used in some of the processing tools, where such carriers are known as “boats.” Dust particles can approach wafers in such containers from only one side. Even when such particles are uniformly suspended, they are electrostatically attracted to the nearest edge of the wafer. This leads to clustering near the edge at the open side of the carrier. Edge clustering of defects and chip failures has been a widely observed phenomenon in semiconductor manufacturing [ 231 , [ 291, [331, [ M I , [391, [461, [471.

Clustering can be modeled with the probability distribution function of fault formation f(x, r). When a cloud of particles lands on a wafer, the particles will not all land at the same time. This holds, also, for particles entering the open side of a wafer carrier. There will probably be a lead particle first. The rest, if any, will follow. This implies that if one particle has landed on a chip, the probability that other particles will follow is high. If two particles have landed on the chip, the probability of more following is even greater since the likelihood has increased that the chip is in the path of a particle cloud, or near’ the open side of a carrier. A chip without any particles on it and not in the path of the cloud, or near the open side of a box, will have a low probability for picking up any particles. It appears, therefore, that this probability of particles landing on a chip depends on the number of particles that are already there.

Let the number of faults, defects, and particles on a chip all be directly proportional t o each other. It then follows that the probability for a fault occuring on a chip must be related to the number of faults already on that chip, the same as for particles. For a specific process step where defects of a given type are formed, the probability of faults occurring can be approximated to be independent of time. This probability will then depend only on the number of faults already on the chip if clustering takes place.

A CLUSTER MODEL: GENERALIZED NEGATIVE BINOMIAL STATISTICS

A statistical yield model can be derived with the assumption that the probability of a fault occurring on a chip is independent of time and depends only on the number of faults already on the chip. The simplest dependency to assume is a linear one. If the defects causing the faults are indicated by a subscript i, the probability density function of fault formation is then given by

f i (x i , r) = ci + bixi (ci, bi > 0) (26)

where ci and bi are constants and xi is the number of faults present on the chip at time t . Under this condition, (23) becomes

a a - C(S; t ) = (S - 1) [ c i c ( s ; t ) + bis - G(s; r)l . (27) at as

This has the solution

~ ( s ; r) = [exp (b i t ) - {exp (b i t ) - 1) SI ( 2 8 4 -ci/bi

or

~ ( s ; t ) = (1 + (1 - s) Ai/ai)-ai (28b)

where

ai = ci/bi (29)

Xi = {exp (bit) - 1) ci/bi. (30)

Equation (28) is the probability generating function of the generalized negative binomial distribution. The corresponding yield formula is given by

yi = (1 + Xi/ai)-ai (25)

which is the same as the one derived in a previous section. The preceding derivation was based on the assumption that

the probability distribution function of fault formation was directly proportional t o the number of faults already on a chip. No doubt, the real situation in a manufacturing line is more complex. Unfortunately, until now, no analytical solutions to this problem have been found for polynomial or other functional dependencies of xi in f i ( x i , r). It is fortunate, however, that the statistics and yield formula we derived here are often good approximations to the actual yield situation [ 141, [271, [291, [331, [421, [431.

It has been pointed out by Rogers [301 that the difference between Poisson statistics and generalized negative binomial statistics is the clustering that is taken into account. The symbol ai in (25) is the clustering parameter. Low values of ai are needed to model severe clustering. When ai approaches infmity, ( 2 5 ) will approach e-ki , which is the yield of the random defect model in (21). In that case, there is no clustering. Val-



(26)

(29)

(30)

(28b)

crj = Ci/bi

Aj = {exp (bit) - I} cj/bj.

where

or

This has the solution

G(s; t) = [exp (bit) - {exp (bit) - I} sfCj/bj (28a)

where ci and bi are constants and Xi is the number of faultspresent on the chip at time t. Under this condition, (23)becomes

Let the number of faults, defects, and particles on a chip allbe directly proportional to each other. It then follows thatthe probability for a fault occuring on a chip must be relatedto the number of faults already on that chip, the same as forparticles. For a specific process step where defects of a giventype are formed, the probability of faults occurring can be approximated to be independent of time. This probability willthen depend only on the number of faults already on the chipif clustering takes place.

A CLUSTER MODEL: GENERALIZED NEGATIVEBINOMIAL STATISTICS

A statistical yield model can be derived with the assumptionthat the probability of a fault occurring on a chip is independent of time and depends only on the number of faults alreadyon the chip. The simplest dependency to assume is a linearone. If the defects causing the faults are indicated by a subscript i, the probability density function of fault formation isthen given by

a aat G(s; t) = (s - 1) [CiG(S; t) + biS as G(s; t)]. (27)

Equation (28) is the probability generating function of thegeneralized negative binomial distribution. The correspondingyield formula is given by

Yj = (l + Aj/crj)-OIj (25)

which is the same as the one derived in a previous section.The preceding derivation was based on the assumption that

the probability distribution function of fault formation wasdirectly proportional to the number of faults already on achip. No doubt, the real situation in a manufacturing line ismore complex. Unfortunately, until now, no analytical solutions to this problem have been found for polynomial or otherfunctional dependencies of Xi in [j(Xj, t). It is fortunate, however, that the statistics and yield formula we derived here areoften good approximations to the actual yield situation [14] ,[27], [29], [33], [42], [43].It has been pointed out by Rogers [30] that the difference

between Poisson statistics and generalized negative binomialstatistics is the clustering that is taken into account. The symbol crj in (25) is the clustering parameter. Low values of cri areneeded to model severe clustering. When crj approaches infmity, (25) will approach e-71.i, which is the yield of the randomdefect model in (21). In that case, there is no clustering. Val-

oFig. 7. Particle locations on "dirty" wafers show a tendency towards

clustering.

This is sometimes known as "bright light" inspection [12].Particles on the wafer scatter the light and can thus be countedby operators or with electronic detection techniques. The sixwafers in Fig. 7 show the particle locations on each wafer fora somewhat "dirty" process. It is clear that the particles onthese wafers are clustered. This is typical for semiconductormanufacturing processes, and clustered faults and defects havebeen described in detail in the literature [29], [33], [37][39], [41].

The clustering of particles is believed to be caused by aggregates of particles that have collected in the manufacturing machinery. When shaken loose by vibrations, pressure changes,or gas flow changes, these clumps of particles will form cloudsin the gasses or liquids used for processing. Where such cloudsreach the wafer surface, particles will be clustered.

There are other reasons for clustering. Between processsteps, wafers are often carried in plastic boxes. On the insideof these boxes are grooves similar to those in a slide projectortray. This allows the wafers to be slid into the box on edgeand parallel to each other. Similar modes of wafer positioningare also used in some of the processing tools, where such carriers are known as "boats." Dust particles can approach wafers in such containers from only one side. Even when suchparticles are uniformly suspended, they are electrostatically attracted to the nearest edge of the wafer. This leads to clustering near the edge at the open side of the carrier. Edge clustering of defects and chip failures has been a widely observedphenomenon in semiconductor manufacturing [23], [29],[33], [38], [39], [46], [47].

Clustering can be modeled with the probability distributionfunction of fault formation [(x, t). When a cloud of particleslands on a wafer, the particles will not all land at the sametime. This holds, also, for particles entering the open side of awafer carrier. There will probably be a lead particle first. Therest, if any, will follow. This implies that if one particle haslanded on a chip, the probability that other particles willfollow is high. If two particles have landed on the chip, theprobability of more following is even greater since the likelihood has increased that the chip is in the path of a particlecloud, or near" the open side of a carrier. A chip without anyparticles on it and not in the path of the cloud, or near theopen side of a box, will have a low probability for picking upany particles. It appears, therefore, that this probability ofparticles landing on a chip depends on the nUm ber of particlesthat are already there.

STAPPER et al.: IC YIELD STATISTICS 46 1

ues from 0.05 to infinty have been used in practice to model actual integrated circuit yields for different defects. It is the simplicity by which clustering is modeled in this approach that has made it useful. It also has reduced the need for earlier and more complex cluster theories as well as simulation techniques 1231, [471-[491.

Thus far, the cluster model in this paper has been described only for faults that are caused by particles. There are other random integrated circuit failures that are not caused by particles. For instance, the bipolar transistors used in integrated circuits are usually plagued by so-called "pipes." Pipes are enhanced emitter diffusions along dislocation lines or stacking faults in the silicon crystal lattice of the wafer. These defects often result in short circuits between the transistor emitters and collectors. The dislocation lines or stacking faults are caused by wafer stresses that result from temperature gradients when the wafers are heated or cooled in very-high-temperature processing steps. These stresses appear to be very nonuniformly distributed within wafers. The result is that pipes are usually severely clustered, as has been reported in the work of Paz and Lawson [ 291. These two authors also found that the random pipe failures could be modeled with the generalized negative binomial model.

Excess reverse current in reverse-biased semiconductor diodes is another failure that is usually caused by defects in the silicon crystal lattice. This phenomenon is known as junction leakage. These leakage defects have also been found to cluster. Unpublished work by Stapper has shown that generalized negative binomial statistics are applicable in this case as well.

If every defect mechanism were similarly subjected to clustering, then (25) would be a model for each defect type. As long as the faults caused by different process steps are independent, the total random defect yield will be given by

where there are m defect types, each one with its own average number of faults Xi and clustering parameter ai. In the next section it will be shown what happens to (31) when the faults caused by one process step do depend on the number of faults already on the chip from a previous process step.

Sredni [ 501 has shown that yield expression (2 1) corresponding to Poisson statistics, as well as (25) for generalized negative binomial statistics, could be obtained with a model building technique described by Box and Cox [ 5 1 1. This method led directly to either yield model, depending only on the data. Similarly, the method used in this paper leads directly to a Poisson distribution or generalized negative binomial distribution. In our case, the function that describes the way faults collect during the manufacturing process determines which type of statistics is appropriate. This implies that the generalized negative binomial distribution is just as fundamental t o yield modeling as the Poisson distribution, something that was not clear from the compounding process used earlier in this paper. Some uncertainty of the mathematical correctness of the generalized negative binomial model for yield modeling has been voiced previously in the literature [24], [37], [52] - [54]. It should be clear from the approach used in here, as well as from Sredni's method, that there is no need for concern.

BIVARIATE DISTRIBUTION: AN INTERACTIVE MODEL

The yield modeling approach for clustered defects and faults of the previous section can be extended to model the yield for faults in a process step caused by defects from a preceding process step. This occurs, for instance, when minute dirt particles in one of the oxide layers cause not only oxide pinholes, but also broken metallization patterns on top of it. Let the oxide pinhole faults be indicated by xi , and the probability of a fault occurring on a chip during the oxide growth process be given by

f i ( x i , t ) = ci + b p i ( c i , bi > 0). (32)

The oxide pinholes will then satisfy the yield equations and conditions given in the previous section. Furthermore, according to (A14) in Appendix 11, the distribution for the number of faults per chip is given by

where ai and X i are defined by (29) and (30). For the second fault type, the missing metal patterns, the

probability of a fault occurring during the subsequent process steps will depend on the number of faults x i caused by the previous step, as well as the number of faults xi caused by the process step under consideration. If a simple linear relationship is assumed, the probability for a fault occurring can be written as

where ci, bi, and bii are constants. When the probability function (34) is used in (1 2), a differ-

ential equation results, similar t o (27) for the case of generalized negative binomial statistics. This differential equation has the solution

(35) or

where

ai = cj/bi (37)

Xi = (e I I - 1) bi/ci (38) b 't'

'Yii = bji/bk (39)

It can be shown by substitution of constants that the probability generating function in (36) corresponds to the distribution

(40)

The probability of having xi faults of type i and xi faults of type j is given by

P(Xi, X i ) = P(XjlXi) P(Xl). (41)

Therefore, by use of (33) and (40)


STAPPER et ",.: IC YIELD STATISTICS 461

(40)

The probability of having Xj faults of type i and Xj faults oftype j is given by

(41)

(34)

(36)G(Sj; tjlSj) = {I + (1 - Sj) Aj/aj}-(aj+CIjjxj)

where

or

P(Xj, Xj) =P(xjlxj) P(Xj).

Therefore, by use of (33) and (40)

where Cj, bj, and bjj are constants.When the probability function (34) is used in (12), a differ

ential equation results, similar to (27) for the case of generalized negative binomial statistics. This differential equation hasthe solution

G(Sj; tjlx j) = {exp (bj tj) - [exp (bj tj) - 1] Sj}-(Cj + bjjxj)/bj

(35)

aj = cj/bj (37)b·t·

Aj = (e / / - 1) bj/cj (38)

aji = bji/bj. (39)

It can be shown by substitution of constants that the probability generating function in (36) corresponds to the distribution

r(ajjxj + aj + Xj) (Aj/aj)XjP(x/·lxj) = .

Xj! r(ajjxj+G.j) (l + Aj/alljjxj+aj+xj

BIVARIATE DISTRIBUTION: AN INTERACTIVEMODEL

The yield modeling approach for clustered defects and faultsof the previous section can be extended to model the yield forfaults in a process step caused by defects from a precedingprocess step. This occurs, for instance, when minute dirt particles in one of the oxide layers cause not only oxide pinholes,but also broken metallization patterns on top of it. Let theoxide pinhole faults be indicated by Xj, and the probability ofa fault occurring on a chip during the oxide growth process begiven by

!i(Xj, t) = Cj + bjxj (Cj, b j > 0). (32)

The oxide pinholes will then satisfy the yield equations andconditions given in the previous section. Furthermore, according to (A14) in Appendix II, the distribution for the numberof faults per chip is given by

( )_ r(aj + Xj) (Aj/ad~j

p Xj - x'+a' (33)Xj! r(aj) (l + Aj/aj) I I

where aj and Aj are defined by (29) and (30).For the second fault type, the missing metal patterns, the

probability of a fault occurring during the subsequent processsteps will depend on the number of faults Xj caused by the previous step, as well as the number of faults Xj caused by theprocess step under consideration. If a simple linear relationship is assumed, the probability for a fault occurring can bewritten as

(31)

ues from 0.05 to infInity have been used in practice to modelactual integrated circuit yields for different defects. It is thesimplicity by which clustering is modeled in this approach thathas made it useful. It also has reduced the need for earlier andmore complex cluster theories as well as simulation techniques[23], [47]-[49].

Thus far, the cluster model in this paper has been describedonly for faults that are caused by particles. There are otherrandom integrated circuit failures that are not caused by particles. For instance, the bipolar transistors used in integratedcircuits are usually plagued by so-called "pipes." Pipes are enhanced emitter diffusions along dislocation lines or stackingfaults in the silicon crystal lattice of the wafer. These defectsoften result in short circuits between the transistor emittersand collectors. The dislocation lines or stacking faults arecaused by wafer stresses that result from temperature gradientswhen the wafers are heated or cooled in very-high-temperatureprocessing steps. These stresses appear to be very nonuniformly distributed within wafers. The result is that pipes areusually severely clustered, as has been reported in the work ofPaz and Lawson [29]. These two authors also found that therandom pipe failures could be modeled with the generalizednegative binomial model.

Excess reverse current in reverse-biased semiconductordiodes is another failure that is usually caused by defects inthe silicon crystal lattice. This phenomenon is known as junction leakage. These leakage defects have also been found tocluster. Unpublished work by Stapper has shown that generalized negative binomial statistics are applicable in this case aswell.

If every defect mechanism were similarly subjected to clustering, then (25) would be a model for each defect type. Aslong as the faults caused by different process steps are independent, the total random defect yield will be given by

where there are m defect types, each one with its own averagenumber of faults Aj and clustering parameter aj. In the nextsection it will be shown what happens to (31) when the faultscaused by one process step do depend on the number of faultsalready on the chip from a previous process step.

Sredni [50] has shown that yield expression (21) corresponding to Poisson statistics, as well as (25) for generalized negativebinomial statistics, could be obtained with a model buildingtechnique described by Box and Cox [51]. This method leddirectly to either yield model, depending only on the data.Similarly, the method used in this paper leads directly to aPoisson distribution or generalized negative binomial distribution. In our case, the function that describes the way faultscollect during the manufacturing process determines whichtype of statistics is appropriate. This implies that the generalized negative binomial distribution is just as fundamental toyield modeling as the Poisson distribution, something that wasnot clear from the compounding process used earlier in thispaper. Some uncertainty of the mathematical correctness ofthe generalized negative binomial model for yield modeling hasbeen voiced previously in the literature [24], [37], [52] -[54].It should be clear from the approach used in here, as well asfrom Sredni's method, that there is no need for concern.


This is a bivariate generalized negative binomial model. Although the result in (42) may be somewhat cumbersome

for calculating the probability of having multiple faults on a chip, the yield case for xi = xi = 0 simply becomes

Yij = (1 + X j / a ! f p ( 1 + Xi/ai)-ai. (43 1 This is a fortuitous result since the yield components still act as if they were independent. Thus the general yield expression

i = 1

holds even when the faults caused by different process steps are not independent.

THE BINOMIAL MODEL As early as 1960, binomial statistics were used by Wallmark

to describe integrated circuit yields [551. Since that time, Yanagawa [46], Gupta e t 01. [23] , [48] , [56] , Hu [241, and Stapper [37] have also used these statistics as a starting point for yield theory. The binomial model can also be derived by the method used in the preceding sections for generating the Poisson and generalized negative binomial yield models. To do this, we have to assume that the probability of a fault occurring in a chip is independent of time and decreases linearly with the number of faults already in it. This is a condition which until now has not been observed for faults in semiconductor processes. We can, therefore, conclude that the model, which follows from this assumption, is not a good model for today’s integrated circuit manufacturing lines.

Nevertheless, the assumption, previously stated, can be expressed mathematically as

f(xi, t ) = ci - bixi, for ci > bixi > 0

= 0, otherwise. (44)

If the final result is t o be a binomial distribution, the ratio Ni = cJbi must furthermore be a positive integer. The condition in (44) differs from the assumption made for generalized negative binomial statistics in (26) only by the sign of the second term. The solution of the resulting differential equation can, therefore, be transcribed from (28a) in the form

~ ( s ; t ) = [exp ( -b i t ) - {exp ( -bi t ) - 1) $1 ci’bf (45)

or

G(s; t ) = [ 1 + (s - 1) Xi/NilNi (46)

where

(47)

Equation (46) is the probability generating function for the binomial distribution. The yield in this case is given by

Y = (1 - Xi/Ni)N’. (48)

The number Ni in this result implies that defects of type i can

never produce more than Ni faults per chip. In fact, the probability of having exactly Ni faults on the chip is given by

There is, of course, no reason at all why a manufacturing line should, within a given period of time, not be able to produce a chip with more than Ni defects causing failures. No matter how large Ni is taken to be, there is always a finite probability, smaller than the one in (49), that a chip will have Ni + 1 faults. This is what limits the scope of binomial statistics.

It has also been shown by Rogers that the probability of fault formation in (44) will result in having regularly spaced faults on a wafer, much like an arrangement in a lattice [301. This is not the way faults are distributed on wafers in today’s manufacturing lines. These, as we discussed earlier, tend to cluster.

It can be shown that, with some manipulations, the binomial expansion of (48) will take the form [ 561

When Ni approaches infinity, the series on the right-hand side of this equation will become the MacLaurin series of the yield model in (21) for Poisson statistics.

The fact that Poisson statistics can be derived in this way from binomial statistics has led to the belief that binomial statistics is more basic to yield theory than Poisson statistics [231, [ 241, [48]. This has led to discussions about the “errors” that exist when using Poisson and generalized negative binomial statistics for yield modeling. We hope that with the approach taken in this paper, we have liberated yield statistics from this restrictive point of view. Poisson statistics, generalized negative binomial statistics, and binomial statistics are all equally fundamental t o yield modeling. It so happens that the willy-nilly way defects occur in present semiconductor manufacturing lines favors a generalized negative binomial model. It must be realized, however, that even this is an approximation to the real world of integrated circuit manufacturing. It may well be that someday either one of the other two models becomes a better approximation. We have, therefore, been careful in this paper to leave the door open for any models. Even models not derived by the methods described in this paper have occasionally proven useful. The world of integrated circuit manufacturing is complex enough that it should not be constrained by yield theories. Any model that is convenient and fits the data should be used.

CHIPS WITH REDUNDANT CIRCUITS: A BINOMIAL MODEL

It needs to be pointed out here that there are true binomial considerations that must be taken into account in yield theory. This occurs for chips that are built with redundant circuits, or chips that can be used even when some of the circuitry does not work. The latter have been called partially good chips. They are low in cost, and some users have found ways to use suchchipsintheirdesigns [431, [571, [581,

The use of redundant integrated circuits was proposed by Tammaru et al. in 1967 [ 601, Chen in 1969 [ 61 1, and Schus- ter in 1978 [62]. In 1977, Elmer et a2. described a charge-



holds even when the faults caused by different process stepsare not independent.

-bjtAj=Nj(l-e ). (47)

Equation (46) is the probability generating function for thebinomial distribution. The yield in this case is given by

Y = (l - AtfNj)Nj. (48)

The number N j in this result implies that defects of type i can

If the final result is to be a binomial distribution, the ratioNj = ctfbj must furthermore be a positive integer. The condition in (44) differs from the assumption made for generalizednegative binomial statistics in (26) only by the sign of the second term. The solution of the resulting differential equationcan, therefore, be transcribed from (28a) in the form

G(s; t) = [exp (-bjt) - {exp (-bjt) - l}.r]Cjlbt (45)

r(e:tt +Xj) r(Ct;'jXi +Ct;' +Xj)P(X i, Xj) = -----"''--'-'----'------''-

xi! Xj! r(aj) r(Ct;'jXj + Ct;')

(A ./afj(Aj/~tjI I., (42)

(l + At/ad;'i + Xj(l + Aj/et; )ajjXi +aj + Xj .

This is a bivariate generalized negative binomial model.Although the result in (42) may be somewhat cumbersome

for calculating the probability of having multiple faults on achip, the yield case for xi = Xj = 0 simply becomes

-aj -ajYjj = (l + Aj/aj) (l + Aj/aj). (43)

This is a fortuitous result since the yield components still actas if they were independent. Thus the general yield expression

(49)

(50)

never produce more than N j faults per chip. In fact, the probability of having exactly N j faults on the chip is given by

(N.)Nj

P(Xj = N j ) = A; .There is; of course, no reason at all why a manufacturing lineshould, within a given period of time, not be able to produce achip with more than Ni defects causing failures. No matterhow large N j is taken to be, there is always a finite probability,smaller than the one in (49), that a chip will have Nj + 1 faults.This is what limits the scope of binomial statistics.

It has also been shown by Rogers that the probability offault formation in (44) will result in having regularly spacedfaults on a wafer, much like an. arrangement in a lattice [30] .This is not the way faults are distributed on wafers in today'smanufacturing lines. These, as we discussed earlier, tend tocluster.

It can be shown that, with some manipulations, the binomialexpansion of (48) will take the form [56]

(A.)Ni Nj Ak

k-1 ( 1)1--1. =l+E-n 1--.

N j k=1 k! 1=0 N j

When Ni approaches infmity, the series on the right-hand sideof this equation will become the MacLaurin series of the yieldmodel in (21) for Poisson statistics.

The fact that Poisson statistics can be derived in this wayfrom binomial statistics has led to the belief that binomial statistics is more basic to yield theory than Poisson statistics [23] ,[24], [48]. This has led to discussions about the "errors"that exist when using Poisson and generalized negative binomial statistics for yield modeling. We hope that with the approach taken in this paper, we have liberated yield statisticsfrom this restrictive point of view. Poisson statistics, generalized negative binomial statistics, and binomial statistics are allequally fundamental to yield modeling. It so happens that thewilly-nilly way defects occur in present semiconductor manufacturing lines favors a generalized negative binomial model. Itmust be realized, however, that even this is an approximationto the real world of integrated circuit manufacturing. It maywell be that someday either one of the other two models becomes a better approximation. We have, therefore, been careful in this paper to leave the door open for any models. Evenmodels not derived by the methods described in this paperhave occasionally proven useful. The world of integrated circuit manufacturing is complex ~nough that it should not beconstrained by yield theories. Any model that is convenientand fits the data should be used.

CHIPS WITH REDUNDANT CIRCUITS:A BINOMIAL MODEL

It needs to be pointed out here that there are true binomialconsiderations that must be taken into account in yield theory.This occurs for chips that are built with redundant circuits, orchips that can be used even when some of the circuitry doesnot work. The latter have been called partially good chips.They are low in cost, and some users have found ways to usesuch chips in their designs [43], [57], [58].

The .use of redundant integrated circuits was proposed byTammaro et al. in 1967 [601, Chen in 1969 [611, and Schuster in 1978 [62]. In 1977, Elmer et aL described a charge-

(31)

(44)

(46)

otherwise.

m -ajY= n (l +Aj/aj)

j= 1

= 0,

G(s; t) = [1 + (s - 1) Ai/Nj]Ni

THE BINOMIAL MODEL

As early as 1960, binomial statistics were used by Wallmarkto describe integrated circuit yields [55]. Since that time,Yanagawa [46], Gupta et al. [23], [48], [56], Hu [24], andStapper [37] have also used these statistics as a starting pointfor yield theory. The binomial model can also be derived bythe method used in the preceding sections for generating thePoisson and generalized negative binomial yield models. To dothis, we have to assume that the probability of a fault occurring in a chip is independent of time and decreases linearlywith the number of faults already in it. This is a conditionwhich until now has not been observed for faults in semiconductor processes. We can, therefore, conclude that the model,which follows from this assumption, is not a good model fortoday's integrated circuit manufacturing lines.

Nevertheless, the assumption, previously stated, can be expressed mathematically as

[(Xj, t) = Cj - bjxj, for Cj~ bjxj > 0

where

or

STAF’PER et al.: IC YIELD STATISTICS 463

coupled device memory chip with redundancy [ 631. A full wafer memory with redundant circuits was described in 1979 by Egawa et al. [64]. The real move towards the use of redundant circuits became apparent during the end of 1978, when IBM and Western Electric announced, almost simultaneously, that they had started the manufacturing of 64-kbit dynamic random-access memory chips with redundancy. Those chips and their redundancy have subsequently been described in the literature [43], [57], [65]-[69]. At the 1981 IEEE International Solid-state Circuits Conference it became clear that the rest of the industry was going in the same direction, when memory chips with redundancy were described by engineers from Hitachi [ 701, Intel [ 711, [ 721, Inmos [ 731, and Mostek [ 74 I .

On all these memory chips extra circuits are manufactured to replace faulty ones. The replacement is done when the chips are tested. Laser beams or fuse blowing are used to remove the connection to faulty circuits and steer the signals to the redundant ones. To illustrate calculation of the yield with redundancy, con-

sider a chip that usually has M circuits, each one with a yield Y1. The yield without redundancy is then given by

Y = Y‘y.

If R redundant circuits are added, all the chips with M or more functional circuits are usable. The yield in that case is given by

Y = R ( M + R ) !

Y p + R - n ) ( l - Y1)” (52) (M+ R - n) !n! n =o

which is the sum of R + 1 binomial probabilities. By substituting numbers in (52) it is not difficult to show that the yield given by that formula is higher than the yield in ( 5 1). This result, however, was not obtained without cost. The redundant circuits require extra chip area. Therefore, there are fewer chips per wafer. In general, redundancy will pay well for manufacturers with low yield processes.

The yield Y1 in (52) can be calculated by any yield theory. Extension of (52) to include the generalized negative binomial yield model has been described in the Soviet Union by Borisov [75] and in the U.S. by Mangir and Avizienis [761. In Ger- man and U.S. plants of IBM, a somewhat different approach was taken by Dreckmann, McLaren, and Stapper [431, [ 591, who expanded the quantity (1 - Y1)” in (52) by means of the binomial theorem. They then applied the mixing process with compound Poisson statistics of (24) to each of the terms of the expansion. The results appear to be in good agreement with experimental data [43 ] .

At the time of this writing there is a divergence of opinions on the appropriateness of using redundant circuits in the manufacture of integrated circuit chips. Japanese manufacturers, in general, claim that chips with redundancy are of inferior quality and should not be used. In fact, the use of redundancy is looked upon as a “crutch” [77 ] . The rest of the world, however, appears to be using chip redundancy.

From the theoretical point of view, we agree with the Japa- nese manufacturers on the point of quality of chips fixed with redundancy. This is a consequence of our derivation of generalized negative binomial statistics. In that case, we had to assume that the probability of incurring a fault on a chip was

proportional to the number of faults already on the chip. We can extend this concept one step further. It requires that the probability of a reliability failure occurring on a chip must depend on the number of faults already on the chip. Chips fixed with redundant circuit fall in this category. Since the chip manufacturing processes favor generalized negative binomial statistics, there is a good chance that the reliability of those chips will behave similarly. The fixed chips would then be expected to have a higher failure rate in later life than the chips which were not fixed. Data will be collected in the next few years to verify or nullify this prediction.

However, even if chips fixed with redundancy have a higher failure rate during their lifetime, they should not necessarily be precluded from use. Such use depends entirely on the quality levels of these chips. Chips manufactured in high yielding manufacturing lines and fixed with redundancy can easily be of better quality and reliability than chips without redundancy that are manufactured in a low-yield manufacturing process. Such high-yield fixed chips are, therefore, not necessarily of inferior quality. Furthermore, there are techniques, like “bum in,” which can be used to weed out the failure-prone chips before they are shipped to customers. The decision to use redundancy is therefore a complex one, but yield models, like the one we have described here, do help in making that decision.

APPROXIMATION FOR THE COMBINED RANDOM FAULT YIELD

The random fault yield theory that appears to be the most satisfactory one is given in (3 1). Note that if ai for any defect type becomes very large, the limiting yield will then become approximately equal to that of the Poisson yield model. Any faults that behave according to Poisson statistics are therefore included in this model by simply taking the limit ai -* 00.

The yield expression in (3 1) has been used by Murrmann and Kranzer [ 781, and in a slightly modified form by Okabe et al. [261 and Stapper [ 331, [ 591. The product for the resulting combined yield, however, has one drawback. It consists of a large number of components and parameters and furthermore, the distribution of the number of faults per chip cannot be expressed in a useable form. This makes it difficult to calculate the probabilities for partially good product and the yield of chips with redundancy [42] , [ 591. For this reason, as well as for the sake of simplicity, Okabe et aZ. [26] , Stapper et al. [42] , and Murrmann and Kranzer [ 781 all simplified the total random defect yield by forms similar to

Y = n m (1 + xj/aj)-*i i = 1

The parameter X represents the sum of the average number of faults per chip for each defect type

x = x j .

m ~

i = l

The parameter (Y in (53) is not so readily defined. Murrmann and Kranzer, as well as Okabe et aZ., reported methods for calculating a from the values of X i and ai [26] , [ 781. These methods, as well as others similar to them, have been evaluated by Stapper using simulation methods as well as actual data.



If R redundant circuits are added, all the chips with M or morefunctional circuits are usable. The yield in that case is givenby

coupled device memory chip with redundancy [631. A fullwafer memory with redundant circuits was described in 1979by Egawa et al. [641. The real move towards the use of redundant circuits became apparent during the end of 1978,when IBM and Western Electric announced, almost simultaneously, that they had started the manufacturing of 64-kbitdynamic random-access memory chips with redundancy.Those chips and their redundancy have subsequently been described in the literature [43], [57], [651-[69]. At the 1981IEEE International Solid-State Circuits Conference it becameclear that the rest of the industry was going in the same direction, when memory chips with redundancy were described byengineers from Hitachi [70], Intel [711, [72], Inmos [73],and Mostek [74] .

On all these memory chips extra circuits are manufacturedto replace faulty ones. The replacement is done when thechips are tested. Laser beams or fuse blowing are used to remove the connection to faulty circuits and steer the signals tothe redundant ones.

To illustrate calculation of the yield with redundancy, consider a chip that usually has M circuits, each one with a yieldy 1. The yield without redundancy is then given by

y = t (M + R)! yr'+R -11)(1 - y 1)" (52)11=0 (M+R-n)!n!

which is the sum of R + 1 binomial probabilities. By substituting numbers in (52) it is not difficult to show that the yieldgiven by that formula is higher than the yield in (51). This result, however, was not obtained without cost. The redundantcircuits require extra chip area. Therefore, there are fewerchips per wafer. In general, redundancy will pay well formanufacturers with low yield processes.

The yield Yl in (52) can be calculated by any yield theory.Extension of (52) to include the generalized negative binomialyield model has been described in the Soviet Union by Borisov[75] and in the U.S. by Mangir and Avizienis [76]. In German and U.S. plants of IBM, a somewhat different approachwas taken by Dreckmann, McLaren, and Stapper [43], [59],who expanded the quantity (1 - Y 1)" in (52) by means of thebinomial theorem. They then applied the mixing process withcompound Poisson statistics of (24) to each of the terms ofthe expansion. The results appear to be in good agreementwith experimental data [43] .

At the time of this writing there is a divergence of opinionson the appropriateness of using redundant circuits in the manufacture of integrated circuit chips. Japanese manufacturers,in general, claim that chips with redundancy are of inferiorquality and should not be used. In fact, the use of redundancyis looked upon as a "crutch" [77]. The rest of the world,however, appears to be using chip redundancy.

From the theoretical point of view, we agree with the Japanese manufacturers on the point of quality of chips fixed withredundancy. This is a consequence of our derivation of generalized negative binomial statistics. In that case, we had toassume that the probability of incurring a fault on a chip was

(54)

(31)

(53)

mA= L Aj.

j=l

The parameter A represents the sum of the average number offaults per chip for each defect type

The parameter Q in (53) is not so readily defined. Murrmannand Kranzer, as well as Okabe et al., reported methods for calculating Q from the values of Aj and Qj [26], [78]. Thesemethods, as well as others similar to them, have been evaluatedby Stapper using simulation methods as well as actual data.

proportional to the number of faults already on the chip. Wecan extend this concept one step further. It requires that theprobability of a reliability failure occurring on a chip must depend on the number of faults already on the chip. Chips fixedwith redundant circuit fall in this category. Since the chipmanufacturing processes favor generalized negative binomialstatistics, there is a good chance that the reliability of thosechips will behave similarly. The fixed chips would then be expected to have a higher failure rate in later life than the chipswhich were not fixed. Data will be collected in the next fewyears to verify or nullify this prediction.

However, even if chips fixed with redundancy have a higherfailure rate during their lifetime, they should not necessarilybe precluded from use. Such use depends entirely on the quality levels of these chips. Chips manufactured in high yieldingmanufacturing lines and fixed with redundancy can easily beof better quality and reliability than chips without redundancythat are manufactured in a low-yield manufacturing process.Such high-yield fixed chips are, therefore, not necessarily ofinferior quality. Furthermore, there are techniques, like "burnin," which can be used to weed out the failure-prone chips before they are shipped to customers. The decision to use redundancy is therefore a complex one, but yield models, like theone we have described here, do help in making that decision.

ApPROXIMATION FOR THE COMBINED RANDOM

FAULT YIELD

The random fault yield theory that appears to be the mostsatisfactory one is given in (31). Note that if Qj for any defecttype becomes very large, the limiting yield will then becomeapproximately equal to that of the Poisson yield model. Anyfaults that behave according to Poisson statistics are thereforeincluded in this model by simply taking the limit Qj ~ 00.

The yield expression in (31) has been used by Murrmann andKranzer [781, and in a slightly modified form by Okabe et al.[26] and Stapper [33], [59]. The product for the resultingcombined yield, however, has one drawback. It consists of alarge number of components and parameters and furthermore,the distribution of the number of faults per chip cannot be expressed in a useable form. This makes it difficult to calculatethe probabilities for partially good product and the yield ofchips with redundancy [42], [59]. For this reason, as well asfor the sake of simplicity, Okabe et al. [26], Stapper et al.[42], and Murrmann and Kranzer [78] all simplified the totalrandom defect yield by forms similar to

(51)y= Y1'.

464

None of these techniques were found acceptable. In most cases, there appeared to be too large a mismatch between the resulting values for the yield calculated with (3 1) and (53).

If one wants t o use the approximation in (53), the best way to find a value for a is by first evaluating (54) and then iteratively solving (53) for a so that the yields of (31) and (53) are equal. This method has been evaluated with a simulation technique. To do this, the average number of faults per chip was randomly generated for 20 random defect mechanisms. The distribution for the number of faults per chip was generated for each defect type with a Monte Carlo technique. The individual results for each defect type were added to obtain the overall fault distribution for each chip. This distribution was then checked against a calculated generalized negative binomial distribution with parameter values of X from (54) and a from the iterative program. This simulation was done for 1000 simulated chips per run. Simulation runs were made with a large number of different values of X i and ai. It has been found that for a total yield greater than 50 percent, the approximation in (53) is acceptable when subjected to statistical tests. For lower yields, the results were not always acceptable. It appeared that the nonacceptable fault distributions occurred for simulated distribution with very long tails and a standard deviation or sigma greater than 3.5 faults per chip. The acceptable distributions had a sigma smaller than 2.5 faults per chip, while distributions with sigmas between these two values were mostly acceptable. The criterion for “acceptable” was a significance level of 0.2 or greater, and that for “unacceptable” a significance level smaller than 0.1, as measured with the so-called Kolmogorov-Smirnov test.

These results show that approximation (53) is somewhat tenuous. However, until something better is found, this appears t o be one of the best approximate formulas available. We will next look at (53) as well as some other yield approximations that are used throughout the industry.

A LOOK AT SIMPLIFTED YIELD THEORIES

A number of simplified yield models have been described in the literature on semiconductors. All these models recognize the fact that yield as a function of chip area or the number of circuits does not behave exponentially as predicted by Poisson statistics. For instance, take a chip that has 70-percent yield, or Y = 0.7. If we double the amount of circuitry and chip area, the yield of the larger chip should be Y = 0.7*, or 49 percent. The yield of a chip with three times the amount of circuitry or area has to be Y = 0.73 or 34.3 percent. That this is not necessarily the case can be checked with the so-called “window method.”

The window method was originally described by Seeds (381, [ 391 and subsequently by Okabe et aZ. [ 261, Warner [541, [82] , and Hemmert [53] . The objective is t o determine the yield as a function of chip multiples. This is done with wafer maps that show the location of functioning and failing chips at final test. The maps are analyzed with overlays. Each overlay has grids, or “windows,” that contain a multiple number of chips. In this way it is possible to count the number of windows for each chip multiple that do not contain failing chips. The yield is obtained by dividing the number of nonfailing windows by the total number of windows on the wafers. The results of a window-method analysis are shown in Fig. 8. The yield is plotted with a logarithmic scale on the vertical axis.


loo

YIELD IN PERCENl \

\ Q

DATA

STATISTICS

\

POISSON STATISTICS

1 2 3 4 5 8 7 8 9 1 2 3 4 5 8 7 8 9 CHIP MULTIPLES

Fig. 8. Yield as a function of chip multiples. According to Poisson statistics, this should fall along a straight line on this semilogarithmic plot. The data are the result of failure map analysis with the ‘kin- dow method.”

b

I I I I 1 , * Fig. 9. Yield of integrated circuit products as a function of chip area in two different factories. ’ Products in one factory are indicated with 0, those in the other factory with A. The same products are connected by straight lines.

For Poisson statistics, yield as a function of chip multiples should appear as a straight line. This is not the case for the data shown.

Many authors have expressed their yield models for window- method data in terms of chip area, generally designated by A [42] , [ 521-[ 541. Others have used some sort of sensitive area, often designated by the same symbol [24]-[261, [381, [391, [ 501. To combine such areas into a yield formula has required the invention of a defect density, usually designated by D. This, however, is a fictional quantity defined only through the yield data and depending completely on the yield formula and the definition of A .

The objective of the simple yield models has been to calculate the yield as a function of chip area. However, this has to be done with great care. An example of this can be seen in Fig. 9. The yield of 15 products, manufactured during one year of production in an IBM semiconductor manufacturing plant, is shown as a function of chip areas. These products are


464

None of these techniques were found acceptable. In mostcases, there appeared to be too large a mismatch between theresulting values for the yield calculated with (31) and (53).

If one wants to use the approximation in (53), the best wayto find a value for a is by first evaluating (54) and then iteratively solving (53) for a so that the yields of (31) and (53) areequal. This method has been evaluated with a simulation technique. To do this, the average number of faults per chip wasrandomly generated for 20 random defect mechanisms. Thedistribution for the number of faults per chip was generatedfor each defect type with a Monte Carlo technique. The individual results for each defect type were added to obtain theoverall fault distribution for each chip. This distribution wasthen checked against a calculated generalized negative binomial distribution with parameter values of A from (54) and afrom the iterative program. This simulation was done for1000 simulated chips per run. Simulation runs were madewith a large number of different values of Ai and ai. It hasbeen found that for a total yield greater than 50 percent, theapproximation in (53) is acceptable when subjected to statistical tests. For lower yields, the results were not always acceptable. It appeared that the nonacceptable fault distributionsoccurred for simulated distribution with very long tails and astandard deviation or sigma greater than 3.5 faults per chip.The acceptable distributions had a sigma smaller than 2.5faults per chip, while distributions with sigmas between thesetwo values were mostly acceptable. The criterion for "acceptable" was a significance level of 0.2 or greater, and that for"unacceptable" a significance level smaller than 0.1, as measured with the so-called Kolmogorov-Smirnov test.

These results show that approximation (53) is somewhattenuous. However, until something better is found, this appears to be one of the best approximate formulas available.We will next look at (53) as well as some other yield approximations that are used throughout the industry.

A LooK AT SIMPLIFIED YIELD THEoRIES

A number of simplified yield models have been described inthe literature on semiconductors. All these models recognizethe fact that yield as a function of chip area or the number ofcircuits does not behave exponentially as predicted by Poissonstatistics. For instance, take a chip that has 70-percent yield,or Y =0.7. If we double the amount of circuitry and chiparea, the yield of the larger chip should be Y = 0.7 2

, or 49 percent. The yield of a chip with three times the amount of circuitry or area has to be Y = 0.7 3 or 34.3 percent. That this isnot necessarily the case can be checked with the so-called"window method."

The window method was originally described by Seeds [381,[391 and subsequently by Okabe et 01. [261, Warner [541,[821, and Hemmert [531. The objective is to determine theyield as a function of chip multiples. This is done with wafermaps that show the location of functioning and failing chips atfmal test. The maps are analyzed with overlays. Each overlayhas grids, or "windows," that contain a multiple number ofchips. In this way it is possible to count the number of windows for each chip multiple that do not contain failing chips.The yield is obtained by dividing the number of nonfailingwindows by the total number of windows on the wafers. Theresults of a window-method analysis are shown in Fig. 8. Theyield is plotted with a logarithmic scale on the vertical axis.

PROCEEDINGS OF THE IEEE, VOL. 71, NO.4, APRIL 1983

YIElD INPERCENT

E)

DATA

e

23456789

CHIP MULTIPLES

Fig. 8. Yield as a function of chip multiples. According to Poissonstatistics, this should fall along a straight line on this semilogarithmicplot. The data are the result of failure map analysis with the "winliow method. "

I

Fig. 9. Yield of integrated circuit products as a function of chip area intwo different factories.' Products in one factory are indicated with 0,those in the other factory with f:>. The same products are connectedby straight lines.

For Poisson statistics, yield as a function of chip multiplesshould appear as a straight line. This is not the case for thedata shown.

Many authors have expressed their yield models for windowmethod data in terms of chip area, generally designated by A[421, [521-[ 54]. Others have used some sort of sensitivearea, often designated by the same symbol [241-[261, [381,[391, [501. To combine such areas into a yield formula hasrequired the invention of a defect density, usually designatedby D. This, however, is a fictional quantity defined onlythrough the yield data and depending completely on the yieldformula and the defmition of A.

The objective of the simple yield models has been to calculate the yield as a function of chip area. However, this has tobe done with great care. An example of this can be seen inFig. 9. The yield of 15 products, manufactured during oneyear of production in an IBM semiconductor manufacturingplant, is shown as a function of chip areas. These products are


indicated by small circles. It is clear from the spread in the data that no simple relationship exists between yield and chip area for these products. In fact, one of the smallest chips has the lowest yield. This indicates that the sensitivity to defects must play a much larger role than the chip area. The triangles in the same figure show the yield of some of the same products in another manufacturing line. This also shows a great amount of scatter.

It is because of this dilemma that we have used the average number of faults per chip in this paper. This average is related to the areas and defect densities from the literature of simple models by

X = AD. ( 5 5 )

We will continue to use the concept of the average number of fauts as we describe the simple yield models.

The approximate yield model given by (53) in the preceding section has been very popular. Seeds has been credited with having proposed a yield model with a value of a = 1 [ 2 1 ] . The actual model developed by Seeds, however, was somewhat morecomplex [381, [391. Amodelwithavalueofa=3has been used by Dingwall [79] and at TRW [ 541. Okabe et al. [261, Sredni [SO], Stapper et al. [421, [431, Murrmann and Kranzer [ 781, and Hemmert [53] considered a a parameter that was to be determined from the data. The model in (53) was also used by Rung, who considered a a free parameter in a cost optimization scheme [ 521.

The yield formula in (53) can also be used for a simplified empirical approach to yield modeling. Work by Ansley has shown that the yield of the number of devices in a circuit behaved rather smoothly and could be modeled with mixed Pois- son statistics [40]. Seeds [38] , [39] as well as Ipri [ 801 have shown that the yield can also depend simply on the number of logic circuits or inverters. Saito and Arai found that the number of fieldeffect transistor gates was the dominant variable that controlled their random-access memory yield [ 321. Stap- per and Rosner [81] found in three IBM factories that the yield of read-only memories (read-nly memories (ROM’s) have a predetermined set of unalterable binary information built in during their fabrication), depended predominantly on the number of bits per chip. These results all suggest that the average number of faults h in (53) can be readily estimated if the average number of faults per circuit, gate, or bit are known. Good results with such simplified yield models and (53) have been reported [ 8 1 1 .

Besides a generalized negative binomial yield model in (53), Hemmert also tried a mixed Poisson model [53] . This model was the same as one originally used by Warner [82] and subsequently proposed again by Hu [ 241. Warner called this the “composite yield model.” It has the form

Warner used the “window method” and obtained an excellent fit for yield as a function of chip multiples. He even did more than that. Moore’s data also gave the number of faults that had been found on each chip. Warner also obtained an excellent fit to the resulting fault distribution. This was done by summing Poisson distributions which had the same weighting factors ci, and the average number of faults A i as those used in (56). In doing so, Warner became the first person to successfully understand and model the interdependence of the fault distribution and chip yield.

It has been subsequently shown, albeit not with the same accuracy of Warner’s method, that the negative binomial distribution and the yield model in (53) can also be used to model the same data [421. This required the two parameters a and X in contrast t o five parameters used in Warner’s model.

The theory of both Warner and Hu dealt with single wafers. In semiconductor manufacturing plants with full production, thousands of wafers are processed daily. Determining five parameters for each wafer becomes a discouraging task. One solution to this problem would occur if the parameters were in some way related. In that case, the same procedure we discussed in the section on mixed and compound statistics can be followed. This results in a set of yield equations given in Ap- pendix 111. These formulas have until now not found any use in the literature.

An empirical yield model of the form y e-& ( 5 7)

has been used by Moore and others at Intel [ 4 1 ] , [ 541 . Simi- lar models with different fractional powers of X have also been used at IBM. A yield model consisting of a weighted average of (57) with one of Murphy’s yield formulas has been used at NCR [83]. However, all these models lack a statistical base; there is no fault distribution associated with (57), thus making it difficult t o extend this theory to chips with redundancy.

Yield models using Monte Carlo simulation techniques have been described by Yanagawa [47] and Gupta et al. [23 ] , [48]. With properly specified input parameters, such models can be made highly accurate. However, in most cases, practical methods for measuring the input parameters are not available, thus making day-today monitoring and modeling of manufacturing line yields very difficult. Simulation models of this type have until now not found much application.

A UNIVERSAL YIELD FORMULATION Poisson statistics, binomial statistics, and general negative

binomial statistics were found to be equally fundamental to random fault yield modeling in the preceding sections. Fur- thermore, the yield expression for the generalized negative binomial model

y = fl (1 + XJai)-=i m

i = 1

which is similar t o the mixed Poisson model of (23). The sum becomes the same as the Poisson model when lim a + a, and it consists of n terms. Each term has its own value of parameters becomes equal to the binomial model when a = -N. Equation ci and Ai. Probability theory requires that the sum of the pa- (3 1) can, therefore, be used as a general yield formula for ran- rameters ci equals one. This model, therefdre, has 2n - 1 free dom yields. The only part that is lacking are the gross yields parameters. Fitting data with a multiparameter model should that were discussed at the beginning of this paper. give very good results. This is indeed what was shown by War- Gross yield losses can be introduced into the model simply ner [ 821, who analyzed wafer map data from Moore [ 411. as yield multipliers. This can be expressed mathematically as


STAPPER et Ill.: IC YIELD STATISTICS 465

indicated by small circles. It is clear from the spread in thedata that no simple relationship exists between yield and chiparea for these products. In fact, one of the smallest chips hasthe lowest yield. This indicates that the sensitivity to defectsmust playa much larger role than the chip area. The trianglesin the same figure show the yield of some of the same products in another manufacturing line. This also shows a greatamount of scatter.

It is because of this dilemma that we have used the averagenumber of faults per chip in this paper. This average is relatedto the areas and defect densities from the literature of simplemodels by

We will continue to use the concept of the average number offawts as we describe the simple yield models.

The approximate yield model given by (53) in the preceding section has been very popular. Seeds has been creditedwith having proposed a yield model with a value of a = 1 (21).The actual model developed by Seeds, however, was somewhatmore complex [38], [39]. A model with a value of a =3 hasbeen used by Dingwall (19) and at TRW [54). Okabe et al.[26], Sredni [50], Stapper et al. [42], [431, Murrmann andKranzer (78), and Hemmert [53) considered a a parameterthat was to be determined from the data. The model in (53)was also used by Rung, who considered a a free parameter in acost optimization scheme [52).

The yield formula in (53) can also be used for a simplifiedempirical approach to yield modeling. Work by Ansley hasshown that the yield of the number of devices in a circuit behaved rather smoothly and could be modeled with mixed Poisson statistics (40). Seeds [38], (39) as well as Ipri (80) haveshown that the yield can also depend simply on the number oflogic circuits or inverters. Saito and Arai found that the number of field-effect transistor gates was the dominant variablethat controlled their random-access memory yield (32). Stapper and Rosner (81) found in three IBM factories that theyield of read-only memories (read-only memories (ROM's)have a predetermined set of unalterable binary informationbuilt in during their fabrication), depended predominantly onthe number of bits per chip. These results all suggest that theaverage number of faults Ain (53) can be readily estimated ifthe average number of faults per circuit, gate, or bit areknown. Good results with such simplified yield models and(53) have been reported (81).

Besides a generalized negative binomial yield model in (53),Hemmert also tried a mixed Poisson model [53). This modelwas the same as one originally used by Warner (82) and subsequently proposed again by Hu (24). Warner called this the"composite yield model." It has the form

A=AD. (55)

Warner used the "window method" and obtained an excellentfit for yield as a function of chip multiples. He even did morethan that. Moore's data also gave the number of faults thathad been found on each chip. Warner also obtained an excellent fit to the resulting fault distribution. This was done bysumming Poisson distributions which had the same weighting factors cit and the average number of faults Aj as thoseused in (56). In doing so, Warner became the first person tosuccessfully understand and model the interdependence of thefault distribution and chip yield.

It has been subsequently shown, albeit not with the sameaccuracy of Warner's method, that the negative binomial distribution and the yield model in (53) can also be used tomodel the same data (42). This required the two parametersa and Ain contrast to five parameters used in Warner's model.

The theory of both Warner and Hu dealt with single wafers.In semiconductor manufacturing plants with full production,thousands of wafers are processed daily. Determining five parameters for each wafer becomes a discouraging task. Onesolution to this problem would occur if the parameters were insome way related. In that case, the same procedure we discussed in the section on mixed and compound statistics can befollowed. This results in a set of yield equations given in Appendix III. These formulas have until now not found any usein the literature.

An empirical yield model of the form

Y = e-.Ji (57)

has been used by Moore and others at Intel (41) , [54). Similar models with different fractional powers of Ahave also beenused at IBM. A yield model consisting of a weighted averageof (57) with one of Murphy's yield formulas has been used atNCR [83]. However, all these models lack a statistical base;there is no fault distribution associated with (57), thus makingit difficult to extend this theory to chips with redundancy.

Yield models using Monte Carlo simulation techniques havebeen described by Yanagawa [47] and Gupta et al. [23],[48]. With properly specified input parameters, such modelscan be made highly accurate. However, in most cases, practical methods for measuring the input parameters are not available, thus making day-to-day monitoring and modeling ofmanufacturing line yields very difficult. Simulation models ofthis type have until now not found much application.

A UNIVERSAL YIELD FORMULATION

Poisson statistics, binomial statistics, and general negativebinomial statistics were found to be equally fundamental torandom fault yield modeling in the preceding sections. Furthermore, the yield expression for the generalized negative binomial model

n _~.

y= L: cje J

j=l

(56) (31)

which is similar to the mixed Poisson model of (23). The sumconsists of n terms. Each term has its own value of parametersCj and Aj. Probability theory requires that the sum of the parameters Cj equals one. This model, therefore, has 2n - I freeparameters. Fitting data with a multiparameter model shouldgive very good results. This is indeed what was shown by Warner [82], who analyzed wafer map data from Moore (41).

becomes the same as the Poisson model when lim a -+ 00, and itbecomes equal to the binomial model when a = - N. Equation(31) can, therefore, be used as a general yield formula for random yields. The only part that is lacking are the gross yieldsthat were discussed at the beginning of this paper.

Gross yield losses can be introduced into the model simplyas yield multipliers. This can be expressed mathematically as


Y = fi Yoj fi (1 + xi/Qi)-ai ( 5 8 ) j = 1 i=l

where Yo, represents the yield for the gross problems of type i. In (581, it is assumed that there are n gross yield detractors. In some cases, gross yield losses can also be associated with

random defects. For instance, “pipes” in bipolar transistors can lead to zero-yield areas on wafers. Separating these gross yields from the random yield can be difficult. A very elegant solution to this problem has been described by Paz and Law- son [ 291. They used a number of methods to obtain wafer maps showing the locations of failing transistor chains. Each wafer was divided into two zones and the yield for each zone was analyzed with the window technique. For each wafer the zonal data were then fitted by the method of least squares to the model

Y = Yoe-AD (59)

where the emitter area in each window is given by A , while D represents the pipe defect density per unit area. The quantity Yo is the gross yield.

Paz and Lawson applied this technique to 137 wafers, thus determining the defect density and the gross yield for each zone on each wafer. The defect densities appeared to vary as a gamma distribution, as has been observed for other random defects elsewhere [ 271, [ 141. The use of the gamma distribution as a compounder was, therefore, verified for this defect mechanism, and generalized negative binomial statistics was subsequently a viable model for these failures.

We only need a single gross yield factor Yoi t o model the gross yields of pipes. It is noteworthy, however, that Paz and Lawson could determine the wafer-to-wafer distribution of this gross yield for each zone. The fact that it fits a beta distribution is information imperative for modeling the yield-perwafer distribution. However, such a model has not yet appeared in the literature.

As a result of the pipe data, it appears that a general yield model should include provisions for gross yields associated with some random defects. This will give the yield formula

Y = fi Yo] n Yoi( 1 i- hi/Qi)-ai. m

j = 1 i=l (60)

This may be complex, but we have shown that any of the parameters in this model can be determined with test sites. The theoretical approach to this model furthermore appears sound.

APPLICATIONS

The importance of any theory depends on its applications. There are three areas where the yield model that we have described here has been used. The first application is that of a control model. Measurements with test sites, visual inspection, failure analysis, and test data analysis are being used to evaluate the yield components of the model. These data are stored in a computer data base. Computer graphics are used to plot the yield for each defect type as a function of time, and weekly review of all defect types and yield losses assures that overall yield objectives are met. Problem areas are quickly spotted and engineers and technicians are sent out to diagnose and fix the problems in the manufacturing line.

A second way the model is used has to do with yield scaling

Fig. 10. Actual and planned yields of 36-kbit dynamic random-access memory chip. The dip in yield occurred when the process was transferred from engineering control to manufacturing. Training of manufacturing operators made it possible to eventually exceed targets.

from product to product. If one integrated circuit chip type is manufactured in a processing line, the question inevitably arises what the yield would be for other products, also manufactured in the same line. Stringent rules for scaling critical areas for each defect type from product t o product have resulted in very good success in the manufacture of dynamic random-access memory chips [ 33 I , [ 43 I .

The knowledge of defect levels in a manufacturing line and the capability to scale between products has led to a third application of this model-the planning for future production. Learning plans for all defect types can be made based on historical learning, the expected improvements in tools and clean room facilities, or improved procedures. Targets can then be set, and the ascent of each defect type on its learning curve can be measured. The results of this approach can be spectacular. The yield learning for a 36-kbit dynamic random-access memory chip is shown in Fig. 10. Yield targets were put in place for all known yield components of this chip by the engineers responsible for the processes. These targets were then introduced in the yield model (including redundancy [43] ) t o project the yield plan shown by the smooth curve in Fig. 10. The zigzagging curve is the actual yield of a five-lot (approximately 20 wafers per lot) sliding average. Noteworthy is the loss of learning in the middle of the curve. This occurred when the line was turned over from engineering development to manufacturing control. The new manufacturing personnel had not been given sufficient training to handle one of the metallization steps properly. The result was zero yield caused by defective metal. After more training and a design improvement of the chip, the manufacturing personnel made the yield climb back to the learning curve. They eventually succeeded in exceeding the targets.

The yield learning of a 64-kbit dynamic random-access memory chip has been described elsewhere [ 121 , [ 591. An updated version of actual yield learning versus the plan for this chip is shown in Fig. 11. These yields were again planned for each yield component and a yield model with redundancy was used to project the yield. In this case, targets were eventually exceeded also.


where YOj represents the yield for the gross problems of typej. In (58), it is assumed that there are n gross yield detractors.

In some cases, gross yield losses can also be associated withrandom defects. For instance, "pipes" in bipolar transistorscan lead to zero-yield areas on wafers. Separating these grossyields from the random yield can be difficult. A very elegantsolution to this problem has been described by Paz and Lawson [29]. They used a number of methods to obtain wafermaps showing the locations of failing transistor chains. Eachwafer was divided into two zones and the yield for each zonewas analyzed with the window technique. For each wafer thezonal data were then fitted by the method of least squares tothe model

466

,. m _~I

Y = n YO/ n (l + 'At/ai)/=1 1=1

(58)

(59)


where the emitter area in each window is given by A, while Drepresents the pipe defect density per unit area. The quantityYo is the gross yield.

Paz and Lawson applied this technique to 137 wafers, thusdetermining the defect density and the gross yield for eachzone on each wafer. The defect densities appeared to vary as agamma distribution, as has been observed for other random defects elsewhere [27 J, [14). The use of the gamma distribution as a compounder was, therefore, verified for this defectmechanism, and generalized negative binomial statistics wassubsequently a viable model for these failures.

We only need a single gross yield factor Y01 to model thegross yields of pipes. It is noteworthy, however, that Paz andLawson could determine the wafer-to-wafer distribution ofthis gross yield for each zone. The fact that it fits a beta distribution is information imperative for modeling the yield-perwafer distribution. However, such a model has not yet appeared in the literature.

As a result of the pipe data, it appears that a general yieldmodel should include provisions for gross yields associatedwith some random defects. This will give the yield formula

,. m _~

Y= n YOj n YOi(l+'At/ai)· (60)/=1 1= 1

This may be complex, but we have shown that any of the parameters in this model can be determined with test sites. Thetheoretical approach to this model furthermore appears sound.

APPLICATIONS

The importance of any theory depends on its applications.There are three areas where the yield model that we have described here has been used. The first application is that of acontrol model. Measurements with test sites, visual inspection,failure analysis, and test data analysis are being used to evaluate the yield components of the model. These data are storedin a computer data base. Computer graphics are used to plotthe yield for each defect type as a function of time, andweekly review of all defect types and yield losses assures thatoverall yield objectives are met. Problem areas are quicklyspotted and engineers and technicians are sent out to diagnoseand fix the problems in the manufacturing line.

A second way the model is used has to do with yield scaling

Fig. 10. Actual and planned yields of 36-kbit dynamic random-accessmemory chip. The dip in yield occurred when the process was transferred from engineering control to manufacturing. Training of manufacturing operators made it possible to eventually exceed targets.

from product to product. If one integrated circuit chip type ismanufactured in a processing line, the question inevitablyarises what the yield would be for other products, also manufactured in the same line. Stringent rules for scaling criticalareas for each defect type from product to product have resulted in very good success in the manufacture of dynamicrandom-access memory chips [33], [43] .

The knowledge of defect levels in a manufacturing line andthe capability to scale between products has led to a third application of this model-the planning for future production.Learning plans for all defect types can be made based on historical learning, the expected improvements in tools and cleanroom facilities, or improved procedures. Targets can then beset, and the ascent of each defect type on its learning curvecan be measured. The results of this approach can be spectacular. The yield learning for a 36-kbit dynamic random-accessmemory chip is shown in Fig. 10. Yield targets were put inplace for all known yield components of this chip by the engineers responsible for the processes. These targets were then introduced in the yield model (including redundancy [43]) toproject the yield plan shown by the smooth curve in Fig. 10.The zigzagging curve is the actual yield of a five-lot (approximately 20 wafers per lot) sliding average. Noteworthy is theloss of learning in the middle of the curve. This occurredwhen the line was turned over from engineering developmentto manufacturing control. The new manufacturing personnelhad not been given sufficient training to handle one of themetallization steps properly. The result was zero yield causedby defective metal. After more training and a design improvement of the chip, the manufacturing personnel made the yieldclimb back to the learning curve. They eventually succeededin exceeding the targets.

The yield learning of a 64-kbit dynamic random-access memory chip has been described elsewhere [12], [59]. An updated version of actual yield learning versus the plan for thischip is shown in Fig. II. These yields were again planned foreach yield component and a yield model with redundancy wasused to project the yield. In this case, targets were eventuallyexceeded also.

STAPPER ef al.: IC YIELD STATISTICS 467

t YIELD RELATIVE

I I I

1978 1979 lgeo 1981 lge2 YEARS

Fig. 11. Actual and planned yields of a 64-kbit dynamic random-access memory chip.

The use of this systematic approach to semiconductor integrated circuit yields has been called "yield management" [ 121. It contrasts sharply with the haphazard yields that result from lack of control and neglect of attention to detail. The scientific fashion of using yield models is also a step ahead of the somewhat mystical adherence to cleanliness. The effects of improvements in cleanliness are directly verified and quantified in a system where all the defects are measured and modeled.

CONCLUSIONS In this paper we have described statistical integrated circuit

yield models and have shown how they can be derived with given assumptions of the fault and defect formation processes during manufacturing. The approach appears t o be general enough to include many of the existing yield theories. By comparing these with each other we can now describe the conditions for which each is applicable.

A universal yield model has been formulated for use in manufacturing control and yield management. Examples of the applications to these fields have been given and discussed.

APPENDIX I BASE FOR YIELD STATISTICS

As a starting point for yield theory, assume that at the beginning of the manufacturing process none of the circuits or chips contain faults. Let p(x, t ) be the probability that an individual cell has x defects that will cause faults by time t . Assume also that during the time interval ( t , t + dt ) , the probability that a fault occurs within a particular chip which already has x defects is f(x, r ) d t , and that the time interval is short enough so that no more than one fault is allowed to fall in a given circuit during a single time interval. Then

p ( x , t + d t ) = p ( x - l , t ) f ( x - l , t ) d r + p ( x , t ) - [ 1 - f ( x , t ) d t l , for x = l , 2 , 3 ; . . (A2)

and it can be readily shown that

a - ~(0, t ) = - d o , t ) f ( O , t ) at

a - P(X, t ) = - d x , t ) f ( x , t ) + P(X - 1, t ) f (x - 1, t ) , a t

(A31

for x = 1, 2 ,3 , - - - . (A4)

Multiply both sides of (A3) by so and (A4) by sx and sum each term. This will give

or

where

c(s; t ) = 2 p(x, r )? (A71 x =o

is the probability generating function of the random variable x, and

0

US, t ) = P(X, t ) f(x, t ) sX. (A81 x =o

To find C(s; t ) requires solving the single differential equation in (A6). The solution will depend on the nature of f(x, t ) . Examples of this are given in the text of this paper.

APPENDIX Il YIELD STATISTICS AND THEIR PROPERTIES

The distribution of the number of faults per chip is the key to yield analysis. The random variable X will be used to designate the number of faults per chip. This is an integer number. The probability for x faults or failures occurring on a chip will be designated by P(X = x).

The expected or average number of faults per chip is designated by EQ. It will have a value of X in all the distributions shown here. The average number of faults usually is not an integer.

The variance in the number of faults per chip is designated as V(X). The yield in all cases is given by Y = P(X = 0), or the probability of having no faults on the chip. Also included in the tabulations below is the distribution

generating function designated by G(s). This is also related to the yield by Y = C(s = 0).

Poisson Statistics

e-AXX P(X=x)=-

X!

E ( X ) = x V(X) = X



RELATIVEYIELD

ACTUAL YIELD

467

p(x,t+dt)=p(x-l,t)[(x-l,t)dt+p(x,t)'[l-[(x,t)dt], for x=1,2,3,'" (A2)

and it can be readily shown that

aat p(D, t) = -p(D, t)[(D, t) (A3)

aat p(x, t) = - p(x, t) [(x, t) + p(x - 1, t) [(x - 1, t),

for x=1,2,3, .. ·. (A4)

Multiply both sides of (A3) by SO and (A4) by i' and sumeach term. This will give

a .. ..a L p(x,t)r=(s-l) L p(x,t)[(x,t)? (AS)tx=o x=o

or

is the probability generating function of the random variablex,and

To imd G(s; t) requires solving the single differential equationin (A6). The solution will depend on the nature of [(x, t).Examples of this are given in the text of this paper.

1978 1979 1980 1981 1982 YEARS

Fig. 11. Actual and planned yields of a 64-kbit dynamic random-accessmemory chip.

The use of this systematic approach to semiconductor integrated circuit yields has been called "yield management" [12].It contrasts sharply with the haphazard yields that result fromlack of control and neglect of attention to detail. The scientificfashion of using yield models is also a step ahead of the somewhat mystical adherence to cleanliness. The effects of improvements in cleanliness are directly verified and quantifiedin a system where all the defects are measured and modeled.

where

aat G(s; t) = (s - 1) L(s; t)

..G(s; t) = L p(x, t) r

x=o

..L(s, t) = L p(x, t) [(x, t) sX.

x=o

(A6)

(A7)

(A8)

APPENDIX IBASE FOR YIELD STATISTICS

As a starting point for yield theory, assume that at the beginning of the manufacturing process none of the circuits or chipscontain faults. Let p(x, t) be the probability that an individualcell has x defects that will cause faults by time t. Assume alsothat during the time interval (t, t + dt), the probability that afault occurs within a particular chip which already has x defects is [(x, t) dt, and that the time interval is short enough sothat no more than one fault is allowed to fall in a given circuitduring a single time interval. Then

CONCLUSIONS

In this paper we have described statistical integrated circuityield models and have shown how they can be derived withgiven assumptions of the fault and defect formation processesduring manufacturing. The approach appears to be generalenough to include many of the existing yield theories. Bycomparing these with each other we can now describe the conditions for which each is applicable.

A universal yield model has been formulated for use in manufacturing control and yield management. Examples of theapplications to these fields have been given and discussed.

APPENDIX IIYIELD STATISTICS AND THEIR PROPERTIES

The distribution of the number of faults per chip is the keyto yield analysis. The random variable X will be used to designate the number of faults per chip. This is an integer number.The probability for x faults or failures occurring on a chip willbe designated by P(X = x).

The expected or average number of faults per chip is designated by E(X). It will have a value of A in all the distributionsshown here. The average number of faults usually is not aninteger.

The variance in the number of faults per chip is designated asV(X). The yield in all cases is given by Y = P(X = I), or theprobability of having no faults on the chip.

Also included in the tabulations below is the distributiongenerating function designated by G(s). This is also related tothe yield by Y = G(s = D).

p(D, t + dt) =p(D, t) [1 - [(D, t) dt] (Al)

Poisson Statistics

e-AAxP(X=x)=-

x!

E(X) = A

V(X) = A

(A9)

(AID)

(All)


Generalized Negative Binomial Statistics

Binomial Statistics

P ( X = x ) = (X/NlX(I - A / N I N - x

E(X) = X

V(X) = X(1 - vrv) G(s)= [ 1 + (s - 1) v N I N

Y = ( l - X/NIN.

APPENDIX III MIXED AND COMPOUND POISSON STATISTICS

The discrete mixed Poisson process of (23) and (52) has the form

For an infinite s u m , the values c have the same properties as a discrete probability distribution. The probabilities associated with the Poisson distribution, binomial distribution, and negative binomial distribution have been used for this purpose. When used in this way, they are often referred to as the mixing or compounding distributions. If X i is directly proportional to the index j , the coefficients cj are the probabilities of the mixing distribution. The average number of faults is then given by

The width of the fault distribution depends on the nature of the distribution picked for ci.

Neyman type-A statistics result from mixing two Poisson distributions. The coefficients ci in (A24) and (A25) are then equal to the probabilities of a Poisson distribution. The results of such mixing is a yield equation.

where a is a parameter related to the width of the Poisson distribution used for mixing.

Mixing a binomial distribution with a Poisson distribution results in

Y = exp [a{(l - v a n ) ” - I}] (A27)

where a is again a parameter related to the width of the binomial fault distribution.

Mixing a negative binomial distribution with a Poisson distribution results in

where a and k are parameters in the negative binomial distribution.

In all the preceding results, the yield expression will become the Poisson yield model when the value of a approaches i n f ~ t y .

The continuous mixing process takes on the form

where (A’) is a probability distribution function for the number of faults per chip. It acts here as a compounder or mixing function. The average number of faults per chip is given by

Murphy [25] used a triangular and uniform distribution for the compounder in (A29). These results in the yield equations

y = (!+)1 and

It is also possible to use a truncated normal distribution for the compounder. This results in

where A. is the value of X‘ where the normal distribution peaks. The value of u is the standard deviation of this distribution before truncation.

Using a gamma distribution for the compounder results in

Y = (1 + u2/X)-k2/‘z2 (A34)

where X is the mean and u is the standard deviation of the gamma distribution. Defining a constant

puts (A34) in the form

which is the same as the formula used in the text.

REFERENCES

[ 11 W. E. Ham, “Yield-area analysis: Part I-A diagnostic tool for fundamental integrated circuit process problems,”RCA Rev., vol.

[ 2 ) P. Gangatirkar, R. D. Reson, and L. G. Rosner. “Test/character- 39, pp. 231-249, June 1978.

Int. SoW-State Circuits Con, D&. Tech. Papers, pp. 62-63, Feb. ization procedures for high density silicon RAM’S,” 1982 IEEE

[ 3 ] D. P. Kennedy. P. C. Murley, and R. R. O’Brien, “A statistical 1982.

approach to the design of diffused junction transistors,” IBM J. Res. DmcL, vol. 8, pp. 4 8 2 4 9 5 , 1964.

[4] C. H. Stapper and P. B. Hwang, “Simulation of FET device parameters for LSI manufacturing,” Smicondvctw Silicon 1977, vot 11-2. Princeton, NJ: Electrochem. SOC., May 1977, pp. 955-961.



Mixing a negative binomial distribution with a Poisson distribution results in

where a and k are parameters in the negative binomial distribution.

In all the preceding results, the yield expression will becomethe Poisson yield model when the value of a approachesinfmity.

The continuous mixing process takes on the form

G(s) = eA("-I)

Y= e-X•

Generalized Negative Binomial Statistics

na+x) ('NalP(X =x) = xl na) (l + A/a)x+a

E(X)= A

V(X) =A(1 + A/a)

G(s) = [1 + (l - s) A/ara

Y = (1 + A/a)-a.

(AI2)

(AI3)

(AI4)

(AI5)

(AI6)

(AI7)

(AI8)

Y = exp [a{(l + A/ak)-k - I}]

Y = JOO e-X'g(A') dA'o

(A28)

(A29)

APPENDIX illMIXED AND COMPOUND POISSON STATISTICS

The discrete mixed Poisson process of (23) and (52) has theform

where (A') is a probability distribution function for the number of faults per chip. It acts here as a compounder or mixingfunction. The average number of faults per chip is given by

(A32)

(A30)

(A31)

1 - e-2XY=---

2A

A= [ A'g(A') dA'.o

Murphy [25] used a triangular and uniform distribution forthe compounder in (A29). These results in the yield equations

(1 - e-X)2

Y= --A

and

(A19)

(A20)

(A21)

(A22)

(A23)

Binomial Statistics

P(X = x) = (:) (A/N)x(l - 'NN)N-X

E(X) = A

V(X) = A(l - 'NN)

G(s) = [1 + (s - 1) 'NN]N

Y= (1- 'NN)N.

(A24) It is also possible to use a truncated normal distribution forthe compounder. This results in

For an infinite sum, the values c have the same properties as adiscrete probability distribution. The probabilities associatedwith the Poisson distribution, binomial distribution, and negative binomial distribution have been used for this purpose.When used in this way, they are often referred to as the mixingor compounding distributions. If Ai is directly proportional tothe index j, the coefficients Cj are the probabilities of the mixing distribution. The average number of faults is then given by

00

A= L AjCj.j=1

(A25)

Y_ 1 +erf {(AO - o)/oV2} A + 2- 1 + erf (A%V2) exp (0 0 /2) (A33)

where AO is the value of A' where the normal distributionpeaks. The value of 0 is the standard deviation of this distribution before truncation.

Using a gamma distribution for the compounder results in

Y = (1 + 0 2/A)-X2/u

2(A34)

where A is the mean and 0 is the standard deviation of thegamma distribution. Defming a constant

(A35)

where a is again a parameter related to the width of the binomial fault distribution.

The width of the fault distribution depends on the nature ofthe distribution picked for Cj'

Neyman type-A statistics result from mixing two Poisson distributions. The coefficients Cj in (A24) and (A25) are thenequal to the probabilities of a Poisson distribution. The resultsof such mixing is a yield equation.

Y= exp [-a(I - e-x/a )] (A26)

where a is a parameter related to the width of the Poisson distribution used for mixing.

Mixing a binomial distribution with a Poisson distribution results in

(1) W. E. Ham, "Yield-area analysis: Part I-A diagnostic tool forfundamental integrated circuit process problems," RCA Rev., vol.39, pp. 231-249, Iune 1978.

(2) P. Gangatirkar, R. D. Presson, and L. G. Rosner, "Test/characterization procedures for high density silicon RAM's," 1982 IEEEI"t. Solid-St4te Circuit" Can., Dig. Tech. Ptlper", pp. 62-63, Feb.1982.

(3) D. P. Kennedy. P. C. Murley, and R. R. O'Brien, "A statisticalapproach to the design of diffused junction transistors," IBM J.Re& Devel., vol. 8, pp. 482-495,1964.

(4) C. H. Stapper and P. B. Hwang, "Simulation of FET device parameters for LSI manufacturing," Semiconductor Silica" 1977, vol.77-2. Princeton, NI: Electrochem. Soc., May 1977, pp. 955-967.

Y=exp [a{(l- 'Nan)" - I}] (A27)

puts (A34) in the form

Y =(l + A/a)-a

which is the same as the formula used in the text.

REFERENCES

(A36)

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