the comparison of macroni serial nor flash products ......erase suspend & resume v v program...

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE

The Comparison of Macronix Serial NOR Flash Products MX25U3232F and MX25U3235F

Macronix Proprietary1

1. IntroductionThis application note compares Macronix MX25U3232F and MX25U3235F Serial NOR Flash products. The document does not provide detailed information on individual devices, but highlights the similarities and differences among them. The comparison covers the general features, performance, command sets, and device identification numbers.

The information provided in this document is based on datasheets listed in Section 7. References. Newer versions of the datasheets may override the contents of this document.

2. General Features

2-1. Feature ComparisonMacronix 1.8V 32Mb Serial NOR Flash families have similar features and functions while MX25U3232F devices provide a feature rich solution to cover MX25U3235F.

Both MX25U3232F and MX25U3235F devices support an individual block protection method as an alternative to the grouped block protection provided with Status Register Block Protection(BP) bits.

In addition, the MX25U3232F added additional protection features in the Advanced Sector Protection mode that provide higher levels of protection. These higher levels of protection include:

1. Nonvolatile individual sector/block protection.2. A software locking mechanism to prevent modifications to the nonvolatile protection until the next

reset cycle or power-up cycle.

These additional protection features can be used to prevent accidental or deliberate data corruption in protected memory areas.

The main differences between MX25U3232F and MX25U3235F are listed as below: 1. Performance: MX25U3232F supports clock frequency up to 133MHz for all protocols and lower

deep power down specifications. 2. Secured OTP: MX25U3232F have an additional 8K-bit secured OTP. 3. Advanced Sector Protection Mode: MX25U3232F provides higher levels of protection. 4. Factory Mode: MX25U3232F supports factory mode to enhance Program and Erase performance

for increase factory production throughput.

Please refer to the MX25U3232F and MX25U3235F datasheets for more details. For additional product differences, please refer to Table 2-1. Feature Comparison as below.

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Table 2-1. Feature Comparison

Part no. MX25U3232F MX25U3235FTechnology 75nm 75nmDensity 32Mb 32MbVCC 1.65V - 2V 1.65V - 2V

Structure

Fast Read I/O support

FAST READ(1-1-1) v vDREAD(1-1-2) v v2READ(1-2-2) v vQREAD(1-1-4) v v4READ(1-4-4) v vQPI(4-4-4) v v

Sector Size 4KB 4KBBlock Size 32KB/64KB 32KB/64KBProgram Buffer Size 256Byte 256ByteSFDP JESD216B JESD216UID v vEndurance (typ.) 100K cycles 100K cyclesData Retention (typ.) 20 years 20 yearsHardware Pin# Reset* Reset*

Software FeaturesConfigurable Dummy Cycles v -Adjustable Output Driver Strength v -Erase Suspend & Resume v vProgram Suspend & Resume v vDeep Power Down Mode v vRead Enhance Mode v vWrap-around Read Mode v vFactory mode v -Secured OTP 4Kb x 2 4Kb x 1BP Protect Top/Bottom TopIndividual/Volatile Write Protection v vIndividual/Non-Volatile Write Protection v -

* Reset# will be disabled since Quad mode is enabled.

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


2-2. Write Protection ComparisonThe MX25U3232F and MX25U3235F provide two write protection modes to easily protect sectors from inadvertent changes.

The default mode is Block Protection Mode, utilizing the nonvolatile Block Protection (BP) bits in the Status Register. The BP bits specify which block groups will be protected.

The second mode uses an individual block protection method. This method utilizes a volatile SRAM lock bit assigned to each block (or sector) and controls its protection status. The Gang Block Lock (GBLK) and Gang Block Unlock (GBULK) commands set or clear all SRAM lock bits simultaneously and these commands are identical for both MX25U3232F and MX25U3235F. The MX25U3232F and MX25U3235F use different commands to control individual SRAM lock bits, and the details are addressed below.

2-2-1. Block Protection (BP) ModeBoth MX25U3232F and MX25U3235F use identical Status Register BP bits to specify which group of blocks to be protected.

However, some difference between their block group sizes, MX25U3232F has a finer granularity of protection and has the ability to specify whether block protection begins at the top or bottom of memory. This is controlled by the Top/Bottom (TB) bit in Configuration Register.

The TB default setting is "0" and specifies the top of the memory as shown in Table 2-2: Block Protection (BP) Comparison (Top memory blocks) and Table 2-3: Block Protection (BP) Comparison (Bottom memory blocks).

Table 2-2: Block Protection (BP) Comparison (Top memory blocks)

Status Register Bit Protected BlocksBP3 BP2 BP1 BP0 MX25U3232F MX25U3235F

0 0 0 0 None None0 0 0 1 1 block (#63) 1 block (#63)0 0 1 0 2 blocks (#62-63) 2 blocks (#62-63)0 0 1 1 4 blocks (#60-63) 4 blocks (#60-63)0 1 0 0 8 blocks (#56-63) 8 blocks (#56-63)0 1 0 1 16 blocks (#48-63) 16 blocks (#48-63)0 1 1 0 32 blocks (#32-63) 32 blocks (#32-63)0 1 1 1 64 blocks (all) 64 blocks (all)1 0 0 0 64 blocks (all) 64 blocks (all)1 0 0 1 64 blocks (all) 32 blocks (#0-31)1 0 1 0 64 blocks (all) 48 blocks (#0-47)1 0 1 1 64 blocks (all) 56 blocks (#0-55)1 1 0 0 64 blocks (all) 60 blocks (#0-59)1 1 0 1 64 blocks (all) 62 blocks (#0-61)1 1 1 0 64 blocks (all) 63 blocks (#0-62)1 1 1 1 64 blocks (all) 64 blocks (all)

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Table 2-3: Block Protection (BP) Comparison (Bottom memory blocks)

Status Register Bit Protected BlocksBP3 BP2 BP1 BP0 MX25U3232F MX25U3235F

0 0 0 0 None NA0 0 0 1 1 block (#0) NA0 0 1 0 2 blocks (#0-1) NA0 0 1 1 4 blocks (#0-3) NA0 1 0 0 8 blocks (#0-7) NA0 1 0 1 16 blocks (#0-15) NA0 1 1 0 32 blocks (#0-31) NA0 1 1 1 64 blocks (all) NA1 0 0 0 64 blocks (all) NA1 0 0 1 64 blocks (all) NA1 0 1 0 64 blocks (all) NA1 0 1 1 64 blocks (all) NA1 1 0 0 64 blocks (all) NA1 1 0 1 64 blocks (all) NA1 1 1 0 64 blocks (all) NA1 1 1 1 64 blocks (all) NA

2-2-2. Individual Block Protection ModeIndividual block protection is only effective after executing the WPSEL command. This one-time-use command permanently disables the block group protection method (Status Register BP bits) and activates individual block protection. The WPSEL command is common to both MX25U3232F and MX25U3235F.

MX25U3232F and MX25U3235F devices implement individual block protection differently and require different commands. The following sections will discuss both implementations.

2-2-3. Individual Block Protection versus Advanced Sector ProtectionThe ability to quickly unlock individual blocks is convenient when changes are required, but it also makes the protected areas vulnerable to corrupt or malicious software. To enhance the security of the protection feature, the protection feature, the MX25U3232F have added Advanced Sector Protection. Advanced Sector Protection adds nonvolatile protection bits with the ability to lock them until the next reset cycle or power-up cycle. These new features require different commands and the user’s application software will need to be modified if the features are desired.

The following sections show the operational differences when using individual sector/block protection.

2-2-4. MX25U3235F: Individual Block Protection ModeThe Single Block Lock Protection bits are volatile SRAM bits assigned to each protectable sectoror block. The bits permit sectors or blocks to be protected individually and independent of any other sector or block. The Single Block Lock Protection bits default to protected mode (set as "1") upon power-up or reset. Table 2-4: Individually Protectable Sectors/Blocks illustrates in green, which blocks can be individually protected.

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Table 2-4: Individually Protectable Sectors/Blocks

64KB Block # 32KB Sector # 4KB Sector # Protectable

63

127

1023

16 4KB sectors (lock/unlock)

.

.

.1016

126

1015...

1008

62

125

1007

62 64KB blocks (lock/unlock)

.

.

.1000

124

999...

992

.

.

.

.

.

.

991......

.

.

.

.

.

.

.

.

.32

1

3

31...

24

2

23...

16

0

1

15

16 4KB sectors (lock/unlock)

.

.

.8

0

7...0

Only the sector and block numbers highlighted in gray are individually protectable.

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


The Single Block Lock (SBLK) instruction (36h) enables read only protection for the specified sector or block of memory. Sector selection is made using address bits A23-A12 and only the top and bottom sixteen 4KB sectors can be individually protected. The remaining sectors are grouped into 64KB blocks. Individual 64KB block selection is made using address bits A23-A16. Use the Single Block Unlock (SBULK) instruction (39h) to cancel the individual sector or block protection state.

Figure 2-1: Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 29 30 31

Command 24 Bit Address Cycles

SI 36/39 A23 A22 A2 A1 A0 MSB

2-2-5. MX25U3232F: Advanced Sector Protection Mode

Dynamic Protection Bits (DPB) is volatile and similar in purpose to the Single Block Lock Protection bits used by the MX25U3235F devices. Nonvolatile Solid Protection Bits (SPB) is a new feature. Each protectable sector or block (Table 2-4: Individually Protectable Sectors/Blocks) is assigned one DPB and one SPB. This permits sector or block protection to be specified individually and independent of any other sector or block. The DPB default to the protect state (FFh) upon power-up or reset. They work in conjunction with the nonvolatile SPB. Both DPB and SPB states must be cleared to 00h before the associated sector or block can be modified. The SPB are preset to 00h at the factory and there is no need to modify them if you are migrating from MX25U3235F. Please refer to the MX25U3232F datasheet for more details if you need to use the SPB features.

To modify the DPB status, issue the DPB Program command (WRDPB) including the target sector or block address and set or clear the DPB protection state. All DPB bits can be quickly unlocked by issuing one Gang Block Unlock (GBULK) command (98h). Sector selection is made using address bits A23-A12 and only the top and bottom sixteen 4KB sectors can be individually protected. The remaining sectors are grouped into 64KB blocks. Individual 64KB block selection is made using address bits A23-A16.

Table 2-5: DPB RegisterBit Description Bit Status Default Type

7 to 0DPB (Dynamic Protection Bit)

00h= Unprotect Sector / Block

FFh= Protect Sector / Block FFh Volatile

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Note: A31-A24 are don’t care.

Note: A31-A24 are don’t care.

Figure 2-2: Write DPB Register (WRDPB) Sequence

21 3 4 5 6 7 8 90

MSB

SCLK

CS#

SI E1h

Command

Mode 3 37 38 39 40 41 42

Mode 032-Bit Address

(Note)

A31 A30 A2 A1 A0 7 6 5 4 3 2 1 0

MSB

Data Byte 1

43 44 45 46 47

Figure 2-3: Read DPB Register (RDDPB) Sequence

21 3 4 5 6 7 8 90

MSB

SCLK

CS#

SI

SO

E0h

Command

Mode 3 37 38 39 40 41 42

Mode 032-Bit Address

(Note)

A31 A30 A2 A1 A0

7 6 5 4 3 2 1 0High-Z

MSB

Data Out

43 44 45 46 47

2-2-6. Lock RegisterTo enhance the security of the protection feature, MX25U3232F provide SPB Lock Down feature, once SPBLKDN (bit 6) is set, SPB bit value cannot be changed again and it is read-only.

Please refer to MX25U3232F datasheets for more detailed information.

Table 2-6: Lock Register of MX25U3232F

Bits Field Name Function Type Default State Description15 to 7 RFU Reserved OTP 1 Reserved for Future Use

6 SPBLKDN SPB Lock Down OTP 11 = SPB changeable

0 = freeze SPB5 to 0 RFU Reserved OTP 1 Reserved for Future Use

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


3. Performance ComparisonThe MX25U3232F provide capable of similar or improved performance as below tables.

Table 3-1: Read Performance Comparison

MX25U3232F MX25U3235F

Operation Frequency (MHz)

1-1-1 (READ) 50 50

1-1-1 (FAST_READ) 104*(8)/133(10) 104(8)

1-1-2 (DREAD) 104*(8)/133(10) 104(8)

1-2-2 (2READ) 84*(4)/133(10) 84(4)

1-1-4 (QREAD) 104*(8)/133(10) 104(8)

1-4-4 (4READ) 84*(6)/133(10) 84*(4)/104(6)

4-4-4 (QPI) 84*(6)/133(10) 84*(4)/104(6)

1. () Indicates numbers of dummy cycles2. * Default

Table 3-2: AC Performance Comparison

AC Performance Condition Unit MX25U3232F MX25U3235F

Program Time 256 BytesTyp ms 0.5 0.5

Max ms 3 3

Erase Time

4KBTyp ms 30 35

Max ms 200 200

32KBTyp s 0.2 0.2

Max s 1 1

64KBTyp s 0.35 0.35

Max s 2 2

Chip EraseTyp s 10 50

Max s 25 75

Clock Low to Output Valid

30pf Max ns 8 7

15pf Max ns 6 6

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Table 3-3: DC Performance Comparison

DC Performance Condition Unit MX25U3232F MX25U3235F

Standby Current (ISB1)Typ uA 15 15Max uA 50 50

Deep Power Down Current (ISB2)Typ uA 0.05 1.5Max uA 5 15

Read Current (ICC1) (1I/O)Typ mA - -Max mA 10 @84MHz 15 @84MHz

Program Current (ICC2)Typ mA 15 20Max mA 20 25

Icc Write Status Reg. Current (ICC3)Typ mA 10 10Max mA 20 20

Sector Erase Current (ICC4)Typ mA 15 18Max mA 20 25

Chip Erase Current (ICC5)Typ mA 20 20Max mA 25 25

4. Command Code ComparisonAll of the commands are listed in Table 4-1: Command Code Comparison below. Most commands are common. Differences are attributted to unsupported or new features.

Table 4-1: Command Code Comparison

Command Symbol Description MX25U3232F MX25U3235F

ID Read

RDID Read Identification 9Fh 9FhRES Read Electronic ID ABh ABhREMS Read Electronic Manufacturer & Device ID 90h 90hQPIID QPI ID Read AFh AFhRDSFDP Read SFDP 5Ah 5Ah

Read

READ Read Data 03h 03hFAST READ Fast Read 0Bh 0Bh2READ 2 x I/O Fast Read BBh BBhDREAD 1I 2O Fast Read 3Bh 3Bh4READ 4 x I/O Fast Read EBh EBhQREAD 1I 4O Fast Read 6Bh 6BhW4READ 4 x I/O Fast Read with 4 dummy clock cycles E7h E7h

Erase

SE Sector Erase 20h 20hBE (64K) Block Erase 64KB D8h D8hBE (32K) Block Erase 32KB 52h 52hCE Chip Erase 60h or C7h 60h or C7h

ProgramPP Page Program 02h 02h4PP Quad Page Program 38h 38h

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


Command Symbol Description MX25U3232F MX25U3235F

Device operation

WREN Write Enable 06h 06hWRDI Write Disable 04h 04hDP Deep Power Down B9h B9hRDP Release from Deep Power Down CS# toggle ABh

EQIO Enable QPI 35h 35hRSTQIO Reset (Exit) QPI F5h F5hSBL Set Burst Length C0h C0hWPSEL Write Protect Selection 68h 68h

PGM/ERS Suspend Suspend Program/Erase 75h or B0h B0h

PGM/ERS Resume Resume Program/Erase 7Ah or 30h 30h

NOP No Operation 00h 00h

RSTEN Reset Enable 66h 66hRST Reset Memory 99h 99h

FMEN Factory Mode Enable 41h -

Register

WRSR Write Status Register 01h 01h

RDSR Read Status Register 05h 05h

RDSCUR Read Security Register 2Bh 2Bh

WRSCUR Write Security Register 2Fh 2Fh

RDCR Read Configuration Register 15h -

RDFMSR Read Factory Mode Status Register 44h -ENSO Enter Secured OTP B1h B1h

EXSO Exit Secured OTP C1h C1h

Protection

SBLK Single Block Lock - 36h

SBULK Single Block Unlock - 39h

RDBLOCK Block Protect Read - 3Ch

GBLK Gang Block Lock 7Eh 7Eh

GBULK Gang Block Unlock 98h 98h

WRLR Write Lock Register 2Ch -

RDLR Read Lock Register 2Dh -

RDSPB Read SPB Status E2h -

WRSPB SPB bit Program E3h -

ESSPB All SPB bit Erase E4h -

RDDPB Read DPB Register E0h -

WRDPB Write DPB Register E1h -

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


5. Device ID Code ComparisonThe Manufacturer and Device IDs are not changed, as shown in Table 5-1: ID Code Comparison.

Table 5-1: ID Code Comparison

Electronic Identification MX25U3232F MX25U3235F

RDID 9Fh

Manufacturer ID C2h

Type 25h

Density 36h

RES ABh Electronic ID 36h

REMS 90hManufacturer ID C2h

Device ID 36h

RDID AFh

Manufacturer ID C2h

Type 25h

Density 36h

6. SummaryThe MX25U3232F provides capable of similar or improved performance and backwards compatible with most of the common commands and features of the MX25U3235F.

Moreover, MX25U3232F supports more features as additional 8K-bit secured OTP , Configurable Dummy Cycles, Adjustable Output Driver Strength, Top/Bottom BP Protect, factory mode and advanced Sector Protection Mode.

7. References Table 7-1 shows the datasheet versions used for comparison in this application note. For the most current Macronix specification, please refer to the Macronix Website at http://www.macronix.com

Table 7-1: Datasheet VersionDatasheet Location Date Issued Versions

MX25U3232F Macronix Website July 05, 2019 0.02

MX25U3235F Macronix Website July 12, 2017 1.6

8. Revision History

Table 8-1: Revision History

Revision No. Description Page Date

Rev. 1 Initial Release ALL July 16, 2019

http://www.macronix.com/

P/N: AN0709 Rev. 1, July 16, 2019

APPLICATION NOTE


MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applica-tions only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as its suppliers and/or distributors shall be released from any and all liabil-ity arisen therefrom.

Copyright© Macronix International Co., Ltd. 2019. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, Nbit, Macronix NBit, HybridNVM, Hy-bridFlash, HybridXFlash, XtraROM, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, RichBook, Rich TV, OctaBus, FitCAM, ArmorFlash. The names and brands of third party referred thereto (if any) are for identification purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

the comparison of macroni serial nor flash products ......erase suspend & resume v v program...

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