Technology MappingTechnology Mapping

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OutlineOutline

What is Technology Mapping?What is Technology Mapping? Technology Mapping AlgorithmsTechnology Mapping Algorithms Technology Mapping as Graph CoveringTechnology Mapping as Graph Covering

Choosing base functionsChoosing base functions Creating subject graphCreating subject graph Tree covering problemTree covering problem DecompositionDecomposition Delay OptimizationDelay Optimization

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Technology MappingTechnology Mapping Technology mappingTechnology mapping is the phase of logic synthesis is the phase of logic synthesis

when gates are selected from a when gates are selected from a technology librarytechnology library to to implement the circuit.implement the circuit.

Technology mapping is Technology mapping is normally done after normally done after technology independent optimizationtechnology independent optimization..

Why technology mapping?Why technology mapping? Straight implementation may not be good. Straight implementation may not be good. For example, For example,

F = abcdefF = abcdef as a 6-input AND gate cause a long delay. as a 6-input AND gate cause a long delay.

Gates in the library are Gates in the library are pre-designedpre-designed, they are , they are usually usually optimized in terms of area, delay, power, etcoptimized in terms of area, delay, power, etc..• Fastest gates along the critical path, area-efficient Fastest gates along the critical path, area-efficient

gates (combination) off the critical path.gates (combination) off the critical path.

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Technology Mapping AlgorithmsTechnology Mapping Algorithms

Basic Requirements:Basic Requirements: Provide high quality solutions (circuits).Provide high quality solutions (circuits). Adapt to different libraries with minimal effort.Adapt to different libraries with minimal effort.

• Library may have irregular logic functions.Library may have irregular logic functions. Support different cost functions.Support different cost functions.

• Transistor count, level count, detailed models for Transistor count, level count, detailed models for area, delay, and power, etc.area, delay, and power, etc.

Be efficient in run time.Be efficient in run time. Two Approaches:Two Approaches:

Rule-based techniquesRule-based techniques Graph covering techniques (DAG)Graph covering techniques (DAG)

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OutlineOutline

What is Technology Mapping?What is Technology Mapping? Technology Mapping AlgorithmsTechnology Mapping Algorithms Technology Mapping as Graph CoveringTechnology Mapping as Graph Covering

Choosing base functionsChoosing base functions Creating subject graphCreating subject graph Tree covering problemTree covering problem DecompositionDecomposition Delay OptimizationDelay Optimization

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Base FunctionsBase Functions

Base function setBase function set is a set of gates which is is a set of gates which is universal and is used to implement the gates in universal and is used to implement the gates in the technology library.the technology library. 2-input AND, 2-input OR, and NOT2-input AND, 2-input OR, and NOT 2-input NAND (and NOT)2-input NAND (and NOT)

RecallRecall: A gate (or a set of gates) is : A gate (or a set of gates) is universaluniversal if it can if it can implement all the Boolean functions, or equivalently, it implement all the Boolean functions, or equivalently, it can implement 2-input AND, 2-input OR, and NOT.can implement 2-input AND, 2-input OR, and NOT.

Choose of base functions:Choose of base functions: UniversalUniversal: able to implement any functions.: able to implement any functions. OptimalOptimal: implement functions efficiently.: implement functions efficiently.

• Introduce redundant gates: Introduce redundant gates: 2-input NAND and NOT.2-input NAND and NOT.

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Subject GraphSubject Graph

Subject graphSubject graph is the graph representation of a is the graph representation of a logic function using only gates from a given base logic function using only gates from a given base function set. (I.e., the nodes are restricted to function set. (I.e., the nodes are restricted to base functions.).base functions.).

For a given base function set, subject graph for a For a given base function set, subject graph for a gate may not be unique.gate may not be unique. NAND(a,b,c,d) NAND(a,b,c,d)

==NAND(NAND(NOT(NOT(NAND(a,b)NAND(a,b)),NOT(),NOT(NAND(c,d)NAND(c,d)))) ) ==NAND(NAND(a,NOT(a,NOT(NAND(NAND(b,NOT(b,NOT(NAND(c,d)NAND(c,d)))))))))

All distinct subject graphs of the same logic have All distinct subject graphs of the same logic have to be considered to obtain to be considered to obtain global optimal designglobal optimal design..

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Example: Example: Subject GraphSubject Graph

t1 = d + e

t2 = b + h

t3 = at2 + c

t4 = t1t3 + fgh

F = t4’

F

f

g

d

e

h

b

a

c

t1

t2

t3

t4

inv

nand

base

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Pattern GraphPattern Graph

For any For any library gatelibrary gate, its logic function can be , its logic function can be represented by a graph where each node is one represented by a graph where each node is one of the base functions. This graph is called a of the base functions. This graph is called a pattern graphpattern graph for this library gate. for this library gate.

A pattern graph is a subject graph when the function A pattern graph is a subject graph when the function represents a library gate. represents a library gate.

Similarly, all pattern graphs for the same library Similarly, all pattern graphs for the same library gate have to be considered.gate have to be considered.

TipTip on choosing base function set: Choose those on choosing base function set: Choose those that provide a small set of pattern graphs.that provide a small set of pattern graphs.

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Example: Example: Pattern Graphs for the LibraryPattern Graphs for the Libraryinv(1) nand3 (3)

oai22 (4)

nor(2)nor3 (3)

xor (5)

aoi21 (3)

nand2(2)

… …

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CoverCover

A A covercover is a collection of pattern graphs so that: is a collection of pattern graphs so that: every node of the subject graphevery node of the subject graph is contained in one is contained in one

(or more) pattern graphs (or more) pattern graphs each input required by a pattern grapheach input required by a pattern graph is actually an is actually an

output of some other pattern graph (i.e. the inputs of output of some other pattern graph (i.e. the inputs of one library gate must be outputs from other gates.)one library gate must be outputs from other gates.)

Cost of a CoverCost of a Cover AreaArea: total area of the library gates used (I.e. gates in : total area of the library gates used (I.e. gates in

the cover).the cover). DelayDelay: total delay along the critical path.: total delay along the critical path. PowerPower: total power dissipation of the cover.: total power dissipation of the cover.

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Example: Example: Subject Graph Cover by BaseSubject Graph Cover by Base

F

f

g

d

e

h

b

a

c

Total cost = 23(7 inverters and 8 NANDs)

t1 = d + e

t2 = b + h

t3 = at2 + c

t4 = t1t3 + fgh

F = t4’inv (1)

nand (2)

base

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Example: Example: Better Cover Using the LibraryBetter Cover Using the Library

F

f

g

d

e

h

b

a

c

aoi22(4)

and2(3)

or2(3)

or2(3)

Total cost = 18nand2(2)

nand2(2)

inv(1)

t1 = d + e

t2 = b + h

t3 = at2 + c

t4 = t1t3 + fgh

F = t4’

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Example: Example: Alternate CoveringAlternate Covering

F

f

g

d

e

h

b

a

c

nand3(3)nand3(3)

oai21(3)oai21(3)

oai21 (3)oai21 (3)Total cost = 15

and2(3)

inv(1) nand2(2)

t1 = d + e

t2 = b + h

t3 = at2 + c

t4 = t1t3 + fgh

F = t4’

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Graph Covering FormationGraph Covering Formation

Technology mapping problem: Find a Technology mapping problem: Find a minimum minimum cost covercost cover of the subject graph by choosing from of the subject graph by choosing from the collection of pattern graphs for all the gates the collection of pattern graphs for all the gates in the library.in the library.

DAG-covering-by-DAG is hardDAG-covering-by-DAG is hardNP-hard for a simple case:NP-hard for a simple case: Only 3 pattern graphs (Only 3 pattern graphs (NOT, 2-input NAND, 2-input NORNOT, 2-input NAND, 2-input NOR)) Each node in the subject graph has no more than 2 Each node in the subject graph has no more than 2

fanins and fanoutsfanins and fanouts..

Do We Need to Solve the Problem Optimally?Do We Need to Solve the Problem Optimally? Input logic from technology-independent optimizationInput logic from technology-independent optimization Numerous subject graphs for the same logic networkNumerous subject graphs for the same logic network

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Generic Algorithmic Approach Generic Algorithmic Approach

Represent each logic function of the network as Represent each logic function of the network as a a subject graph (DAG);

Generate all possible pattern graphs (DAGs)for each gate in the technology library;

Find Find an optimal-cost coveringan optimal-cost covering of the subject DAG of the subject DAG using the collection of pattern DAGs.using the collection of pattern DAGs.

Question: how to solve this NP-hard problem?Question: how to solve this NP-hard problem? If subject DAG and pattern DAG’s are trees, an If subject DAG and pattern DAG’s are trees, an

efficient algorithm exists.efficient algorithm exists.

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Optimal Tree Covering by TreesOptimal Tree Covering by Trees

Proposed by Keutzer in program DAGONProposed by Keutzer in program DAGON[DAC’87][DAC’87]

Basic idea: Basic idea: dynamic programmingdynamic programming.. Procedure:Procedure:

Partition the subject graph into trees;Partition the subject graph into trees; Cover each tree optimally;Cover each tree optimally; Piece the tree-cover into a cover for the subject graph.Piece the tree-cover into a cover for the subject graph.

Complexity: finding all sub-trees of the subject Complexity: finding all sub-trees of the subject graph that are isomorphic to a pattern tree. It is graph that are isomorphic to a pattern tree. It is linear in the size of subject tree and the size of linear in the size of subject tree and the size of the pattern trees.the pattern trees.

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Partitioning Subject DAGs into TreesPartitioning Subject DAGs into Trees

Tree circuitTree circuit: a single output circuit in which each : a single output circuit in which each gate (except the output) feeds exactly one gate.gate (except the output) feeds exactly one gate.

Break the graph at all multiple-fanout pointsBreak the graph at all multiple-fanout points

Example:Example:

Leads to Leads to 33 trees trees

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Tree Covering by Dynamic ProgrammingTree Covering by Dynamic Programming

For each primary input, cost to cover is 0;For each primary input, cost to cover is 0; For each (non-leaf) node For each (non-leaf) node vv in the subject trees in the subject trees

(the traverse follows a (the traverse follows a topological ordertopological order)) Recursive assumptionRecursive assumption: we know a best cost cover for : we know a best cost cover for

each of its (transitive) predecessors.each of its (transitive) predecessors. Recursive formulaRecursive formula for cost to cover for cost to cover vv::

• For each matched pattern graph, compute sum of For each matched pattern graph, compute sum of the cost of this pattern and the total best costs of all the cost of this pattern and the total best costs of all fanins to this pattern graph.fanins to this pattern graph.

• Take the minimum as the best cost for node Take the minimum as the best cost for node vv.. Total cost is the sum of best costs for all primary Total cost is the sum of best costs for all primary

outputs of the subject trees.outputs of the subject trees.

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Example: Example: Base Functions & Pattern TreesBase Functions & Pattern Trees

inv 1 nand3 3 oai21 3nor2 2nand2 2

Base Functions:

Pattern Trees:

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nand3 3nand2 15=2+13

nand3 3nand2 5=2+3

nand2 15=2+13

nand2 5=2+3

Example: Example: Subject Graph and CoveringSubject Graph and Covering

inv 1

nand2 2

nand2 2

inv 1

inv 3=1+2

nor2 2 nand3 3 oai21 3

nand2 5=2+(2+1)

nand2 8=2+(5+1)

nand3 3nand2 13=2+(8+3)

inv 14=1+13 nand3 14=3+(8+3)

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oai21 7=3+(3+1)

Example: Example: a Better Coveringa Better Covering

inv 1

inv 1

nor2 2 nand3 3 oai21 3

nand2 5=2+(2+1)

nand2 8=2+(5+1)

nand3 3

nand3 14=3+(8+3)

nand2 2

inv 3

nand3 13=3+(7+3)

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ExampleExample: : Role of DecompositionRole of Decomposition

For a give logic function (including gates from the For a give logic function (including gates from the library), different decomposition to base functions library), different decomposition to base functions create distinct subject function.create distinct subject function.

Example: Example: Base Functions: Pattern Trees: same as before Circuit:

one decompositionand a cover of cost 5

another decompositionand a cover of cost 4

nor2 2 nand3 3 oai21 3

nand3 3nor2 2

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More on Technology MappingMore on Technology Mapping

Rule-based techniquesRule-based techniques DAG covering problemDAG covering problem Tree covering approachTree covering approach Binate covering problemBinate covering problem Boolean matchingBoolean matching Decomposition + mappingDecomposition + mapping Technology mapping for performanceTechnology mapping for performance Gate resizing after technology mappingGate resizing after technology mapping FPGA technology mappingFPGA technology mapping

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Big PictureBig Picture

Given a set of Given a set of logic equations logic equations (not optimized):(not optimized): tt1 = a + bc

t2 = d + e

t3 = ab + ch

t4 = t1t2 + g

t5 = t4h + t2t3

F = t5’

17 literals17 literals

Technology Technology independent independent optimization:optimization: t1 = d + e

t2 = b + h

t3 = at2 + ch

t4 = t1t3 + gh

F = t4’

13 literals13 literals

Technology Technology dependent dependent implementation:implementation:Implement this Implement this network using a set network using a set of gates form a of gates form a librarylibrary, each gate has a cost (i.e. its area, delay, etc.) such that the total cost is minimized.