Synthesis Basics & Optimization

by Sunil

Agenda

• Introduction to Synthesis

• Synthesis Goals

• Synthesis Flow

• Inputs/outputs of synthesis

• Synthesis Optimization techniques

Introduction

• Synthesis is process of converting the high level description (RTL) of design like HDLs (VHDL or Verilog etc) into low level description (optimized gates) of design for given technology libraries, while meeting design specification like area, power, performance and testability.

Goals of synthesis

• Goals of Synthesis

– Minimize number of levels (delay)

– Minimize number of gates (area)

– Minimize signal activity (power)

– Design Rules

– DFT constrains (testability)

– LEC (functionality)

Synthesis – FlowUser setting/controls

Synthesis

Floor-plan Info

Reports/Netlist/def

Read libraries (.db/.lbs/symbol/syn.lib/design ware)

Read Verilog/VHDL(single or Multiple RTL files)

Read Constraints(SDC, timing tcl etc)

Synthesis - Inputs

• RTL files• SDC or constraints (A, P, T, T)• Design rules• Libraries

Synthesis – DC synthesis Basic flow

• Reference: DCUG

Synthesis_dc.setup

Search_path

• Search_path specifies directories that the tool

searches for files specified without directory names

• The search includes looking for technology and

symbol libraries, design files, and so on. • “set search_path [concat $SYNOPSYS/libraries/syn] “

Target Library

• The target library is the technology library you want

to map to during synthesis. It is also known as the

destination library.

• Target library may not contains the pad/memory

libraries or any hard macro libraries. set_app_var target_library “CLN28ATSQ_Pss_V0p95_Tm30_CCS.db “

Link Library

• The link library is a technology library that is used to describe the function of mapped cells prior to optimization, and also for resolved references

• Typically, the link and target library are set to the same technology library.

• The first entry in the list should be "*" to use designs currently in memory.

set_app_var link_library "* $target_library $ADDITIONAL_LINK_LIB_FILES $synthetic_library“

Synthesis – Flow

• Basic Steps of Synthesis– Read and Analyze RTL file ( RTL, libraries)– Elaborate design– Compile Design ( read constraints)– Report Generation– Save Design

• Depends on the constraints and optimization goals some changes can done to Basic steps

Synthesis - Analysis

• HDL (RTL) like VHDL or Verilog files are analyzed for conformance of synthesis.– Syntax error, unsupported statements, constructs,

etc.• Once analysis successful then RTL files will

converted into some intermediate from that tools can understand and ready for next step. – Example: read_file -format verilog -define BLOCK_A_DEF { block_a.v block_b.v }– Example: analyze -f verilog -update { block_a.v block_b.v }

Synthesis - Elaboration

• The intermediate form from analysis step in converted into technology independent design.

• Design is expressed in term of functional block and generic logic gates.

Constraining the Design

• Two types Design Rule Constraints

Optimization Constraints

Defining Design Environment

Defining Operating Conditions

Modeling Wire Loads

Before Compilation

• Make sure that all HDL files are read, all libraries are read-in.

• Constrains are proper• Operating condition are applied.• One can check different reports before

compile to make sure design ready for compile.

Before Compilation

• Report_port

• Report_design

• Report_clock

• Report_attributes –design

Synthesis – during compilation

• Compile maps and optimize the technology independent design into technology specific design based on area, power and timing requirements.

• This is iteration process, where optimization happens to meet the synthesis or design goals.

• compile [-map_effort low | medium | high] [-incremental_mapping] [-verify] [-scan]

Compile strategy

Top-Down

Bottom-up

Optimizing the Design• The optimization (compile) step translates the HDL

description into gate-level net-list using the cells available in the technology library. The optimization is done in several phases.

• In each optimization phase different optimization techniques are applied according to the design constraints.

• The following is somewhat simplified description of optimizations performed during synthesis. – Design Compiler performs optimizations on three levels:

architectural, logic-level, and gate-level.

• Reference: Design Compiler User guide

Optimization – Architecture Level• Architecture optimization level work on HDL,

which are high abstraction level. These techniques works on unmapped stage.

Arithmetic Optimizations

Resource Sharing

Selecting DesignWare implementations

Reference: Design Compiler User Guide

Optimization – Logic Level

• This optimization works technology independent level (GTECH level): Two such optimization are

Structuring

Flattening

Reference: Design Compiler User Guide

Optimization – Gate Level

• Gate level optimization work on technology-independent netlist and maps it to the library cells to produce a technology-specific gate-level netlist

MappingDelay optimizationDesign rule fixingArea optimization

Reference: Design Compiler User Guide

Optimization Phases

• Optimization is process of modifying the netlist which meeting specific for given technology library.

• Type of optimization (Design Compiler)

– Combination optimization

– Sequential optimization

– Local optimization

Design Compiler User guide

Optimization Phases• Combination Optimization : Transform logical

description of combo ckt to gate level net-list

Design Compiler User guide

Optimization Phases• Technology independent opt

– It work at GTECH cells level. The optimization is done algebraic and Boolean logic equation to meet area and timing.

• Mapping– Tools tries to select stdcell from library to implement logic structure. – Area and timing are considered while mapping and restructuring.

• Technology specific optimization– Tools work on the mapped design to reduce the timing and area (power also)

Design Compiler User guide

Optimization Phases• Sequential optimization– Initial sequential optimization

• Maps generic sequential cells to library specific sequential cells. • This mapping might not be optimal due to lack complete timing

information.– Final sequential optimization

• Maps and optimization the sequential cells to meet timing on critical paths.

• Delay through combination or pad logic is known and mapping is more accurate.

• Two task– Improve the timing by choosing higher performance cells– Try to reduce the area and delay by merging some of combos in

sequential cells or high speed sequential cells

Design Compiler User guide

Optimization Phases• Local optimization

– Incremental changes to design at gate level to meet timing and area– Some of the are

• Gate restructuring• Cloning• Buffer insertion/deletion• sizing• Pins swapping

Design Compiler User guide

After Compilation

• check_timing

• check_design

• Report_area

• Report_power

• Report_timing

Synthesis – Report

• Report are to analyze the design whether synthesis met the design goals.– Area report– Power reports– Timing reports– Coverage report (DFT)– L.E.C– Misc (like path report, analysis coverage,

histograms, qor reports, etc)

After Compile – Save Design

• You can save your design in many formats, but the most common are as gate-level verilog ("structural verilog") or DC "db" format. Both commands are shown here:– write -hierarchy -format db -xg_force_db -output

$GATE_PATH/$TOPLEVEL-$STAGE.db– write -hierarchy -format verilog -output

$GATE_PATH/$TOPLEVEL-$STAGE.v

Synthesis – Y Chart