synaptic labs’ hyperbus memory controller (hbmc) tutorial ......hbmc tutorial 001 2.1.4.2....

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Synaptic Labs’ HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices

T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP

This tutorial describes a simple reference design for S/Labs HBMC IP targeted specifically to the Intel Cyclone 10 LP evaluation kit and the devboards GmbH HyperMAX 10M25 and 10M50 boards. Most HBMC customers using any of these boards board will want to start with this tutorial.

This tutorial describes key aspects of a pre-configured Quartus Prime .qsys reference project and then walks through the process of generating and compiling that .qsys project. This tutorial then describes how to compile the example Nios II source code, integrate the firmware into the FPGA bitstream and then run the reference design on the development board.

The reference project for this Tutorial is bundled with a Free Trial License for the full-edition of S/Labs HBMC IP

That Quartus License Key never expires.

After completing this tutorial, readers may like to proceed to the second tutorial called “T001B: A Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM device using S/Labs' HBMC IP”. That tutorial shows how to download the Nios II firmware into the FPGA device using the Nios II software development environment.

Benjamin Gittins Chief Technical OfficerMbl: +995 551 026 588 [email protected]

Synaptic Laboratories Ltd.Company ID 41272593www.synaptic-labs.com [email protected], July 16, 2018

T001A 16 July 2018 +995 551 026 588 © www.synaptic-labs.com page � of �1 27

http://www.synaptic-labs.com

mailto:[email protected]


mailto:[email protected]

Table of Contents

Synaptic Labs’ HyperBus Memory Controller (HBMC) Tutorial for Intel FPGA devices 1

T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP 1

Table of Contents 2

1. Setup your development environment 3

2. Contents of the reference project 4

3. Open the reference Quartus Project 5

4. Open the reference Qsys project 6

5. Explore and configuring the reference Qsys project 6

6. Generating the Qsys Design 14

7. Preparing the firmware 15

8. Create a simple application and BSP 15

9. Configure the Board Support Package (BSP) 17

10. Generate the BSP and clean the project 21

11. Copy the memory testing source code 21

12. Configure the source code 22

13. Build the Nios II Application 22

14. Generate memory initialization files 23

15. Update the memory initialization field(s) in Qsys 24

16. Synthesize and assemble the Design 25

17. Program the FPGA Bitstream into the FPGA device 26

18. Run the nios2-terminal application 27



1. Setup your development environment1.1. Obtain core materials

1.1.1. Download and install the latest version of Quartus Prime Lite Edition or Standard Edition (18.x at the time of publication) on your PC, please ensure that your PC meets the required minimum specification.

1.1.2. Create a folder/directory for your work. We suggest: C:\prj\

1.1.3. For Intel's C10 LP Evaluation Kit:

1.1.3.1. Download the reference design HyperNios_Project_C10LP:https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_C10LP.zip

1.1.3.2. Extract in the folder/directory: C:\prj\

1.1.4. For devboards HyperMAX boards:

1.1.4.1. Download reference design HyperNios_Project_HM10M25 from:https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_HM10M25.zip

1.1.4.2. Extract in the folder/directory: C:\prj\

1.2. Read the License Agreement and Setup your License Key

1.2.1. This version of the tutorial is bundled with:

1.2.1.1. A copy of the full edition of S/Labs HBMC IP found in the ip folder

1.2.1.2. A Free Trial License Credential with Embedded Quartus License Key for S/Labs HBMC IP that never expires.

1.2.2. Before you Use the HBMC IP, please read the License Agreement and related files in this bundle: …-LA-IDX-…-Agreement.pdfand …LA-ID-…-ExtendedTerms.pdf

1.2.3. Please install (copy and paste) the entire License Credential with Embedded License Key into Quartus Prime: …-LC-ID-…-Full-Edition-HBMC-For-Intel-Devices.txt

1.2.4. If required, search the phrase: “Intel FPGA Software Installation and Licensing Quick Start” on the Internet to find instructions on how to install License Keys into Quartus Prime.



https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_C10LP.zip

https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_C10LP.zip

https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_HM10M25.zip

https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/HyperNios_Project_HM10M25.zip

https://duckduckgo.com/?q=%E2%80%9CIntel+FPGA+Software+Installation+and+Licensing+Quick+Start%E2%80%9D

1.3. Setup your board

1.3.1. If you have a Cyclone 10 LP Evaluation Kit Board:Ensure that DIP Switch 4 on the Cyclone 10 LP EK board is set to ON as this bypasses the virtual JTAG system and simplifies board programming.Note: this board can be powered over USB. In this case, no power supply is required for this simple low power reference design.

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2. Contents of the reference project2.1. Synaptic Labs' HyperBus Memory Controller (HBMC) Reference design projects includes the

following files and directories:

2.1.1. The root folder of the reference project contains the Quartus Prime and Qsys project files for the first reference project.

2.1.2. The ip folder contains S/Labs HBMC encrypted IP and License Key.

2.1.3. The software folder is used as the workspace folder for Eclipse

2.1.4. The source folder contains the source code for:

2.1.4.1. The simple TestHyperRAM program from devboards GmbH as used in this HBMC Tutorial 001

2.1.4.2. S/Labs’ TestMbs memory bandwidth benchmark for HyperRAM program which is used in the HBMC Tutorial 002, which can be downloaded from the link below: https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/SynapticLabs-HBMC-Tutorial001B-NiosII-SwHyperRAMBenchmark.pdf

2.2. Please contact S/Labs about enabling simulation with Altera's ModelSim Simulator.



https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/SynapticLabs-HBMC-Tutorial001B-NiosII-SwHyperRAMBenchmark.pdf

https://synaptic-labs.s3.amazonaws.com/pub/2017-Designs/SynapticLabs-HBMC-Tutorial-001/SynapticLabs-HBMC-Tutorial001B-NiosII-SwHyperRAMBenchmark.pdf

3. Open the reference Quartus Project 3.1. In the menu bar of Quartus Prime, select File → Open Project…

3.2. Select the file NIOS_HyperRAM.qpf in the project directory

3.3. Click the [ Open ] button.

3.4. Check the correct FPGA device is selected:

3.4.1. Every Quartus project is targeted to a specific FPGA device that must match the physical FPGA device on the Board. In particular, for devboards GmbH HyperMAX 10M25 and 10M50 boards, check that the FPGA device in Quartus Prime matches the physical device on the board.

3.4.2. The HyperMAX 10M25 board employs the 10M25DAF256C7G device.

3.4.3. The HyperMAX 10M50 board employs the 10M50DAF256I7G device.

3.4.4. The Intel C10LP Evaluation board employs the 10CL025YU256I7G device

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3.5. If you need to change the FPGA device for your specific board:

3.5.1. Ensure that there are no instances of the Intel Platform Designer (Qsys) application running.

3.5.2. Right click on the device name.

3.5.2.1. Select “Devices…” in the pop up window.

3.5.2.2. A new window will open. Select the “Device” tab.

3.5.2.3. Copy the required device name into the “Name filter:” field.

3.5.2.4. A popup window will ask: “Do you want to remove all location assignments?” Click on the [ No ] button.

3.5.2.5. Select the requested device in the “available devices:” field so that it is highlighted in blue.

3.5.2.6. Then click on the [ Okay ] button.

3.5.2.7. The Quartus project file (.qpf) and the Platform Designer file (.qsys) are now both configured for the FPGA device you selected.



4. Open the reference Qsys project4.1. In the menu bar of Quartus Prime, select Tools → Platform Designer

4.2. Select the file hypernios.qsys in the project directory

4.3. Click the [ Open ] button.

5. Explore and configuring the reference Qsys project5.1. Regarding the components employed in the reference project

5.1.1. The reference Qsys project in this tutorial employs a NiosII/f processor, S/Labs’ HyperBus Memory Controller (HBMC) IP, Altera’s On-Chip Memory module to store code and data in on chip SRAM, and various peripherals such as Altera’s JTAG UART and timer modules as illustrated below:

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5.2. Nios II/f processor configuration

5.2.1. In this example, the Nios II/f Reset vector and Exception vector are mapped to onchip_memory as illustrated below. This means that the Nios II/f processor will look for the boot code and exception handling / interrupt code in the onchip_memory module.

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5.2.2. As illustrated below, the instruction cache and data cache of the Nios II/f core should both been set to 4Kbytes in size to accelerate software performance. Increasing the cache size is often the easiest way to improve software performance in a Nios II/f design.

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5.2.3. Please note: Ensure that the instruction and data caches have both been configured with their burstcount signal enabled so that both caches issue burst memory transfer requests. This is required because:



5.2.3.1. The HyperBus protocol employs burst memory transfer requests with modest delays between inserted between back-to-back memory transfer operations; and

5.2.3.2. The HyperBus protocol requires burst access with a word width of at least 256-bits in length (e.g. 8 x 32-bit words) to achieve effective memory bandwidth utilization of the HyperBus memory channel.

5.2.3.3. SLL’s HBMC employs an Avalon interface with burst mode support.

5.2.3.4. All Avalon Bus Masters accessing HyperBus memory devices, such as the instruction and data ports of the Nios II, must also be set to burst mode to achieve acceptable levels of effective memory bandwidth utilization of the HyperBus Channel.

5.3. Configuring S/Labs HBMC IP

5.3.1. S/Labs HyperBus Memory Controller IP has been pre-configured in this reference project. We will describe various configuration options that you may wish to change below.

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5.4. Configuring S/Labs HBMC IP - Master Tab

5.4.1. The full edition of SLL HBMC IP supports any combination of HyperFlash and HyperRAM. The full edition of SLL HBMC IP also includes the option to manually configure each HyperBus device connected to the HBMC IP.

5.4.2. In the "Master Configuration" tab:

5.4.2.1. To configure the project to just use HyperRAM on the Intel C10LP/HyperMAX board. the FPGA board type field is set to either:

• Devboards - HyperMAX 10M25 (HyperRAM) or

• Devboards - HyperMAX 10M50 (HyperRAM) or

• Intel – Cyclone 10 LP Evaluation Kit (HyperRAM)



5.4.2.2. To configure the project to use both HyperFlash and HyperRAM on the HyperMAX board:

• Devboards - HyperMAX 10M25 (HyperFlash and HyperRAM) or

• Devboards - HyperMAX 10M50 (HyperFlash and HyperRAM)

• Note: At the time of this document’s publication, Intel's Cyclone 10LP evaluation board does not contain a HyperFlash device

5.4.2.3. If this is your first time through the tutorial, S/Labs strongly recommends using a HyperRAM only configuration. For Example:

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5.5. Configuring S/Labs HBMC IP - Clock and PLL Tab

5.5.1. The PLL Configuration field is set to External PLLPlease note: S/Labs recommends all customers now use the “External PLL” mode of our HBMC IP. The External PLL provides you far greater flexibility and control over the clock-speed settings available for your specific FPGA device.

5.5.2. The Avalon and HyperBus clock configuration field is set to Two clocks

5.5.3. The HyperBus channel clock frequency field is automatically detected

5.5.4. The Shared Avalon clock frequency field is automatically detected

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5.6. Configuring S/Labs HBMC IP - Ingress Avalon Slave 0 (IAVS0) Tab

5.6.1. The IAVS0 port is used to access all HyperBus memories connected to the HyperBus Memory Controller IP. The most common configuration of the IAVS0 port is as follows.

5.6.2. IAVS0: Ingress Avalon port stage

5.6.2.1. The [X] Enable Avalon write capability field is checked

5.6.2.2. The [X] Enable Avalon byte-enable capability field is checked

5.6.2.3. The [ ] Register Avalon write data field is left unchecked

5.6.3. IAVS0: Burst Converter and address decoder stage

5.6.3.1. the max BurstSize (in Words) field is set to 8 words (This matches the burst length of the Nios II/f caches)

5.6.3.2. The lineWrapBursts field is set to true (This Nios II/f instruction cache issues line wrapping bursts)

5.6.4. IAVS0: Ingress Avalon return stage

5.6.4.1. The [ ] Register Avalon read data path field is unchecked

5.6.4.2. The [ ] Use Avalon Transaction Response field is unchecked

5.6.5. Please note that the GUI interface includes significant amounts of inbuilt documentation. Moving your mouse over a configuration field pops up the on-screen help for that field. That documentation will help you select the correct configuration for your future projects.

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5.7. Configuring S/Labs HBMC IP - Device 0 Info Tab

5.7.1. The “Device 0 Info” tab provides information about the HyperBus device connected to chip select 0 of the HyperBus channel. In this case, Device 0 may or may not map to HyperFlash in this reference project depending on how you have configured the reference project.

5.7.2. If in the "Master Configuration" tab, the FPGA board type field is set to Devboards - HyperMAX 10M25/50 (HyperRAM) or Intel – Cyclone 10LP Evaluation Kit (HyperRAM), the Device 0 Info tab remains relatively empty as illustrated below.

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5.7.3. If in the "Master Configuration" tab, the FPGA board type field is set to Devboards - HyperMAX 10M25/50 (HyperFlash and HyperRAM), then you will see several configuration and timing parameters for the HyperFlash memory.

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5.7.4. In this tutorial the “[x] Use factory default settings” field for this HyperBus device is left checked.

5.7.5. Unticking this box can result in improved system performance in exchange for increased circuit area to configure the HyperBus device at power on. All system designers will want to consider these extra configuration settings in their production designs.



5.8. Configuring S/Labs HBMC IP - Device 1 Info Tab

5.8.1. The “Device 1 Info” tab provides information about the HyperBus device connected to chip select 1 of the HyperBus channel. In this reference project, Device 1 is typically mapped to a HyperRAM device.

5.8.2. This tab show the parameters, configuration and timing for the HyperRAM memory.

5.8.3. The exact parameters on your screen may be different because:

5.8.3.1. The HyperMAX 10M25 board employs a 64 Megabit HyperRAM device.

5.8.3.2. The HyperMAX 10M50 board employs a 128 Megabit HyperRAM device.

5.8.3.3. The Intel C10LP Evaluation kit employs a 128 Megabit HyperRAM device.

5.8.4. In this tutorial the “[x] Use factory default settings” field for this HyperBus device is checked

5.8.5. Unticking this box can result in improved system performance in exchange for increased circuit area to configure the HyperBus device at power on. All system designers will want to consider these extra configuration settings in their production designs.



5.9. Configuration of Altera’s On-Chip Memory

5.9.1. In this reference project, Altera's On-Chip Memory is configured as a 40 Kilobyte single port RAM. We will setup this memory to be initialized by the Nios II SBT for Eclipse

5.9.2. Please ensure that:

5.9.2.1. [x] Initialize memory content is Ticked

5.9.2.2. [x] Enable non-default initialization file is Ticked

5.9.2.3. [x] User created initialization file is

./software/HelloWorld/mem_init/onchip_memory.hex Note: If you do not specify an initial .hex filename, Nios II SBT will not generate the memory initialization file.

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6. Generating the Qsys Design6.1. Once the Qsys project has been correctly configured, press the [ Generate HDL… ] button on

the bottom right hand side of the Qsys window. The following dialog box will then open:

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6.2. In the Synthesis section, set the Create HDL design files for synthesis field to Verilog.

6.3. In the Simulation section, set the Create simulation model field to None.

6.4. In the Output Directory section, accept the default value for the Path: field.

6.5. Then click on the [ Generate ] button.

6.6. You may see a Save System window. If you do, click the [ Close ] button to save the project design and close the save window.

6.7. Generating the .qsys project updates the .SOPC file which will be used by the Nios II Software Build Tools (SBT) environment.

6.8. Click the [ Close ] button to close the generate window.

6.9. You may want to close the Platform Designer window.



7. Preparing the firmware 7.1. Open the NIOS II Software Built Tools for Eclipse

7.1.1. In Quartus Prime, go to the menu bar and select Tools → NIOS II Software Built Tools for Eclipse

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7.1.2. Click the [ Browse… ] button. A new file selector window will open. In this tutorial, select the software folder located inside the project folder as the workspace directory. Then click the [ OK ] button. The file selector window will close.

7.1.3. Be sure to leave the [ ] Use this as the default field unticked.

7.1.4. Click the [ OK ] button.

7.1.5. The Nios II Eclipse development environment will now open.

8. Create a simple application and BSP8.1. The software folder in the reference project is empty. This is because technical problems can

be experienced when moving the Eclipse workspace directory between Windows and Linux Systems. The Project Explorer tab is empty because the software folder is empty.

8.2. We need to create a Nios II application , and a Nios II board support package for that Nios II application:

8.2.1. In the Eclipse window, go the menu bar and select: File → New → NIOS II Application and BSP from Template

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…/software


8.2.2. A new window will pop up: (most of the fields below will initially be empty)

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8.2.3. In the Target hardware information section, click on the [ … ] button.

8.2.4. A file browser window will open. Locate and select the hypernios.sopcinfo file generated by Qsys which was stored in the reference project directory. Click [ Open ].

8.2.5. It may take around 30 seconds for the Eclipse application to parse the .sopcinfo file.

8.2.6. Select a Project name. In this example, we are using HelloWorld as the project name.

8.2.7. Ensure that: [x] Use default location is ticked.

8.2.8. We now need to select a template from the Project Template list. In this example, select the Hello World template.

8.2.9. Press the [ Finish ] button to complete the current step.


/hypernios.sopcinfo


8.3. The Nios II SBT will now generate:

8.3.1. a software/HelloWorld folder that contains the hello_world.c file. We will replace that hello_world.c file with a custom program that tests the HyperRAM device later in this tutorial.

8.3.2. a software/HelloWorld_bsp folder that contains the Nios II Board Support Package (BSP) hardware abstraction layer (HAL).

8.3.3. These two folders should now be visible in the Project Explorer tab.

9. Configure the Board Support Package (BSP)9.1. The Nios II BSP must be configured before we can compile the source code.

9.2. In the Project Explorer tab, right click on: HelloWorld_bsp → Nios II → BSP Editor…

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9.3. A BSP Editor window will open.

9.4. In the Main Tab of the BSP Editor (located on the left hand side), select: Settings → Common

9.5. Set the sys_clk_timer field to timer_0 This is used to generate a recurring system clock interrupt for the hardware abstraction layer.

9.6. Set the timestamp_timer field to interval_timer This field is used to enable the hardware abstraction layer to perform fine precision timing.

9.7. The Newlib ANSI C standard library can be configured as small or normal:

9.7.1. Generally, when mapping code and data to on-chip memory:

9.7.1.1. Tick the [x] Enable small C library field to reduce the size of the executable code generated by the hardware abstraction layer (HAL). Ticking this option also reduces the functionality and performance of the HAL. Please note that the inbuilt memset() and memcpy() routines will be very slow.

9.7.2. Generally, when mapping code and data to HyperRAM and/or HyperFlash:

9.7.2.1. Untick the [ ] Enable small C library field to increase the functionality and performance of the executable code generated by the hardware abstraction layer (HAL). Please note that the inbuilt memset() and memcpy() routines will achieve good performance. However, the executable code will be considerably larger.

9.7.3. We recommend Tick the [x] Enable small C library for this specific tutorial.

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https://en.wikipedia.org/wiki/Newlib

9.8. In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings → Advanced → hal.

9.9. Then, in the panel on the right hand side, scroll down to find the hal.linker as illustrated below.

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9.9.1. For the purpose of this tutorial, the following configuration will work:

9.9.1.1. Tick [x] allow_code_at_reset

9.9.1.2. Tick [x] enable_alt_load

9.9.1.3. Tick [x] enable_alt_load_copy_rodata

9.9.1.4. Tick [x] enable_alt_load_copy_rwdata

9.9.1.5. Tick [x] enable_alt_load_copy_exception

9.9.2. Please note: This specific configuration may not be the best configuration for your future project’s needs. Please refer to Altera’s documentation for detailed information on how to setup the hal.linker fields in the: Generic Nios II Booting Methods User Guide, UG-20001, 2016.05.24 https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf



https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/niosii_generic_booting_methods.pdf

9.10. Select the Linker Script tab of the BSP Editor window.

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9.10.1. In this tutorial, we are going to:

9.10.1.1. Map the reset vector (.reset) to the onchip memory (onchip_memory2_0) . This is generated by Qsys and depends on the location of the Nios II reset vector.

9.10.1.2. Map the exception vector (.exceptions) to the onchip memory (onchip_memory2_0). This is generated by Qsys and depends on the location of the Nios II exception vector.

9.10.1.3. Map the instruction code (.text) in the onchip memory (onchip_memory2_0)

9.10.1.4. Map all other data regions (.bss, .heap, .rodata, .rwdata, .stack) to the onchip memory (onchip_memory2_0)

9.10.2. This will map all the Linker Memory Regions of the GCC tools to the on-chip SRAM.

9.10.3. For more information about Linker Memory Regions in general, please see:Nios II Gen2 Software Developer's Handbook, NII5V2Gen2, 2017.05.08 Section 5, Nios II Software Build Tools https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf

9.11. Click on the [ Exit ] button on the bottom right hand corner of the BSP Editor window.

9.12. Then click on the [ Yes, Save ] button on the Save Changes window to save the BSP settings.



https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf

10. Generate the BSP and clean the project10.1. The software developer must regenerate the BSP every time the Platform Designer (.qsys)

project is regenerated.Among other things, this ensures that the device drivers and memory addresses of peripherals are reflected correctly in the hardware abstract library.

10.2. To (re)generate the BSP:

10.2.1. Go to the Nios II eclipse window.

10.2.2. Right click on HelloWorld_bsp project then select Nios II → Generate BSP.

10.2.3. Right click on the HelloWorld_bsp project then select Clean Project to delete any intermediate files generated by the gcc compiler for this board support package library.

10.2.4. Right click on the HelloWorld project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application folder.

11. Copy the memory testing source code11.1. We now want to replace the original HelloWorld.c source code with software that checks the

HyperRAM. Copy and replace the files located in: …/source/TestHyperRAMto: …/software/HelloWorld

11.2. In the project explorer window of Eclipse, right click on the HelloWorld folder. Then select Refresh. The new source code files should now be visible within Eclipse.



12. Configure the source code12.1. If the FPGA board type field of the "Master Configuration" tab of the HBMC IP, is set to

Devboards - HyperMAX 10M25/50 (HyperFlash and HyperRAM), then please // COMMENT out line 8 in the new hello_world.c file.

12.2. From a HyperRAM only configuration:

12.3. To a HyperFlash and HyperRAM configuration:

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13. Build the Nios II Application13.1. We now want to run the ‘C’ compiler and linker:

13.1.1. Go to the Nios II eclipse window.

13.1.2. Go to the menu bar and select: Project → Build All

13.1.3. If the project produces warning / error messages, you may need to build the project twice.



13.2. The executable firmware (.ELF) for the Hello World application is now generated in the software/HelloWorld folder.

13.3. That .ELF can be downloaded directly into on-chip SRAM and off-chip SDRAM using the Nios II Debugger. However, the .ELF file can not be embedded directly into the FPGA bitstream file, or programmed/written directly into the HyperFlash memory.

13.4. To embed the firmware into the FPGA bitstream, or to program/write the firmware directly into the HyperFlash memory, we need to convert the .ELF file into one or more memory initialization files which we will do in the next section.

14. Generate memory initialization files 14.1. If we want to embed the firmware into the on-chip SRAM of the FPGA when program the FPGA

device using a FPGA bitstream, or if we wish to program the HyperFlash memories, we need to generate “memory initialisation” .hex file/s from the .elf file we just generated.

14.2. In the Project Explorer tab, right click on: HelloWorld → Make Targets → Build…

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14.3. A Make Targets window will open.

14.4. Select mem_init_generate

14.5. Click on the [ Build ] button.

14.6. New hex files will be generated. These files will be located in Project folder → Software → HelloWorld → mem_init

14.7. The file onchip_memory.hex can be embedded into the FPGA bitstream to initialize the on chip memory as described in the next section.



15. Update the memory initialization field(s) in Qsys15.1. Before synthesizing the design, it is important to ensure that the initialization file for the on chip

memory is set to the exact path of the .hex file in the Qsys project. This is because it is possible to create multiple applications within a Nios II Eclipse workspace.

15.2. In Platform Designer, open the hypernios.qsys project.

15.3. Open the parameters for the On-Chip Memory module.

15.4. Ensure that the User created initialization file points to the onchip_memory.hex file generated by NIOS II SBT for Eclipse for the application you want to use. In this tutorial we only have one Nios II application located in the software/HelloWorld folder.

15.5. As indicated previously, we recommend using the filename with a relative path: ./software/HelloWorld/mem_init/onchip_memory.hex

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15.6. Please note: each and every time you change the .qsys project, you will need to:

15.6.1. Save and regenerate the Platform Designer .qsys file

15.6.2. Then regenerate the Nios II BSP

15.6.3. Then clean the projects and rebuild the (.elf) Nios II Application

15.6.4. Then regenerate the (.hex) memory initialization binaries

15.7. As we set the path and filename correctly at the start of the tutorial, you do not need to execute the above steps at this time.



16. Synthesize and assemble the Design16.1. Go to the Quartus Prime window.

16.2. In the menu bar, select:Processing → Start Compilation

16.3. Compilation takes around 2 to 3 minutes on most modern desktop computers

16.4. Windows users, please note: If the compilation fails you may need to reduce the path length of your project folder. This is because some versions of Windows have a maximum path length of 260 characters which can be easily exceeded when compiling projects in Quartus Prime.If you change the path, make sure all .hex files in the Qsys project are set correctly.

16.5. The assembler step will create the SRAM FPGA Bitstream file (.sof) with the memory initialisation file (.hex) for the SRAM embedded in that FPGA Bitstream file.

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16.6. If at a later time you recompile your Nios II Code, you will need to embed the new .hex files into the FPGA bitstream. The fastest way to do this is:

16.6.1. In the menu bar, select:Processing → Update Memory Initialization File This will ensures the latest version of the .hex file will be used during the assembly step.

16.6.2. In the menu bar, select:Processing → Start → Start Assembler



17. Program the FPGA Bitstream into the FPGA device17.1. Connect the HyperMAX / Intel C10 LP Evaluation Kit board into the USB port of your computer

17.2. Open the Quartus Prime window

17.3. To start the Altera Programmer select:Tools → Programmer

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17.4. Click on “Hardware Setup…”.

17.5. A new window will open.

17.6. Double Click on the HyperMax (or Intel C10 LP Evaluation Kit ) device

17.7. Click the [ Close ] button.

17.8. If the NIOS_HyperRAM_time_limited.sof is not already selected:

17.8.1. Click “Add File...” in the programmer window.

17.8.2. Go to the output_files folder

17.8.3. Double click on NIOS_HyperRAM_time_limited.sof

17.8.4. Click the [ Start ] button

17.9. The FPGA bitstream will now be programmed into the SRAM configuration memory of the FPGA device.

17.10. A window called “OpenCore Plus Status” should open.



18. Run the nios2-terminal application18.1.1. In Linux:

Open a Linux command shell / terminal

18.1.2. In Windows: Run the Nios II Command Shell application from the Windows start menu.

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18.1.3. Run the nios2-terminal command from the terminal.

18.2. Messages similar to the one below should be displayed in the command shell.

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18.3. Please note that for the HyperRAM only test: The HyperFLASH CFI test is not executed and the HyperRAM base address will be located at 0x00000000.



synaptic labs’ hyperbus memory controller (hbmc) tutorial ......hbmc tutorial 001 2.1.4.2....

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