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13th IEEE International Conference on Advanced Thennal Processing of Semiconductors - RTP 2005 Superior Spike Annealing Performance in 65nm Source/Drain Extension Engineering Ching I Li", Chin Cheng Chien', K T Huang', Po Yuan Chen', Hsiang Ying Wang1, S F Tzoul, Stan Chen2*, Jones Lin2, Tony Fu2, Riyang Tandjaja3 and Sundar Ramamurthy3, Eagle Chung2, Jason Chuang2, Wen-Shan Chen2 United Microelectronics Corp., Central Research and Development Division,No. 18, Nan-Ke Rd. II, Science-Based Industrial Park, Shan-hua, Tainan County, Taiwan, R.O.C Tel: +886-6-5054888 Ext: 12459; Fax: +886-6-5050960; E-Mail: china i li(unumc.com 2Applied Materials Taiwan, Hsinchu, Taiwan, ROC, 300 3Applied Materials Inc., Santa Clara, California, USA, 95054 Abstract To meet the requirements of smaller devices while still maintaining high performance, it is necessary to form shallow source/drain extensions with high activation. For 65nm devices, reducing the "peak width" of spike annealing will enhance device performance. Two RTP tools were compared by 65nm device performance with different residence times (1.4s and 1.85s). Spike anneal thermal profile of the shorter residence time (1.4s) demonstrated -4% reduction in Cov and improved Vt roll-off based on device data. The improvement is due to the efficient suppression of lateral diffusion in source/drain extensions. RTP A demonstrates this improvement while retaining the same Lon/off performance as delivered in the larger thermal budget spike anneal system. In this paper we show that shorter residence time ("peak width") is required to improve ultra-shallow junction performance in 65nm devices as characterized by Io,Ioff, and Vt parameters. Introduction Experiment Spike annealing has replaced soak annealing as the RTA process for source/drain areas for a couple of years. Spike annealing offers a lower thermal budget for the sub-130nm technology node. It can suppress lateral diffusion in source/drain extensions. Since spike annealing was introduced to 65nm devices, two RTP systems have been evaluated for spike temperature profile control. The critical factor in choosing a process is device performance, such as Cov and Vt roll-off. The 65nm production process is based on experience at the 90nm mode; however, the thermal budget and uniformity requirements are more rigid with the shrinking of devices. A lower thermal budget is required to reduce junction depth in profile tuning. More aggressive spike annealing demonstrated ability to meet 65nm node demand. Most experiments were carried out on RTP A, which has a honeycomb lamp design and achieves a sharper temperature profile. Sharpness of residence time (the duration of peak temperature - 50°C) is extremely critical for spike annealing of source/drain extensions because it directly influences electronic characteristics. The recipes were set up with various residence times. They were tuned by changing the cooling rate, since ramp-up rates above 200°C/sec do not change sharpness much. Different cooling rates were achieved by adjusting helium flow in the recipe. Four residence times are adopted to investigate the influence of junction depth and sheet resistance. The residence times are 1.4 seconds, 1.6 seconds, 1.7 seconds, and 2.06 seconds. Nitrogen gas with 1.5slm helium flow achieved 1.4 seconds of residence time. Higher residence time is tunable by decreasing helium flow. 0.5slm helium results in 1.6 seconds residence time, and no helium flow brings about 1.7 seconds and 2.06 seconds with a slower cooling rate. The temperature profiles are compared and shown in Figure 1 below. 0-7803-9223-X/05/$20.00 02005 IEEE 163

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13th IEEE International Conference on Advanced Thennal Processing of Semiconductors - RTP 2005

Superior Spike Annealing Performance in 65nm Source/Drain ExtensionEngineering

Ching I Li", Chin Cheng Chien', K T Huang', Po Yuan Chen', Hsiang Ying Wang1, S F Tzoul,Stan Chen2*, Jones Lin2, Tony Fu2, Riyang Tandjaja3 and Sundar Ramamurthy3, Eagle Chung2, Jason Chuang2,

Wen-Shan Chen2

United Microelectronics Corp., Central Research and Development Division,No. 18, Nan-Ke Rd. II,Science-Based Industrial Park, Shan-hua, Tainan County, Taiwan, R.O.C

Tel: +886-6-5054888 Ext: 12459; Fax: +886-6-5050960; E-Mail: china i li(unumc.com2Applied Materials Taiwan, Hsinchu, Taiwan, ROC, 300

3Applied Materials Inc., Santa Clara, California, USA, 95054

Abstract

To meet the requirements of smaller devices while still maintaining highperformance, it is necessary to form shallow source/drain extensions with highactivation. For 65nm devices, reducing the "peak width" of spike annealing willenhance device performance. Two RTP tools were compared by 65nm deviceperformance with different residence times (1.4s and 1.85s). Spike anneal thermalprofile of the shorter residence time (1.4s) demonstrated -4% reduction in Cov andimproved Vt roll-off based on device data. The improvement is due to the efficientsuppression of lateral diffusion in source/drain extensions. RTP A demonstrates thisimprovement while retaining the same Lon/off performance as delivered in the largerthermal budget spike anneal system. In this paper we show that shorter residencetime ("peak width") is required to improve ultra-shallow junction performance in65nm devices as characterized by Io,Ioff, and Vt parameters.

Introduction Experiment

Spike annealing has replaced soak annealing as theRTA process for source/drain areas for a couple ofyears. Spike annealing offers a lower thermal budgetfor the sub-130nm technology node. It can suppresslateral diffusion in source/drain extensions. Sincespike annealing was introduced to 65nm devices, twoRTP systems have been evaluated for spiketemperature profile control. The critical factor inchoosing a process is device performance, such as Covand Vt roll-off. The 65nm production process is basedon experience at the 90nm mode; however, the thermalbudget and uniformity requirements are more rigidwith the shrinking of devices. A lower thermal budgetis required to reduce junction depth in profile tuning.More aggressive spike annealing demonstrated abilityto meet 65nm node demand. Most experiments werecarried out on RTP A, which has a honeycomb lampdesign and achieves a sharper temperature profile.

Sharpness of residence time (the duration of peaktemperature - 50°C) is extremely critical for spikeannealing of source/drain extensions because itdirectly influences electronic characteristics. Therecipes were set up with various residence times. Theywere tuned by changing the cooling rate, sinceramp-up rates above 200°C/sec do not changesharpness much. Different cooling rates were achievedby adjusting helium flow in the recipe. Four residencetimes are adopted to investigate the influence ofjunction depth and sheet resistance. The residencetimes are 1.4 seconds, 1.6 seconds, 1.7 seconds, and2.06 seconds. Nitrogen gas with 1.5slm helium flowachieved 1.4 seconds of residence time. Higherresidence time is tunable by decreasing helium flow.0.5slm helium results in 1.6 seconds residence time,and no helium flow brings about 1.7 seconds and 2.06seconds with a slower cooling rate. The temperatureprofiles are compared and shown in Figure 1 below.

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Figure 1. Sharpness comparison of spike anneals.

Once recipe tuning is completed, temperatureuniformity has to be optimized prior to otherexperiments. The temperature sensitivity was

calculated to tune temperature uniformity on RTP A.The temperature sensitivity can be evaluated by a

"sheet resistance vs. temperature" sensitivity curve.Typical temperature sensitivity is 1.5 -3.5 ohm/sq/°C.For a spike anneal process, it depends on implantconditions.

Results and Discussion

A. Influence ofpeak width on sheet resistance andjunction depth

The lateral diffusion of various spike anneals isillustrated in Figure 2. The experiment was carried outon a BF2 (lKeV, 1.lE1 5, TO) implanted wafer with Gepreamorphization (Ge2KeV, 3E14, TO). The boronconcentration is plotted as a function ofjunction depth.The BF2 implanted wafer was annealed by a 1090°Cspike anneal for four residence times. The higher thethermal budget, the deeper the junction depth.Obviously, longer residence time leads to more lateraldiffusion.

Figure 2. The lateral diffusion of various spikeanneals.

Sheet resistance was also measured for these fourspike anneals. The sheet resistance increased as

residence time decreased, where the shorter residencetime results in lower thermal budget and higher sheetresistance, as shown in Table 1. For every 0.1 secincrease in residence time, Rs decreases 7.2 ohm/sqand junction depth increases 0.8nm. Compared to 2.06seconds residence time, junction depth is reduced byabout 9%, based on the same sheet resistance.Therefore, the reduction in the thermal budget by peakwidth is important for the 65nm node because it leadsto a clear decrease in the dopant diffusion during theanneal.

Table 1. Comparison ofresistance, and junction depth.

residence time, sheet

B. Comparison of two RTP tools by device wafers

The 65nm device qualification was carried out on

RTP A and RTP B. Two RTP tools used the sharpestspike anneal for the device comparison. The residencetime of tool B junction depth was 1.85s, which is

limited by the cooling rate of the wafer; tool Aachieved a residence time of 1.4s because of theaddition of He cooling (Figure 3). Thermal profile of a

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shorter residence time (1.4s) demonstrated -4%reduction in overlap capacitance (Cov) and improvedVt roll-off. Figure 4 and Figure 5 illustrate thecomparison results. The improvement is due to theefficient suppression of lateral diffusion insource/drain extensions. Moreover, RTP Ademonstrates this improvement while retaining thesame 1on/loff performance as delivered in the largerthermal budget RTP B, which is illustrated in Figure 6.Usually, reduction in Cov should worsen Ion/loff. RTPA succeeds to demonstrate comparable achievement indopant activation and also efficient suppression inlateral diffusion. According to 65nm device data,shorter residence time is proven to improveultra-shallow junction performance as characterized byIongoff, Idsat, and Vt parameters.

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Figure 5. RTP A demonstrates improvement in Vtroll-off than RTP B.

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C. Oxygen concentration influence on device

Influence of 02 concentration on a device isillustrated in Figure 7 and Figure 8. The experimentwas carried out by tuning S/D spike anneal recipes(RTP A, with and without lOOppm 02). The deviceresults reveal that 02 concentration has a greatinfluence on P-poly sheet resistance and gate-oxidethickness (Tox-inv., measured in the inversion region).For P-poly sheet resistance, annealing with oxygenachieves 122% reduction in sheet resistance comparedto annealing under pure nitrogen, but only 1.2%change on N-poly, as is shown in Figure 7. It wassuspected that boron out-diffusion results in highersheet resistance. The incorporation of a lowconcentration of oxygen in a spike anneal can suppressboron out-diffusion on P-poly. It showed less influenceon N-poly due to the different implant species.Simulated results show boron implant retained dosehas a distinct increase with the oxygen concentrationand saturates at around 5000ppm oxygen [3,4].Oxygen concentration is conspicuous on device wafers,and results in three times sheet resistance difference onP-poly.

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Gate oxide thickness is influenced by oxygenconcentration when annealing. For PFET, adding1 00ppm oxygen can reduce 0.7A Tox-inv. Thisphenomenon is not obvious on NFET. Both areillustrated in Figure 8. Annealing with a smallconcentration of oxygen can reduce poly depletion andget smaller Tox-inv on PMOS.

Since a small amount of oxygen was added into thenew 65nm spike anneal recipe, we were concernedwhether other device parameters would change. Theultra-shallow junction performance as characterized byIon/lIoff, Idsat, Vt, and Cov were widely investigated.Based on 65nm device parameter inspection, noevident difference is observed on all inspected deviceparameters of both NFET and PFET. Here we bring upIon/loff and Vt roll off as examples. No evidentdifference was shown on the PFET universal curve.The result ofVt roll off showed a similar curve as well.Both are illustrated in Figure 9 and Figure 10.

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Figure 8. Tox-inv. Behavior on (a)P-poly (b)N-poly.

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Summary and Conclusion

To get the shallowest junction depth with anacceptable sheet resistance, it is necessary to decreasepeak width. For 65nm devices, reducing the "peakwidth" of spike annealing will also enhance deviceperformance. RTP A demonstrated a shorter residencetime (1.4s) spike anneal thermal profile, whichreduced Cov by -4% and improved Vt roll-off, whileretaining the same 'on/Ioff performance. 65nm nodedevice results prove that the peak width must bereduced. The sharper peak temperature of the spikeanneal can limit dopant diffiusion and improve deviceperformance of source/drain areas.

References

(1) APPLIED MATERIALS, Radiance 300Process Manual - Rev 003, October, 2003.

(2) APPLIED MATERIALS, 300MM SpikeAnneal BKM, January 15, 2002.

(3) W. Lerch, M. Gluck, N. A. Stolwijk, H. Walk,M. Schafer, S.D. Marcus, J. Electrochem. Soc., 146,1670(1999)

(4) Z. Nenyei, H. Sommer, J. Gelpey, A. Bauer,"Gas flow engineering in rapid thermal processing",Mater. Res. Soc. Symp. Proc., 342, 401-406(1994)

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