status of trigger server electronics
DESCRIPTION
Status of Trigger Server electronics. Trigger boards TB. Server board SB. Topics: Trigger Server Status TSS screening TSM and SB pre-production tests LVDS Jitter tolerance measures. LVDS to Sector Collector. ……. Link board. Server Board. Chamber Minicrate. Control - PowerPoint PPT PresentationTRANSCRIPT
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Status of Trigger Server electronics
Trigger boards TB
Server board SB
Topics: Trigger Server Status TSS screening TSM and SB pre-production tests LVDS Jitter tolerance measures
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Trigger Server – Status updateLVDS to Sector Collector
Controlserial line
Chamber Minicrate
……
Server Board
Linkboard
“backplane”bus
TSS (1200 ASIC, Alcatel 0.5 m):- full production already delivered- currently: screening of 1200 working
devices ready to startTSM (250 TSMS + 500 TSMD pASIC, Actel, 0.35 m):- 1000 device (to be fused) in hands- Final Prototype succesfully tested!- 1 month to fuse all chips
(ext firm already contacted): wait for pre-production tests of the Server Board (End
Apr.)
Server Board :-pre-production delivered in March. 03 (5 SB)-2 SB succesfully tested !-Pre-series production will start soon (beginning of May) -> to provide 35 SB for ’03 minicrate production- tender for full production going on
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSS Screening – HW system
Screening will be performed in Bologna with the test jig
setup for prototypes
Piggy board mounted on a Pattern unit emulating Traco inputand receiving output
TSS Asic Alcatel 0.5 m CMOSProduct by Europractice
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSS Screening – SW system
SW developed in Visual C++, fully automatic
*) interfaces Power supply and clock generator through GPIB protocol *) interfaces mySQL database for bookeeping
Full test: • Bonding check
• Running test(different conf,
Clock frequency andVoltage supply)
• Monitor and control logic check (Jtag and Parallel access)
• Spying and Test features(snap and test reg.s)
• Power consumption continuously monitored
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSS Screening – System performance
Process yield 70%Package yield 90%(conservative estimate)
Delivery consists of2700 chips
To have 1200 TSS workingWe need to test ~ 2000 chip
4 weeks !With a working time of 4 hour/day
Performances of the test system:
Test sorting in differentsetups with 106 patterns
(~16 s @ 60 Kevt/s)
Test monitoring and controllogic
( ~ 5 s)
Bookeeping into the database
Bonding check( < 1 s)
2 min/chip
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
9.5 cm
20.6 cm
TSMside
TSMS
Reminder: TSM is implementedwith 3 pASIC Actel A54SX320.35 m CMOS
PCB16 layers !
Front side
National serializer10-to-1 DS92LV1021
Server Board – Pre-production
TSMDs
NB: Backside contains most ofthe control logic electronics for the minicrate
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Server Board – Test System
Crate VME
Vme board withCPU Pentium II
Rs232PC serial port
Server Board
Pattern Units
232 bits @ 40 MHz
Adapter Board
Trigger Link Rx
LVDS link –data serialized @ 480 MHz
2 copper cables FTP class 6– 40 m
80 bits @ 40 MHz
232 bits @ 40 MHz
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Server Board – Test Setup
Server Board
AdapterBoard
Trigger Link Rx
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Server Board – Software for tests
SW controls all test options: Generates, transmits and receives pattern Checks output with emulation Finds better setup conditions Provides monitoring and configuring
Developed under WinNT with Visual C++
SW to use for full SB production test.
Clock phase (input)
Clock phase (output)
GoodGoodworkingworkingcondition!condition!
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSM design – a reminder…
TSM system is the bottleneck of the trigger electronics on chamber. It is segmented on 3 pASICs with partially redundant functionalities:
Two main working modes:Normal mode (all pASICS work properly) Backup mode (one or two pASICs in failure)
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSM algorithm – another reminder..
Normal mode: implemented by sorting 1 track out of 6 for BX Backup mode: each half chamber sorts 2 tracks independently in two BXs, by means of a “quick” sorting (quality bits are involved)
Main features (enabled in default , can be switched off):Recovery of “good” track eventually found at the previous BX (called carry ) Ghost rejectionRecovery of “good” tracks in overlapped events (i.e.pile-up betweentracks from events in consecutive BXs)
Remember: TRACO sends 2 tracks belonging to the same trigger eventsin 2 consecutive BXs
TS task : to sort two best tracks in two consecutive BXs
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
TSM and SB – Test Status
Server Board Tests Summary (2 boards fully tested):Board layout was checked and approved for production. Signals transmission from Pattern Units has been successfully checked! (N.B: it has the same characteristics of transmission from Trigger Boards)TSM monitoring and configuring works fine!TSM output tests with LVDS transmission through 40 m cables has been performed.
TSM Algorithm Tests Summary: First test: About 1000 “surgical” input patterns have been initially used. These “surgical” patterns, developed during the chip design and simulation, thoroughly check all functionalities, in different configurations also.Second test: About 109 random input patterns have been submitted with different configurations in long tests periods (3-4 days) to find bugs and check stability and performances
Results:-TSM and SB work as expected up to 44 MHz of clock frequency and transmitting output through cables long up to 40 m.
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
LVDS Trigger Link
TSM
TSM
MB 1
MB 2
MB 3
MB 4
Balcony
Sector Collector VME Crate
Sector Collector Board
“Ethernet” cables
( up to ~40m )CLASS 6 FTP
Z = 100
Opto-Link DTTF( in USC55 )
TSM
TSM
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Workshop on LHC Physics with High Pt Muon in CMS R.Travaglini – INFN Bologna Bologna , 10/04/2003
Jitter Measurements
Jitter Tolerance measured in Bologna• Stand-alone LVDS transmission
system equipped as the final trigger link system
• Clock Jitter generatorMaximum Jitter tolerated from NationalSerializer LVDS in worst conditions with Cable of 40 m lengths
=> RMS = 80 ps
Jitter Tolerance measured in Legnaro• TTCex driven by TTCvi• TTCoc inserted (Optical input power = -20dBm)• TTCrx in MC sends clock on LVDS ser.• No Broadcast command•Measured : RMS = 26 ps