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Spin-On-Dielectrics: Characteristics and Modeling
John A. Smythe
A thesis submitted in partial fulfillment of the
requirements for the degree of
Master of Science in Materials Science and Engineering
University of Washington
2004
Program Authorized to Offer Degree:
Materials Science and Engineering
University of Washington
Graduate School
This is to certify that I have examined this copy of a master’s thesis by
John A. Smythe
and have found that it is complete and satisfactory in all respects, and that any and all revisions required by the final
examining committee have been made. Committee Members: _____________________________________________________ Scott Dunham _____________________________________________________ Guozhong Cao _____________________________________________________ Fumio Ohuchi Date:__________________________________
In presenting this thesis in partial fulfillment of the requirements for a master’s degree at the University of Washington, I agree that the Library shall make its copies freely available for inspection. I further agree that extensive copying of this thesis is allowable only for scholarly purposes, consistent with “fair use” as prescribed in the U.S. Copyright Law. Any other reproduction for any purposes or by any means shall not be allowed without my written permission.
Signature ________________________ Date ____________________________
i
TABLE OF CONTENTS
Page List of Figures ..................................................................................................................... ii List of Tables...................................................................................................................... iv 1 A Brief History of Spin-On-Dielectric Materials........................................................ 1
1.1 Background and Introduction.............................................................................. 1 1.2 A Historical Discussion....................................................................................... 2 1.3 Highlights of Existing Spin-Coating Models .................................................... 27 1.4 Initial Work Plan Concepts ............................................................................... 30 1.5 Section 1 Notes.................................................................................................. 31
2 Planarity and Density Model Approach .................................................................... 35
2.1 Introduction ....................................................................................................... 35 2.2 Discussion of Available Modeling Approaches for Planarity........................... 36 2.3 Modeling Spin-Coating Planarization............................................................... 40 2.4 Proposed Work for Global Planarity................................................................. 45 2.5 Proposed Work for Small Feature Effect .......................................................... 49 2.6 Materials and Structures.................................................................................... 53 2.7 Analytical Methods ........................................................................................... 54 2.8 Next Steps ......................................................................................................... 54 2.9 Section 2 Notes.................................................................................................. 55
3 Experimental Plan and Results.................................................................................. 58
3.1 Introduction ....................................................................................................... 58 3.2 Experimental ..................................................................................................... 58 3.3 Test Pattern Layout ........................................................................................... 59 3.4 Experimental Results......................................................................................... 62
3.4.1 Optical Results .......................................................................................... 62 3.4.2 Surface Profile Results .............................................................................. 70
4 Conclusions and Model Development ...................................................................... 84
4.1 Conclusions ....................................................................................................... 84 4.2 Model Development Plan.................................................................................. 84 4.3 Section 4 Notes.................................................................................................. 86
Bibliography......................................................................................................................87
ii
List of Figures Page Figure 1-1: General Schematic of Planarity 4 Figure 1-2: SOG on CVD Oxide Schematic 6 Figure 1-3: MSQ Cross-Linking Reaction24 21 Figure 2-3: Global Planarity for Large Features 46 Figure 2-4: Global Planarity for Large Features - Zoomed View 46 Figure 2-5: Optical Image of Large Feature Sample 47 Figure 2-6: Calculated Omega2 for expected condition 48 Figure 2-7: Calculated Omega2 in sub-micron range 48 Figure 2-8: Small Feature Image without Etch 50 Figure 2-9: Small Feature Image with Etch 50 Figure 2-10: Small Feature Effect 51 Figure 2-11: Wide Feature Density 51 Figure 2-12: Thickness Effect of Densification Reaction 52 Figure 2-13: Thickness Effect of Densification Reaction 53 Figure 3-1: Test Pattern Schematic - Quadrant Position 60 Figure 3-2: Test Pattern Schematic - Quadrant Spacing Dimensions 60 Figure 3-3: Test Pattern Schematic - Quadrant Detail 61 Figure 3-4: Test Pattern Schematic - Minimum Feature Detail 61 Figure 3-5: Optical microscope example of measurement points 62 Figure 3-6: Optical measurements 7114_08 quadrant I to quadrant II (same pattern) 63 Figure 3-7: Optical measurements for 7114_08 quadrant II to quadrant I (next pattern) 64 Figure 3-8: Measurement sites for GOF measurements 64 Figure 3-9: Step planarity by optical measurement 65 Figure 3-10: Large spot GOF by position 65 Figure 3-11: Optical measurements for 7114_09 quadrant II to quadrant I (next pattern)66 Figure 3-12: Optical measurements for 7114 08 vs. 09 quadrant II to quadrant I (next
pattern) 66 Figure 3-13: Percent Fill 7114 08 vs. 09 67 Figure 3-14: Percent of Test Wafer for 7114 08 and 09 68 Figure 3-15: Fill Efficiency for 20 µm gap 7500 Å and 11000 Å nominal 68 Figure 3-16: 7114 08 within quadrant uniformity 69 Figure 3-17: 7114 08 global uniformity right side of quadrant 70 Figure 3-18: 7114_03 scan 1 complete 71 Figure 3-19: 7114 03 scan 1 segment 300 to 600 71 Figure 3-20: 7114_03 Scan 1 segment 350 to 600 72 Figure 3-21: 7114_03 Scan 2 complete 72 Figure 3-22: 7114_03 Scan 2 segment 700 to 950 73 Figure 3-23: 7114_03 Scan 3 complete 73 Figure 3-24: 7114_03 Scan 3 segment 700 to 950 74 Figure 3-25: 7114 08 scan 1 complete 75 Figure 3-26: 7114_08 Scan 2 Complete 75
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Figure 3-27: 7114_08 Scan 2 segment 750 to 1000 76 Figure 3-28: 7114_08 Scan 3 Complete 76 Figure 3-29: 7114_08 Scan 3 segment 750 to 1000 77 Figure 3-30: 7114 03 scan 3 segment 886 to 926 linear fit 78 Figure 3-31: 7114_08 AFM Analysis Locations 79 Figure 3-32: 7114_08 AFM scan line vertical step at edge of feature 80 Figure 3-33: 7114_08 AFM scan line vertical results at center of feature 81 Figure 3-34: 7114_08 AFM scan of 21 micron gap 83 Figure 3-35: 7114_08 P-20h scan for AFM comparison 83
iv
List of Tables
Page Table 1-1: SOG Plasma Etch Rates..................................................................................... 5 Table 1-2: SOG Plasma and 20:1 HF Etch Rates................................................................ 5 Table 1-3: FTIR Peaks8 ..................................................................................................... 10 Table 1-4: Percent Planarity Ranges by Yen and Rao11.................................................... 12 Table 1-5: Poly-Siloxane Thickness and Index12.............................................................. 12 Table 1-6: Table III17 For Viscosity from 2.44 to 5.33 mPa-s .......................................... 15 Table 1-7: Table IV17 for viscosity of solvents from 0.59 to 3.18 mPa-s ......................... 15 Table 1-8: FTIR Peaks22.................................................................................................... 19 Table 1-9: FTIR Peaks for MSQ Studies24........................................................................ 22 Table 2-1: Table III7 For Viscosity from 2.44 to 5.33 mPa-s ........................................... 38 Table 2-2: Table IV7 for viscosity of solvents from 0.59 to 3.18 mPa-s .......................... 38 Table 2-4: Typical Values for Planarity Variables............................................................ 43 Table 3-1: Sample Treatment............................................................................................ 59 Table 3-2: 7114 03 fit equation summary ......................................................................... 74 Table 3-3: 7114 08 fit equation summary ......................................................................... 77 Table 3-4: 7114_08 Planarity as function of feature position........................................... 82
v
Acknowledgements
I would like to acknowledge Joe Wiggins of Micron Technology, Inc. for the AFM sample work and Leigh Soutter for continued assistance in the understanding of FEMLAB software package in preparation for model development. Finally, none of the work would be possible without the continued support of Micron Technology, Inc.
Disclaimer The views expressed in this work are strictly those of the author and do not represent those of Micron Technology, Inc.
vi
Dedication
To RaDawn. This work could not have been completed without your continuous support.
Thank-you for believing.
1
1 A Brief History of Spin-On-Dielectric Materials
1.1 Background and Introduction The idea of replacing chemical vapor deposition (CVD), plasma enhanced chemical
vapor deposition (PECVD), and sputter oxide materials, among others, with a spin-on
approach has been of interest in the Semiconductor industry for the last two decades. The
basic technique draws from the planarizing nature of a liquid when applied to surface
topography. The method was initially known as Spin-On-Glass (SOG) and has more
recently taken on the more general acronym of Spin-On-Dielectric (SOD). The focus
over the years has been to make the material as close to oxide (SiO2) as possible after a
cure step or series of cure steps in various ambient gases, temperatures and pressures. The
work includes doped oxides such as phosphor-silicate-glass (PSG) because of important
mobile cation gettering characteristics. The many works have addressed issues including,
but not limited to, crack resistance, etch rate in both wet and dry etch chemistries,
resistance to photo resist stripping conditions, film stress control, and particulate control.
The ideal result, in many present day applications, would be to find a material that would
match the materials character of densified or as-deposited high-density-plasma (HDP)
oxide. There are still applications where matching the materials character of densified
(often called “reflow” or “flow”) boro-phospho-silicate-glass (BPSG) or phosphor-
silicate-glass (PSG) would be beneficial. The one characteristic that has not been
addressed with rigor is the interaction between underlying topography and degree of local
and global planarization. The general concepts are widely known in the industry but little
has been done to provide models that guide the 2D-layout rules of semiconductor circuit
design. Some relevant work has been done outside the industry. The process technology
known as Chemical-Mechanical-Polishing (CMP) has conversely received focus in this
area with many papers and Doctoral Theses, particularly at MIT, on the subject of
modeling such interactions. Now that widely used SOD materials have been sufficiently
refined and new materials developed, it is appropriate to develop models that will guide
2
optimization of layout to facilitate optimum benefit from implementation of SOD
materials in sub 100 nm semiconductor process technologies.
This work will provide a chronology of materials, characterization and integration results
from early 1986 to present day. Though not exhaustive, the work is intended to be
thorough in regards to materials, methods, analysis, and trends throughout the ever
shrinking technology design rule sequence. Where appropriate, reference to work outside
the semiconductor industry will also be discussed. The work then proposes an approach
to modeling the local and global planarization character in the context of underlying
topography and how those results would be used to guide 2D-layout rules and define
limitations in the 3D sense.
1.2 A Historical Discussion Our walk through time begins with papers published in 1986. At that time, use of silicate
based materials and some siloxanes were common for inter-metal dielectric planarization.
The general intent at that time was to provide a smoothing effect from one metallization
pattern to the next. The motivation came from the need to improve the continuity (i.e.
step coverage) of metal conductors and to reduce depth of focus and stringer effects for
photolithography and etch processing respectively. Each SOG material would contain
some level of carrier solvent that had to be cured from the coating. The end result was to
have a film that acted like a CVD oxide after cure was completed. This theme has been a
common thread to this day with various degrees of success.
Nakamura1 and coworkers provide a general formula (Equation 1-1) for what were
known as linear silicates:
Equation 1-1 SinOn-1(OH)2n+1 where n = 1, 2, 3, …
3
They state that when heated, successive bonding of Si-O-Si takes place through
dehydration following Equation 1-2:
Equation 1-2 SinOn-1(OH)2n+2 SinOn(OH)2n + H2O where n = 1, 2, 3, …
The carrier solvent in this work was ethanol. The samples of ethanol silicates were cured
from 200 to 1200ºC for 1 hour in N2. The primary object being to drive off the volatile
organic solvent and then react the silicate to drive off as much water as possible. One
aspect of their work was to measure the film stress. Their results led them to conclude,
“The intrinsic stress must be brought about by bond strains originating from the
dehydration reaction.” They also proposed that the intrinsic stress and density for
samples heat treated above 800ºC are driven by distortion relief of O-Si-O bond angle
from tetrahedron position and elongation of the Si-O-Si bond.
The next work by J.K. Chu et.al.2 provides insight to some of the integration issues
associated with implementation of SOG materials. They report on an inter-metal
application evaluation and selection process. They used the following categories:
material stability, material consistency, film shrinkage, adhesion, vendor support, and
ability to coat in the 1000 to 5000Å range. The basic requirement was to reduce the
topography created by patterning of the first layer of aluminum metallization. Two
fundamental approaches were used: SOG on CVD oxide and CVD oxide on SOG. This
was aggressive for the time; as it was more common to use a sacrificial etch back
approach in this era. However, the cost and simplification made it worth understanding
the limitations and possibilities. Adhesion failures were noted when SOG is in direct
contact with metal or photo resist is in direct contact with SOG. For these reasons, the
sacrificial SOG (i.e. etch back) approach is generally preferred. With regards to
planarization, they report that “the amount of SOG remaining in the device depends on
the underlying metal aspect ratio and the initial CVD dielectric thickness”. It is this point
that continues to motivate the development of robust spin-on planarization models. The
researchers also state that for passivation applications, changes in the wt% phosphorous
4
can be used to match the underlying oxide etch rate to the SOG. The use of SOG
eliminates the so called forbidden gap constraints of CVD oxides. They provide a
relation for percent planarization, %P, as a function of aspect ratio X/Y per Equation 1-3
and Figure 1-1.
Equation 1-3 10090
1% xXZP
−= θ
where: θ = step coverage angle
X = step height Y = step space Z = dip from top of oxide to lowest SOG point
Figure 1-1: General Schematic of Planarity
The workers did provide an initial figure of merit but did not provide parameters for
material viscosity, bare wafer thickness and other factors related to how a liquid coats a
surface with topography.
Vines and Gupta3, in a joint work, report on inter-metal dielectric planarization using
Allied Chemical Accuglass 204 and 105/305 materials. They evaluated etch back and
non-etch back approaches. The methods are distinguished by SOG being between metal
lines only versus remaining above metal lines such that the inter-metal via connection
must be made through a combination of SOG material and CVD oxide. Both materials
θ
X
Y
Z
5
are siloxane polymers dissolved in alcohol/ketone based solvent systems. A 3 ml
dispense volume was used for 100 mm wafers. The casting RPM was 3000 rpm. Casting
refers to the portion of the spin sequence that sets the thickness on wafer without
topography. A Blue M vacuum (3 to 5 Torr) oven was used to bake out the solvent. A
low temperature oxide (LTO) tube was used for cures up to 350ºC. The PECVD oxide
was deposited at 290ºC in an AME3300 system. A Lam Research Auto Etch 590 system
using C2F6/He was used to obtain dry etch rate for Accuglass 204 as a function of cure
temperature. These were common semiconductor tools at the time of this work. A
selection of etch rates reported by Vines and Gupta are shown in Table 1-1 to give a
general sense of rate compared to thermal oxides and CVD oxides.
Table 1-1: SOG Plasma Etch Rates
Cure Temp ºC Etch Rate Å/sec (Vacuum Cure)
Etch Rate Å/sec (Air Cure)
100 115 ± 7 120 ± 13 175 99 ± 3 107 ± 8 250 95 4 98 8
Etch: C2F6/He = 185/45, 600 mT, 850 Watts Reference: PECVD oxide = 100 Å/sec
The Accuglass 105/305 material was evaluated as a non-sacrificial dielectric using
plasma etch and 20:1 dilute HF. All samples were baked at 175ºC for 60 minutes in
vacuum prior to the cures noted in Table 1-2 below.
Table 1-2: SOG Plasma and 20:1 HF Etch Rates
Etch Rates Å/sec Oxygen Ambient Steam Ambient Cure Temp
ºC Plasma 20:1 HF Plasma 20:1 HF 300 165 95 159 87 350 187 86 181 81 425 185 78 180 70
The researchers report that the Accuglass 105 forms a thinner layer on top of metal lines
than the 305. The distinction between 105 and 305 is that 105 has a lower viscosity and
is blended to achieve a lower thickness on a bare wafer for a given set of spin conditions.
6
Though the technology had 1.2 um spaces between metal lines, the actual space for SOG
fill was reduced by the initial PECVD oxide deposition. This is illustrated in Figure 1-2
by comparison of the space between metal lines, Y and the space between the edges of
the conformal CVD oxide Y1.
Figure 1-2: SOG on CVD Oxide Schematic
Another Inter-Metal Dielectric (IMD) approach by Rey and coworkers4 is discussed that
integrates a non-etch back approach. They used the following sequence: PECVD SiO2;
SOG (2.5% P2O5); static dispense; in situ hard bake (400ºC); PECVD oxide capping
layer. A dual slope via etch was used. This resist erosion approach was common in the
mid to late 1980’s to help improve sidewall step coverage of physical vapor deposition
(i.e. sputtered) aluminum in the via. Though the researchers did not suggest a model,
they report that planarization for a given bare (blanket) thickness target is a direct
function of the aspect ratio of the steps to be coated. Since the thickness in the gaps is
generally thicker than a bare coated wafer, to avoid cracking problems, the researchers
chose low film thickness. For this period, it was likely that low meant something on the
order of 3000 to 5000 Å. The technology for this application was 1.5 um HCMOS3.
Another example of an implementation of silicates is work by Elkins at al.5 in which they
examined use of Allied Chemical type 204 SOG on PECVD PSG. The cure was 45
X
Y
Y1
CVD Oxide
SOG
7
minutes at 400ºC in nitrogen or air. They report a 10 percent film thickness reduction
after cure. The approach was a sacrificial etch back using a 2:1 He:C2H6 chemistry with
O2 added for uniformity control. This introduces one of the most significant
complications of the sacrificial etch back approach. The challenge was to maintain
matched etch rate when both SOG and CVD oxide was being etched. The details of such
control is beyond the scope of this historical review but it is a key driving force towards
materials and treatments that result in a SOG material that can be directly patterned. Etch
rate selectivity (PSG:SOG) could be controlled to some degree using w% phosphorus in
the nominal 4 wt% PSG. They report that the difference in coefficient of thermal
expansion between SOG and PSG will cause the PSG to peel away if the top PSG does
not directly contact the bottom PSG. This peeling effect with SOG and PSG will be
explained from another perspective about five years later by other researchers. Elkins and
coworkers also attempted O2 plasma as a cure method without success. The rapid
conversion resulted in 40 percent film thickness shrinkage and adhesion problems. The
application was on a 2 um CMOS technology.
Pei-Lin Pai and coworkers6 reported their findings as a result of detailed characterization
of materials properties of polysiloxane. At the time of this work, they make reference to
silicate and polysiloxane being the two most widely used spin-on glass materials. The
crack threshold of silicates is about 4000 while polysiloxane can be deposited about 5000
without cracking. Polysiloxane when cured below 600ºC still contains methyl, ethyl or
phenyl groups and polymer-bound hydroxyl groups. Quantitative amounts depend on the
exact SOG blend and cure conditions used. The implication of their finding is that the
film cannot be fully converted to oxide if used as an inter-metal dielectric with aluminum
metallization that was common at the time and still was in 2003. Cure above 900ºC
results in oxidation of organic groups leaving a silicon dioxide like film. The 900ºC
condition would be appropriate for most technologies that did not include a silicide below
the SOG layer. The workers evaluated what they named SOG-A (methyl, phenyl, ethoxy,
groups with 20-30 wt% carbon, with propanol as solvent) and SOG-B (methyl, alkoxy
groups bonded to silicon, with butanol as solvent). Their results support that higher
8
boiling point solvent and a so called “leveling agent” yield better coating uniformity for
SOG-B. They used Blue M convection bake at 100ºC for 30 minutes followed by 200ºC
for 30 minutes to drive off the casting solvent. The final cure step was completed in a
furnace tube at temperatures from 400 to 950ºC. Metrology included optical thickness,
RI, FTIR (Fourier Transform Infrared Spectroscopy) spectra, stress (room and hot).
Some FTIR signal peaks of interest were: 940cm-1 from stretching of silicon-bound
hydroxyl (silanol, Si-OH); 1270cm-1 from Si-CH3 stretching. FTIR spectra were taken
for samples cured at 450, 600 and 900ºC in N2 and O2 gas ambient. In discussion of
dielectric constant results, the researchers state that polar OH groups respond to ac
signals thus increasing the dielectric constant. Their FTIR results support that for a given
temperature, O2 is more effective that N2 in converting polysiloxane to SiO2. They point
out that stress (tensile) can be attributed to film shrinkage. The equation for stress based
on induced wafer curvature is given by Equation 1-4 (Stoney’s equation).
Equation 1-4 ( ) f
s
s
st tR
tE 2
16 νσ
−=
where: σt (+) = tensile (concave on coated side) σt (-) = compressive (convex on coated side) tf = film thickness R = radius of curvature vs = Poisson’s ratio of Si (0.064) ts = wafer thickness Es = Young’s modulus of Si [1.689E11 N/m2 for (100)] Stress was collected as a function of heating to 600ºC and cooling back to room
temperature. The methyl polysiloxane becomes more tensile during heating and then
does not return to a lower level upon cooling. The film maintains the high tensile stress.
For their work, the dielectric constant was determined from Equation 1-5:
Equation 1-5 AtC
or ε
ε =
9
where: A = area of capacitor plate C = measured capacitance t = dielectric thickness from optical measurement εo = permittivity of vacuum (8.854E-12 F/m) Their results show that 1 minute of O2 in rapid thermal process system gives similar
results as 30 minutes in a tube in O2 ambient. This finding supports that the cure process
is not diffusion limited.
The work of Naguib et. al7 examined the implementation of SOG in a 1.2 um design rule
double metal process. They evaluated two silicate-type materials: Emulsitone silica film
209 and 210; Allied Chemical (now Honeywell Electronic Materials) 203. They also
evaluated two versions of Allied Chemical’s siloxane material (204 and 208). After cure,
their results show that from 1 to 15 % of Si-C bonds remain. The silicate materials were
found to have more than three times the stress of the siloxane films. The researchers
propose a metric of planarity as a function of the line-space pitch. The general idea is
that a small gap (relative to the coat thickness) can be near 100 percent planar while
larger features are only smoothed. At the time, the idea of global planarity was not
seriously considered.
Ting and Lin8 in a joint work with Pai and Oldham8 evaluated siloxane materials to
planarize 1 um thick aluminum patterns using a non-etch back approach. They report
that the siloxane films still contained organic groups after 450ºC cure but an anneal at
900ºC in oxidizing ambient results in an essentially silicon dioxide film. The material
and coat method gave about 4000 Å in the open areas between metal lines. The material
was baked at 200ºC followed by a tube cure in nitrogen for 30 minutes at 450ºC. Their
findings indicate that the tensile stress from volume shrinkage is the driving force for film
cracking. This is consistent with other researchers at the time and since. They also
reported stress as a function of temperature. One reported purpose of higher temperature
anneal conditions is to provide the activation energy required to rearrange bond angles
and hence relieve stress. They report the following FTIR peaks of interest (Table 1-3).
10
Table 1-3: FTIR Peaks8
Peak Bond Comments 1060 - 1080 cm-1 Si-O exact position of peak
depends on anneal temperature and ambient
1270 cm-1 methyl groups 3200 - 3800 cm-1 OH bonds includes absorbed water 940 cm-1 Si-OH exclusive to this bond type Based on FTIR observations, the researchers conclude that OH concentration is lower
when films are annealed in N2 compared to O2 and is highest for 600ºC O2. Cure at
920ºC in N2 or O2 will reduce OH to very low levels. The methyl groups are removed at
920ºC with O2 being more effective than N2. Values of k were measured at 10 kHz and 1
MHz. With the exception of the 600ºC oxygen anneal, the anneal conditions tested gave
low values of k. The film BV values were based on a 1uA/um2 leakage limit under
ramped voltage. They also report use of siloxane SOG for polysilicon planarization.
Cure was 450ºC and 800ºC in nitrogen. The researchers reported blistering of overlaid
BPSG (920ºC flow) if the SOG was not cured at 800ºC. SOG coatings of 2000 and 4000
Å were applied directly on 1.0 um thick aluminum pattern. They report that a 450ºC
nitrogen out-gas cycle was required after via etch and prior to second metal aluminum
deposition to avoid the via-poisoning effect.
The physical and chemical properties of silicate SOG materials were evaluated by Chen
and coworkers9. Their work was in the context of inter-metal dielectric (IMD) using the
CVD/SOG/CVD approach to smooth 6500Å metal lines. The first CVD layer is 2000Å
and the capping CVD 6000Å. The materials were silicates from Allied Chemical and
TOK (Tokyo Okha). Bake and cure sequence was as follows: 250ºC for 30 minutes in N2
followed by 450ºC for 60 minutes in N2. The FTIR work found the expected Si-O bond
peak at 1080 cm-1 becomes higher and narrower as cure proceeds. The C-H groups at
2988 cm-1 were found to be minimized or eliminated as a result of cure in nitrogen. Their
finding is consistent with the previously reported reaction equation (Equation 1-2)
showing that oxygen is not required for conversion to SiO2 matrix. They report k values
11
from 3.7 to 4.2 depending on the degree of cure. Their work included temperature
cycling from 150ºC to -65ºC with 10 minutes at each temperature where a cycle is on
hot/cold sequence. This is a typical range to assess resistance to TCE related physical
failures such as delamination and cracking.
Morimoto and Grant10 reviewed results for a process that involved sacrificial etch back,
400ºC N2 cure before capping oxide deposition, and capping oxide deposition. They
define planarity as the slope of the oxide surface between feature lines. They state that
the spin characteristics are also affected by the organic content. Higher organic content
gives better planarity for the same thickness. One specific example is that higher organic
content materials form a local mounding of thick SOG on wide metal features. They
report that 12 wt% is the optimum carbon content. The changes in the material during
heating and cure are described as solvent evaporation followed by evolution of water
from polymerization of silanol (Si-OH) groups.
Planarization performance of a Tokyo Okha material was measured in work by Yen and
Rao11 on a 1.2 um design rule double metal technology. The implementation used 3000
Å of PECVD oxide, 1500Å of SOG and 3000Å of capping PECVD oxide. The results of
their work caused them to conclude that, “coating behavior of the SOD depends not only
on its viscosity but also on its composition.” They demonstrated use of a multi-step
coating process to eliminate crack formation in valleys where the SOG reaches the
greatest thickness. The Toyko Okha type 2 SOG thickness decreases approximately 10
percent after bake and another 10 percent after cure. From FTIR spectra collected, the
Si-O absorption peak at 1080 cm-1 in cured SOG. The cure used 250ºC for 20 minutes to
stabilize the material. The time was selected to allow sufficient time for out gassing and
then ramp to 425ºC holding for 35 minutes to complete the cure. They define the degree
of planarization as follows in Equation 1-6:
Equation 1-6 1001% xcoatbeforeStep
coatafterStepPlanarity
−=
12
The %Planarity was found to have different ranges depending on step for the same
spacing as shown in Table 1-4. The numeric order reflects the expected relation that for a
given step height and coating thickness, the percent planarity will increase as the spacing
decreases. This is one example of how useful a comprehensive model would be for
definition of materials requirements and layout rules.
Table 1-4: Percent Planarity Ranges by Yen and Rao11
Step (um) Spacing Range (um) % Planarity 0.5 8 to 1 70 to 90 1.1 8 to 1 50 to 70
One of the less common materials in use was poly-siloxane. Riley and Shelley12
evaluated poly-siloxane for multi-level metallization application. Initial cure was under
vacuum at 190ºC for 45 seconds. The subsequent tube cure was 250ºC for 30 minutes in
nitrogen. Further cure was in RTP (Rapid Thermal Process) system at 450ºC for 2 to 4
minutes. The most aggressive cure was in O2 plasma in a barrel type reactor at 1 Torr,
300W, 13.56 MHz for times from 2 to 30 minutes. Some example thickness and
refractive index values reported by Riley and Shelley are shown in Table 1-5.
Table 1-5: Poly-Siloxane Thickness and Index12
Bake and Cure Thickness Å
Refractive Index (633 nm)
Hot plate 190ºC 45 sec 1422 1.414 Hot plate 190ºC 45 sec
Oven 450ºC N2 30 minutes 1432 1.337
Hot plate 190ºC 45 sec Oven 450ºC N2 30 minutes
O2 Plasma 30 minutes 864 1.429
Hot plate 190ºC 45 sec O2 Plasma 30 minutes 886 1.438
The FTIR results were used to make comparisons to CVD SiO2 in the 280 to 1810 cm-1
range. They proposed that O2 is incorporated during O2 plasma treatment as indicated by
13
narrower and higher peak at ~1060cm-1 from increased presence of Si-O-Si bonding,
noting that RI changes may be a result of polymer cross-linking of methyl groups.
Another reference to the via poisoning issue in SOG implementation was made by Ting
et al.13 in their work on a non-etch back implementation. Though they did not reveal the
SOG material used, they did report that it was critical to use a high temperature cure after
opening the via to reduce poisoning. This is generally regarded as a method to complete
additional out gassing of the exposed SOG.
Ito and coworkers14 studied a poly-methyl-siloxane based SOG material. The initial dry
after coating to the desired thickness was completed in an air circulation oven at 100ºC
for 30 minutes. Subsequent bake was 200ºC (or higher) for 30 minutes in either air or
nitrogen. Consistent with silicate and siloxane materials, oxygen is not needed in the
cure process. They demonstrated curing approach named Reactive Glass Stabilization
(RGS). The RGS process was conducted at 50 mT in O2, at 200W and 13.56 MHz, for
80 minutes in a parallel-electrode reactor. The concept was to form a gas-tight SiO2 -like
layer that would resist attack by O2 plasma ashing (7 Torr, 300W, O2, 10 minutes, barrel-
type asher). For the specific integration approach, this skin layer was found to be
effective in resisting attack by ashing.
Researchers15 at Allied-Signal (a SOG material supplier) reported on their study of
methyl-siloxane and phosphosilicates (2 and 4 mole % P2O5) for ULSI dielectric
planarization schemes. Viscosity of the materials evaluated was reported to be in the
range of 1-2 cP with solid content of 4-6 percent. After coating, a track bake of 150ºC
for 60 seconds was followed by a tube cure at 425ºC for 60 minutes in air (N2/O2). The
Si-CH3 absorption peak (from the methyl groups) in the FTIR spectra at 1270cm-1 was
still present after 60 minutes at 450ºC in air. After O2 plasma exposure, they proposed
that the methyl groups oxidized causing water and silanol absorption peaks to appear in
the FTIR spectra. They used 50:1 BOE to characterize wet etch rate. For cured films, the
14
etch rate in BOE was 3000 Å/min best case for undoped and 720 Å/min for doped
compared to 140Å/min for thermal oxide reference material.
The use of phosphorous (P2O5) was common (and still is to a large extent) to trap mobile
contaminants such as sodium. Hence, the availability of such materials previously
discussed. In some implementations, the underlying oxide is PSG but the SOG is still
undoped. This condition was reported on by Sinha and the author16. The SOG was
Allied Signal Accuglass 310 and 110. This was applied to a PSG (3-5 wt%) pre-metal
dielectric layer used for planarization of poly-silicon interconnect. We found that
delamination from the PSG surface was difficult to control. The results of our work
indicated that the separation was a result of phosphoric acid formation as moisture was
absorbed by the PSG surface. A pre-bake just before application of the SOG was found
to be a critical step towards control of adhesion. Compositional analysis of the acid
levels used as a catalyst for gelation in the SOG was used to define a maximum value
above which delamination would occur more frequently. This work is an example where
planarization models were secondary to simply keeping the films from delaminating or
cracking.
One of the bench mark materials studies was by Nakano and Ohta17. They studied
inorganic (silicate; silanol Si-OH) and organic (siloxane) SOD materials. Their
evaluation was conducted using 5000 angstrom film thickness; hotplate bakes of 80ºC,
150ºC, and 230ºC (1 min each); final cure at 400ºC for 30 minutes in N2. Gap fill was
successful down to 0.09 um for some of the SOG materials evaluated (Table 1-6). Radial
striations were reported to be a result of the carrier solvent used. Materials with
molecular weights from 1200 to 14000 were evaluated. They propose that the solvent
(Table 1-7) is the dominant factor for film quality and coating characteristics. Their
analysis included very detailed NMR analysis of bond structure including conclusions
about nearest neighbor atoms to silicon.
15
Table 1-6: Table III17 For Viscosity from 2.44 to 5.33 mPa-s
SOG Main Solvent Sub Solvent Viscosity at
25ºC (mPa S)
Striation
A Methanol 1-Propoxy-2-propanol 4.61 + B Methanol 1-Propoxy-2-propanol, water 5.22 + C Ethanol Butyl acetate, Butanol 2.18 - D Methanol 1-Propoxy-2-propanol, water 4.79 ++
E Methanol 2-Propanol 2-Methylpropyl acetate 2.44 -
F Ethanol 2-Propanol, Acetone Butanol 2.54 -
G Ethanol 2-Propanol, Acetone 3.15 + or -
Table 1-7: Table IV17 for viscosity of solvents from 0.59 to 3.18 mPa-s
Solvent Viscosity at 20ºC (mPa - s)
Methanol 0.59 Ethanol 1.22 2-Propanol 2.41 Butanol 2.95 Acetone 0.80 Butyl acetate 0.88 2-Methylpropyl acetate 0.88 1-Propoxy-2-propanol 3.18(1) (1) measured at 25ºC
Note: For reference, 10 Poise = 1 Pa – sec, or 1 cP = 1 mPa-sec, where the units of mPa-sec
are often used in other works. After extensive study, the researchers provide the following broad conclusion: “There appears to be no obvious relation between gap filling
properties and the chemical compositions. Gap filling phenomena relate not only to a complex behavior of the surface tension and viscosity change of the solution as a function of its concentration and the spinning speed, but also interfacial tension between the solution and the under layer film.”
The work of Nakano and Ohta was reported in 1995 and covered a great amount of
analysis detail. In spite of the excellent work, relations that would support a useful model
were not forth coming. Most of those practiced in the art of SOG application had general
16
rules of thumb after sufficient experience but most simple models broke down as soon as
pattern thickness or feature size (line or space) changed.
New technology will often add another variable. One example is of such a technology is
electron beam flood exposure. In a joint work18 by researchers from Allied Signal,
Hyundai and Electron Vision, significant improvements in cure characteristics were
demonstrated. The prior rule of thumb was that cure became less efficient as the aspect
ratio of the gap increased. The researchers used a flood-type e-beam exposure treatment
to fully cure siloxane SOG materials. They found that most organic content is gone after
a dose of 3000uC/cm2. They reported no change in the e-beam cured films after exposure
to O2 plasma. The cured material was evaluated as part of a non-etch back approach.
The flood exposure was conducted in reduced pressure with Ar or N2 ambient using dose
from 3000 to10000 uC/cm2. The process technology node was 0.5 um. They did not find
any evidence of via poisoning that is often a problem with non-etch back approaches.
The general trade magazines of the semiconductor industry will periodically offer
summary articles covering a specific discipline. Singer19 in one such review article
provided a broad scope perspective of the available materials and applications circa 1997.
Until the late 80’s, inorganic silicate or silanol materials were largely used. A track (i.e.
hot plate) cure was generally followed by a furnace cure to get a silica-like glass film.
Two or three coats were commonly used to achieve thicker total films. As the geometries
went below 1 um design rules, material shifted to organic siloxane. Singer made specific
reference to a definition provided by T. Nakano17: “Siloxane SOG materials are solutions
of a partially hydrolyzed mixture of tetra-functional alkyl-siloxane oligomer synthesized
from tetra-alkoxysilane and mono-alkoxysilane and/or dialkyldialkoxysilane.” At the
time, high density plasma (HDP) CVD oxides and TEOS/ozone oxides were able to
demonstrate gap filling capability to a certain extent. Damascene (additive interconnect
approach) applications do not require gap filling capability as the dielectrics are always
coated (or deposited) on to a globally flat surface. He points out that application to
17
memory products tend to be the common driver for SOD because the regular and densely
packed arrays lend themselves to the character of SOD planarization. Though Singer did
not elaborate, he was making the point that small spaces are more easily planarized than a
mixture of narrow and broad spaces. He mentions that CMP has been combined with
SOG and in many cases, SOG is partially etched back to avoid a phenomena commonly
know as “via poisoning”. This is true today as evidenced by the research reports from
Dow Corning and Samsung Electronics that will be reviewed later in this discussion.
Singer goes on to highlight that organic SOG materials can be damaged by oxygen
plasma (used for photo resist stripping) or by too much time above 500ºC. Some “hot”
aluminum sputter deposition processes use temperatures as high as 525ºC. Such
conditions tend to generate a hygroscopic surface that will absorb moisture. He makes
reference to a proposal by Neil Hendricks of Allied Signal (provider of the Accuglass
series) that strained Si-O-Si bonds at the surface result in SiOH groups forming when the
surface is exposed to atmosphere after the oxygen plasma exposure. Another critical
point made is the importance of maintaining compressive stress on metal lines (primarily
Al, AlCu and AlCuSi alloys) to reduce hillock and lateral extrusion formation. Though
Singer provided a comprehensive overview, no mention was made to models that assisted
material property definition or application to planarization of variable aspect ratio pattern.
Because of the exceptional results that can be obtained using e-beam exposure, additional
work was soon reported by researchers20 at Allied Signal (now Honeywell Electronic
Materials). They reported on their work with siloxane (Accuglass 311) material that was
e-beam cured. Depth profile results were presented as a function of e-beam exposure
dose and energy. The method (flood-type electron beam) successfully mitigates the
widely reported “via poisoning” effect by removing residual organic groups and lowering
moisture content. The work was directed at finding optimum conditions of dose and
energy with respect to a non-etch back process. The non-etch back approach being
preferred because it eliminates the difficulties of SOG etch. The researchers used 3 coats
to reach total thickness of 9750 Å. The thickness values were reduced to a 6800 to 8500
18
Å range after e-beam treatment. FTIR was used to obtain an indication of composition
and 50:1 BOE was used for wet etch rate (WER) determination. Repeated
dip/measurement cycles were used to obtain a profile of etch rate. They report that 5 kV
energy provided uniform cure down to about 2000 Å while 3 kV films were uniform to
about 1200 Å. Their results support the expectation that electrons follow the same depth
profile predictability as charged species used in ion implantation. The WER increased
rapidly below the cure depth. Energy of 10 kV (and the highest evaluated) was sufficient
to uniformly cure a nominal 6000 Å film. Dose in the range of 3 mC/cm2 to 10mC/cm2
had little effect on WER with values being within 1 to 1.5 Å/sec without regard to
energy. Their results suggest that film thickness to be cured dictates the required energy
while dose can be used to fine tune WER.
In their FTIR work, the peaks of interest were: Si-C at 1289 cm-1 and C-H bond
stretching at 2976 cm-1. They report that the pyrogenic decomposition of CH3 occurs at
temperatures greater than 500ºC. E-beam energy of 10 kV was sufficient to remove C-H
and Si-C bond peaks from the FTIR signal. Moisture content was reported to be
diffusion limited based on correlation of results to increased dose when the beam current
was kept constant. Thermal Desorption Spectroscopy (TDS) was used to quantify the
moisture effects. The researchers point out that the energy based depth control could be
used to uniquely tailor the film properties. They also associated oxidation by oxygen
plasma as a catalyst for subsequent moisture absorption. This is consistent with prior
references that the surface becomes hygroscopic.
Loboda and Toskey21 reported on their characterization of hydrogen silsesquioxane
(HSQ) resin with a k value of 3.0. This was considered low-k in comparison to CVD
oxide having k of near 3.9. The material is marketed as Dow Corning’s FOx flowable
oxide product. Siloxane SOG materials contain Si-C and C-C bonds while the HSQ
resins do not. The only draw back is that alcohols and water can promote gelation of
HSQ materials in drain lines and other portions of the apparatus used to apply and handle
19
HSQ. The reported FTIR results show the H-Si-O molecular bonding network: Si-H bond
stretch at 2250 cm-1; Si-O-Si bond stretch at 1060-1150cm-1; H-Si-O hybrid vibration at
830-870cm-1. Compositional analysis of HSQ after 1 hour nitrogen cure at 450ºC gives:
18 atm% H, 30 atm% Si, 52 atm% oxygen. Film stress of the cured film is 50-80 MPa
(tensile). Dielectric constant and field breakdown voltage are 2.7-3.0 and >4 MV/cm
respectively. After coat, hot plate bakes of 150, 200, and 350ºC with time of 1 minute
each are used to drive off residual carrier solvent and initiate structural changes in the
film that help to stabilize the film prior to furnace tube annealing. They propose that if
the film is rich in H-Si-O component, the Si-H bond interacts with water to form oxide.
Their work demonstrated that 100 ppm O2 is sufficient to oxidize HSQ for temperatures
above 350ºC. This is in contrast to siloxanes that do not require any oxygen as
previously discussed. They found that the amount of Si-H bond dissociation from
oxidation increases very rapidly with temperature. They proposed that in an oxygen
plasma environment, oxygen radicals attack the Si-H bond leading to formation of porous
oxide and increased hydroxyl content. A neat carbon-tetra-fluoride etch chemistry has
been used to open vias in HSQ-based films.
Lin and coworkers22 report on their development of a non-etch back process for 0.5 um
three-layer-metal interconnect. The material was methyl-silsesquioxane (MSQ) cured
using e-beam energy. One key aspect of the development was to improve resistance to
water absorption. The material was applied as 4600Å coat. The cure conditions were
various combinations of: 250ºC, 30 seconds; e-beam exposure for 2 minutes; 425ºC
furnace for 1 hour; 400ºC hot plate. The e-beam conditions were 5 kV and 3 mC/cm2 or
6 kV and 5mC/cm2 for energy and dose. A capping layer of SiH4-N2O based oxide was
deposited to 1000Å. The FTIR peaks are described in Table 1-8.
Table 1-8: FTIR Peaks22
Wave number Description 3500cm-1 presence of absorbed water 1289cm-1 Si-C bond stretching 2976cm-1 C-H bond stretching (with particular connection
to Si-CH3 bond being present)
20
The FTIR results show that 250ºC for 30 seconds is not sufficient to remove water. The
e-beam cure was successful in removing all evidence of C-H bond stretching. The e-
beam cure resulted in 24 percent reduction in film thickness while the 1 hour thermal
cure at 450ºC caused only an 8 percent reduction. Buffered oxide etch (BOE) was used
to decorate the SEM cross-section samples. The thermally cured MSQ was completely
removed by the BOE etch while the e-beam cured MSQ stained like the densified CVD
oxide. This is consistent with prior reports as well as most recent findings. It should be
possible to develop models that explain why for instance, a 1 um wide feature will cure
uniformly top to bottom while a feature at 0.2 um (or below) does not.
Their e-beam results were not without complications. Measurements of PMOS threshold
voltage showed a significant shift as result of the e-beam exposure while the NMOS had
little effect. The particular memory device employed a poly load resistor (G-ohm level)
that shifted to lower values as a result of e-beam exposure. Some evidence of saturated
drain current (Ids) and effective channel length (Leff) changes were presented. However,
in the absence of statistical comparisons, strength of difference could not be assessed
from the data presented.
A new material entered SOD applications in 1999. Aoki and coworkers23 reported on
conversion of perhydrosilazane in to a low-k (1.6) inorganic film. Use of a 400ºC
nitrogen atmosphere cure is reported. The hydrophobic SiH and SiH2 groups remain in
the film. TDS measurements were made up to 800ºC. The results showed no evidence of
H2O or NH3 evolution. For the conversion, aluminum ethylacteoacetate is used as the
catalyst. The resulting material has a porous granular structure. The composition was
measured and found to have Si/O/N/C atomic percent of 40/55/5/0.5. This is an exciting
new material to add to the list of those requiring fill characterization and modeling.
The use of electron beam curing is contrasted to ion implantation in work by Wang and
coworkers24. Consistent with other SOD material studies, the used FTIR to study of the
21
curing process and thermal stability of a low-k methyl-silsesquioxane (MSQ). They
propose that the mechanism is solvent out diffusion and cross-linking. Methods of cure
include electron beam exposure and ion implantation. The main objective was to
increase resistance to oxygen plasma ashing used for photo resist and etch residue
removal. Refractive index (RI) and thickness measurements were made along with FTIR
spectra collection. SIMS profiles were also collected before and after ashing. The
material was TOK MSQ using a typical track hot plate cure sequence of 80, 150 and
250ºC with 1 minute at each temperature in nitrogen ambient. Blanket film thickness was
targeted to 400 nm. FTIR readings were taken as the average of 50 scans of a heated
sample in vacuum. A typical scan range of 400 to 4000 cm-1 was used. For thickness
and RI measurements, the electron beam and implanted materials were modeled as two
layers to get reasonable goodness of fit (GOF > 0.90). The need to model as two layers
indicates that they were not curing the complete thickness of the film. This is consistent
with the depth profile nature of electron exposure and ion implant. Ion implant
conditions were as follows: specie 75As+; dose 1E15 to 5E15 ions/cm2; energy 80 to 140
keV. They propose that the MSQ cross-linking proceeds as shown in Figure 1-3.
Figure 1-3: MSQ Cross-Linking Reaction24
For the FTIR studies, the researchers highlighted specific peaks of interest. These are
listed in Table 1-9.
Si - OH + OH - Si -O - Si - O - + H2O
22
Table 1-9: FTIR Peaks for MSQ Studies24
Peak cm-1 Bond 710-870 Si-C bond and Si-O bending mode 950 Si-OH groups 1033 solvent 1201 solvent 1272 CH3 deformation 1307 - 1479 solvent 1025 - 1200 Si-O-Si stretching mode 2900 C-H groups 3000 - 3600 OH groups
Their FTIR results support complete solvent evolution by 100ºC. A 425ºC cure is
required to get rid of Si-OH and OH groups. There was no additional change up to
600ºC. They also report that the material is greater than 90 percent cross-linked after a
250ºC bake. The e-beam conditions were as follows: 3 keV, 5000 uC/cm2; 5 keV, 5000
uC/cm2. Film durability would be defined based on evidence of material alteration as a
result of exposure to oxygen plasma ashing. The e-beam cured samples did not exhibit a
shift in FTIR spectra taken before and after oxygen plasma ashing. They propose that the
electrons cause Si-C and C-H bond breaking. They also propose a hardened surface layer
or skin can form during e-beam exposure or ion implant. The need for a two-layer
optical thickness model supports this hypothesis. The SIMS results reported carbon levels
as a function of depth and cure.
In a year 2000 paper, Lee and coworkers25 report on their implementation of e-beam
cured hydrogen-silsesquioxane (HSQ) in a stacked-cap DRAM technology. They used
FTIR, WER, thickness, cure shrinkage, index of refraction, XPS (x-ray photoelectron
spectroscopy) and ESR (Electron Spin Resonance Spectroscopy) to characterize the film.
The specifically note the use of Ta2O5 as a driver for reduced thermal budget. They
report that HSQ normally has poor densification at sidewalls when cured below 700ºC.
The researchers obtained uniform cure using e-beam below 400ºC. After coat, hot plate
bakes of 100, 150 and 300ºC for 1 minute each were used. After the initial drying and
solvent evolution, the following full-cure conditions were evaluated: vacuum at 400ºC for
23
30 minutes; e-beam flood for 260 seconds at 400ºC; tube cure for 30 minutes in N2 at
750ºC after capping with PECVD oxide. They used 200:1 dilute HF for WER
determination. E-beam conditions were: 4-12 kV; 5000 or 10000 uC/cm2; 400ºC; Ar; 20
mA; 10-15 mTorr. The researchers measured Vt, hot carrier degradation; TDDB;
capacitance and leakage of the stack capacitor.
They report the presence of the following peaks for thermally baked HSQ: Si-O main
peaks and the Si-H peaks (HSiO2/2 units) at 1141cm-1, 1070 cm-1 and 2256 cm-1. They
note that other researchers have reported unique peaks for the H2SiO2/2 units at 2200, 982
and 953 cm-1 for the 400ºC reaction (Equation 1-7).
Equation 1-7 2/222/42/32 SiOHSiOHSiO +⇒
The FTIR results were used to conclude that e-beam cured films were silicon rich
compared to the films cured at 750ºC. The etch rate of the e-beam cured HSQ in 200:1
HF was reported to be in the range of 20 to 30 Å/min. The RI decreased from 1.61 at 12
kV cure to 1.52 for 4 kV cure while the RI is 1.40 after 400ºC tube cure. This work, as
with most of the reported literature discussed here, provides thorough materials
characterization from a bulk perspective but does not teach aspects of planarity. One
may argue that in many references planarity was not the topic but in fact, are not all
materials being applied with the purpose of planarization?
One material that has attracted significant interest for deep sub micron applications is
polysilazane. Goo and coworkers26 have reported on their application of polysilazane
SOD material to 60 nm features and below. Key comparisons are made to HDP oxide
and BPSG. These films are commonly and extensively employed in technologies below
250 nm. The researchers point out that BPSG is limited by either high concentration of B
and P and/or high flow temperatures for filling of small gaps. The films also have higher
etch-rates in wet chemistries. In their work, gaps to be filled were narrowed down to 25
24
nm to explore the limits of both fill and cure characteristics. A 700ºC oxidizing ambient
was used to cure polysilazane prior to etching contact holes for polysilicon conductive
plugs. The wet etch-rates were reported to be different in the gaps as compared to larger
patterns of varied density. They also report that sidewall consumption from contact
cleaning increased based on increased spin speed during application of the material.
Some approximate values were: 13 nm/side at 500 rpm; 14 nm/side at 1000 rpm; 18
nm/side at 3000 rpm. Sidewall consumption was also reported to be inversely
proportional to solid content in the solution: 2.5% gave 30 nm/side; 10% gave 30
nm/side; 17% gave 25 nm/side; 22% gave 18 nm/side. The poly plugs in the cured
polysilazane were for connection to the bottom of the charge storage capacitor. The work
by Goo and coworkers begins to explore the issue of cure as a function aspect ratio. This
supports the idea of just how useful a planarization and cure model would be in the
definition of layout rules and coating/cure characterization. In the present, the vast
majority of such decisions are made using empirical results. In the world of process
technology development, time is closely connected to money and useful models can and
do save significant amounts of time. The slope of the so-called learning curve (i.e.
amount of learning per unit of time) can also be increased.
Another recent work using polysilazane deals with the pre-metal dielectric (PMD) section
of a CMOS technology. Lee and coworkers27 report on the application of SZ-SOG to
replace BPSG and/or replace BPSG and CMP. In their application, they coat to a target
thickness of 8000 Å using 1000 rpm followed by hot plate cure for 3 minutes at 150 to
300 ºC in air. The main cure is completed at 900ºC for 30 minutes in a water atmosphere.
FTIR was used to measure bond changes as a result of cure where: Si-N, Si-H, N-H
bonds convert to Si-O while NH3 is evolved. They recommend that the furnace
temperature during loading must be kept below 500ºC and the ramp rate below 20
ºC/min. In this context, “below” is likely to mean slower-than as opposed to numerically
below. Slow ramp rate would reduce likelihood of film cracking. They observed a 19.3
percent film thickness shrinkage from cure with RI of 1.45, k=3.97 and stress at 1.22E09
25
dynes/cm2 compressive. NMOS and PMOS transistor (25x0.5um) Vt were measured.
The implementation appears to be for pre metal planarization in which contact holes are
etched for application of W or poly plugs for electrical connection. The paper makes
reference to obtaining “proper” wet and dry etch properties on a blanket wafer but does
not present any numerical values. It is reasonable to assume that proper means that the
rates were slow enough that existing wet processing did not remove an unacceptable
amount of the cured material. Packaged die were evaluated through 1000 hr operating
life (HTOL) and 1000 cycles of temperature cycling. The researchers noted that they
obtained acceptable reliability.
Polysilazane has also been applied to shallow trench isolation (STI). STI has previously
been largely off limits to SOD materials because of high WER compared to thermal or
HDP oxide unless fully converted to dense SiO2 with a high temperature steam oxidation.
The high etch rates have implications during sacrificial oxidation and gate oxidation
cleans common to CMOS technologies. Heo and coworkers28 have reported on
application of polysilazane (“P-SOG”) to create a pillar at the bottom of the shallow
trench isolation feature. Their stress distribution simulations indicate that the material
creates a low stress fill compared to HDP oxide. Low stress in the bottom of the trench
helps to minimize defect formation in the adjacent single crystal silicon. To create the
pillar, the wafers are initially coated with 2000 Å of SOD and then etched in dilute HF.
The SOD is then cured at 700ºC in an oxidizing ambient prior to being covered with HDP
oxide. SEM sections show that v-shape trenches that are 0.1 um (100 nm) at the top and
1.0 um deep are completely filled. It is proposed that the “P-SOG” has lower stress
because the density is lower. They implemented the approach on a 0.17 um 256 MBit
DRAM technology for comparison to HDP approach. Gate oxide charge to breakdown
(Qbd) was used as a metric to check for grooving at the interface between active area
silicon and field isolation oxide. All results were reported to be greater than 1 C/cm2.
This value can be considered to be acceptable for most applications. They also indicated
that they expect that there will be fewer interface trap states because of the reduced stress.
26
Researchers29 at Dow Corning Corp. have recently (2002) reported on SOD applications
for 0.10 um design rules and below. They point out that a material needs to
simultaneously meet the requirements of: gap fill, thermal budget and wet etch resistance.
They provide a specific example of the 600ºC phase transformation of Ti-silicates as one
thermal budget limitation. Their study of SEM cross-sections reveal the “corner-etch”
patterns of HSQ (hydrogen silsesquioxane) after being etched with 200:1 HF for 90
seconds. The HSQ was steam annealed at 700 ºC for 30 minutes. The “corner-etch”
regions have been reported to function as a stress relief in large regions. From their study
of cure as a function of aspect ratio of feature being filled they make the following
observation: “The densification of spin on materials in the sub micron trenches is a
complicated process.” They offer the following areas of discipline: fluid mechanics,
chemical reactions, mass transfer, heat transfer and interfacial science. Though implied
by the engineering and science fields mentioned, modeling mathematics and
programming are certainly appropriate.
The pattern samples were coated with a thin nitride layer prior to application of the SOD
material. A casting rpm of 2000 was used with a total spin time of 20 seconds. The
researchers used EELS-STEM (Electron Energy Loss Spectroscopy in Scanning
Tunneling Electron Microscope) to map density and composition along with HAADF-
STEM (High Angle Annular Dark Field) imaging. The differing degrees of inelastic
scattering were used to distinguish differences in density. They report much larger low
density regions for N2 cured HSQ as compared to oxidatively cured films. They propose
that, in narrow trenches, the densification of HSQ films is constrained by the capillary
effect and surface skin formation. They go on to state that, “the initial shape and film
height in the trenches are determined by the surface tension of the HSQ solution.” They
also used Ultrasonic Force Microscopy (UFM) to assess film density differences. The
results of the Dow Corning work support the hypothesis that the cure process has unique
limitations as the aspect ratio is increased. However, aspect ratio alone may not be as
27
important as the absolute value of the X term when aspect ratio is defined as Y over X.
The point will be expanded in the proposal of work section.
Though not directly connected to SOD applications, research by Luoh and coworkers30
does reflect the importance of managing stress in STI architectures. They report on the
use of RTP steam oxidation to grow the liner oxide and the sacrificial oxide prior to final
gate oxidation. This is compared to a standard thermal oxidation prior to STI fill with
HDP oxide. The work was done in the context of a 0.25 um design rule flash technology.
The approach uses ISSG (In Situ Steam Generation) in which the H2 and O2 are reacted at
the wafer surface. The OH, O radical and atomic O reaction with Si-Si and Si dangling
and strained Si-O bond occurs at pressures below 20 Torr. The resulting oxide is
reported to have lower corner stresses based on simulations.
The review has now covered the period from 1986 to 2002. The selected works represent
the nature of hundreds of papers covering materials and process implementations in the
period. The next step is to cover some aspects of spin coating that relate to modeling
planarization.
1.3 Highlights of Existing Spin-Coating Models
Stillwagon and Larson31 updated their two-stage flow/shrinkage model to account
qualitatively for solvent evaporation. In the introduction, they point out the simple
relation of the balance between capillary (i.e. surface tension) and centrifugal forces. The
issue of solvent evaporation is included because of the effect on viscosity. The general
idea then is to maintain capillary effects as long a possible because they drive leveling
(i.e. planarization). The centrifugal forces drive the film to a uniform thickness. The
prime example is the casting step in any spin-coat sequence: The rpm selected sets the
film thickness on a bare wafer, and in most cases, on large features (e.g. 1000 um). Their
model is a good candidate as a starting point because it includes: density of fluid, surface
28
tension of fluid to air, angular velocity of spinning substrate, feature width, feature depth
and radial position from center. To first order, the only missing factors would be a term
to describe the nature of the feature before and after the depression being filled. The
work of Stillwagon and Larson is very detailed and will be studied and exercised to a
great extent.
Peurrung and Graves32 followed Stillwagon and Larson to develop a simulation to predict
the effect of an isolated block that disturbs the path of flowing material. They also
include the evaporation effect and specifically point out that drying does not effect the
film shape until the fraction of solvent drops such that the viscosity is high enough to
effectively freeze the film in position. If we follow their assumption that the fraction
shrinkage is constant without regard to thickness, a perfectly planar (global or local)
surface after coat will have depressions where the film is of greatest thickness. This
would suggest that the only method to achieve even local planarity would be to use many
coats. However, present day experience says that such planarity can be achieved even
after high temperature curing of a single coating. Hence, the need for a model that
comprehends not only the coat and dry parameters but also the scaling effects.
Hirasawa and coworkers33 studied the surface-tension driven flow of liquid (i.e. SOG) on
a two-dimensional grooved substrate during the drying or shrinkage phase. Their
modeling approach makes the assumption that spreading (i.e. flow) driven by centrifugal
force occurs mainly in the first 2 to 3 seconds and the dry shrinking occurs in the
following 10 seconds (approximately). Therefore, they treat the two effects separately.
The equation for the surface tension force includes a term for the pressure of the
surrounding gas. The report some useful empirical relations that will guide development
of models that are fine tuned for smaller ranges of conditions. It seems clear from the
existing works that a universal planarization and cure model is not practical, though the
idea is not completely absurd.
29
Control of evaporation during the spin process is covered by various U.S. Patents (circa
1997 to 2000) and reflects the general idea that slowing the evaporation process increases
the length of time that surface tension driven forces can improve planarity. One example
is by Fairchild Technologies Corp.34. They demonstrated improvements in local
planarity of both large (up to 200 um) and small features with 0.7 um steps. The other
example is by Silicon Valley Group36 to be discussed later.
Kucherenko and Leaver35 report on spin coating work in the integrated optics and
micromechanics area. They model features in 2D from 0.6 um to as high as 6 um. Their
simplifications and range of features will provide guidance in developing more fine tuned
models for the range of features encountered in deep sub micron semiconductor
processing.
Gurer and coworkers36 report on the closed cup approach to DUV lithography coatings
and low-k SOD materials. Because of the cost of DUV chemicals, one driving force is to
reduce the amount dispensed per wafer. They report the ability to reduce the amount
from 2 cc to as low as 0.4 cc for a 200 mm wafer. With chemical costs in the thousands
per liter, this is a very important achievement. Their model results indicate that it is
possible to planarize large steps if the evaporation rate can be sufficiently slowed.
Haas and coworkers37 studied the source of striations that can form in SOD coatings.
They point out that surface tension gradients can develop. These gradients cause high
surface tension regions to draw material from low surface tension regions. It is likely that
this is a key factor in modeling the interactions relative to the position of a given feature
from the center of the spinning wafer.
Osredkar38 reported on his work to study the limits of SOG planarization. He concludes
that a planarization factor (i.e. fractional step reduction) of 0.9 may be achievable with
multiple coat/cure steps in local but not global regions.
30
1.4 Initial Work Plan Concepts The next phase of the work is to take the details of published models and calculate results
based on a group of HSQ, MSQ, polymer and polysilazane materials as applied to various
step height features and coating and cure conditions. The first pass will only cover
enough points to determine where the various approaches fail to predict the existing
planarization and cure profiles.
The initial results will guide development of new parameters that are beyond the typical
constants or fitting parameters often employed. Yes, such parameters can often serve a
noble purpose but are not appropriate for this exploratory work. The work will proceed in
an iterative fashion: make model, calculate outcomes, generate test results, refine the
model and parameters, repeat. The desired outcome is to create a family of models that
will guide development of new SOD materials, coat techniques, and layout/structural
rules for future technology.
31
1.5 Section 1 Notes
1. Minoru Nakamura, Ryosaku Kanzawa, and Kohli Sakai, Hitachi Research
Laboratory, Japan, “Stress and Density Effects on Infrared Absorption Spectra of Silicate Glass Films,” J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 133, No. 6, June 1986, pp. 1167-1171. (survey 2)
2. John K. Chu, Jagir S. Multani, Sanjiv K. Mittal, John T. Orton, and Robert Jecmen, Intel Corporation, U.S.A.,“Spin-On-Glass Dielectric Planarization for Double Metal CMOS Technology,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, pp. 474-483 (survey 12)
3. Landon B. Vines, Mostek Corporation, U.S.A., Satish K. Gupta, Allied-Signal Corporation, U.S.A., “Interlevel Dielectric Planarization with Spin-On Glass Films,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, p506-515 (survey 14)
4. A. Rey, D. La Fond, J.M. Mirabel, M.C. Tacussel and M.F. Coster, LETI IRDI, France, “A Double Level Aluminum Interconnection Technology with Spin On Glass Based Insulation,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, pp. 491-499 (survey 17)
5. Pat Elkins, Karen Reinhardt, and Rebecca Tang, Rockwell International Corporation, U.S.A., “A Planarization Process for Double Metal CMOS using Spin-On-Glass as a Sacrificial Layer,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, pp. 100-106 (survey 18)
6. Pei-Lin Pai, Arun Chetty, Robert Roat, Neal Cox, and Chiu Ting, Intel Corporation, Components Research, U.S.A., “Material Characteristics of Spin-On Glasses for Interlayer Dielectric Applications”, J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 134, No. 11, November 1987, pp.2829-2834 (survey 3)
7. H.M. Naguib, C. Jang, T.F. Klemme, K. Wong, A. Rangappan, W.W. Yao and R.T. Fulks, Xerox, U.S.A., “The Evaluation of Planarization Techniques for Double Level Metallization in 1.2 Micron CMOS Technology,” Proceedings of 4th Intl. IEEE V-MIC Conference, June 1987, pp. 93-102 (survey 4)
8. C.H. Ting, H.Y.Lin, Intel Corp., U.S.A., P.L. Pai, W.G. Oldham, UC-Berkeley, U.S.A., “Planarization Process using Spin-On-Glass,” Proceedings of 4th Intl. IEEE V-MIC Conference, June 1987, pp. 61-77 (survey 16)
9. S.N. Chen, Y.C. Chao, J.J. Lin, Y.H. Tsai, and F.C. Tseng, Taiwan Semiconductor Manufacturing Company, Taiwan, “Spin-On Glassess: Characterization and Application,” Proceedings of 5th Intl. IEEE V-MIC Conference, June 1988, pp. 306-312 (survey 13)
10. Seiichi Morimoto and Sarah Queller Grant, Intel Corporation, U.S.A., Manufacturable and Reliable Spin-On-Glass Planarization Process for 1 um CMOS Double Layer Metal Technology,” Proceedings of 5th Intl. V-MIC Conference, June 1988, pp. 411-418 (survey 5)
32
11. Daniel L.W. Yen and Gopal K. Rao, Philips Research Laboratories, The Netherlands, “Process Integration with Spin-On-Glass Sandwich as an Intermetal Dielectric Layer for 1.2um CMOS DLM Process,” Proceedings of 5th Intl. V-MIC Conference, June 1988, pp. 85-94. (survey 6)
12. Paul E. Riley and Attila Shelley, Fairchild Research Center, U.S.A., “Characterization of a Spin-Applied Dielectric for Use in Multilevel Metallization,” J. Electrochem. Soc.: Solid-State Science and Technology, May 1988, pp. 1207-1210. (survey 7)
13. C.H. Ting, H.Y. Lin, P.L. Pai and T. Rucker, Intel Corporation, U.S.A., “A Non-Etchback SOG Process For Multilevel Interconnect Technology,” Electrochem. Soc. Fall Meeting, 1988, Extended Abstracts No. 257, p. 366 (survey 8)
14. S. Ito, Y. Homma, E. Sasaki, S. Uchimura, and H. Morishima, Hitachi Research, Japan, “Application of Surface Reformed Thick Spin-On-Glass to MOS Device Planarization,” Electrochem. Soc. Conf. Spring 1989. Extended Abstract No. 178, p. 258 (survey 9)
15. R. J. Hopkins, T. A. Baldwin, and S. K. Gupta, Allied-Signal Inc., U.S.A., “Characterization of SOG Materials for use in ULSI Dielectric Planarization Processes,” Electrochem. Soc. Spring 1989, Extended Abstract No. 177, p. 257 (survey 10)
16. Pankaj K. Sinha and John A. Smythe, National Semiconductor, U.S.A,“Moisture and Phosphorous Sensitivity of Sacrificial Spin-On-Glass Dielectric Planarization Process”, Journal of Electro. Chem. Soc. Vol 138, No. 3, March 1991, pp 854-855 (Survey 30)
17. Tadashi Nakano and Tomohiro Ohta, LSI Research Laboratories, Kawasaki Steel Corporation, Japan, “Relationship Between Chemical Composition and Film Properties of Organic Spin-on Glass,” J. Electrochem Soc., Vol. 142, No. 3, March 1995, pp. 918-925 (survey 1)
18. L. Forester, S.B. Kimo, D.K. Choi, J.H. Koo, J.C. Kimo, M. Ross*, W.R. Livesay*, and J.J. Yang, AlliedSignal, U.S.A., oHyundai Electronics, Korea, *Electron Vision, U.S.A., “Novel Flood Exposure Siloxane Spin-On Glass Elctron-Beam Curing and Application to Non-Etchback Process,” June 1996, 13th Intl. VMIC Conference Proceedings, pp. 119-121 (survey 21)
19. Pete Singer, , U.S.A., “New Frontiers in Spin-On Dielectrics”, Semiconductor International, vol. 20, Issue 5, May 1997, pp. 73-76 (survey 27)
20. J.J.Yang, D.K.Choi, L Forester and M. Ross, Allied Signal Inc.,U.S.A., “Electron Beam Curing of Siloxane SOG for Non-Etch Back Process,” Conference Proceedings ULSI XII, 1997, Materials Research Society, pp.505-509 (survey 20)
21. Mark J. Loboda, George A. Toskey, Dow Corning Corp., U.S.A., “Understanding Hydrogen Silsesquioxane-based Dielectric Film Processing,” SolidState Technology, May 1998 (survey 11)
22. Chi-Fa Lin, I-Chung Tung and Ming-Shiann Feng, Winbond Electronics Corporation, Taiwan, “Effects of Methyl Silsesquioxane Electron-Beam Curing on Device Characterizatics of Logic and Four-Transistor Static Random-Access
33
Memory”, Jpn. J. Appl. Phys. Vol. 38 (1999), Part 1, No. 11, November 1999, pp. 6253-6257 (survey 19)
23. T. Aoki*, Y. Shimizu* and T. Kikkawa**, *Tonen Corporation, Japan, **Hiroshima Univeristy, Japan, “Porous Silicon Oxynitride Films Derived from Polysilazane as a Novel Low-Dielectric Constant Material,” Mat. Res. Soc. Symp. Proc. Vol. 565, 1999 pp.41-46 (survey 25)
24. C.Y. Wang,1 J.Z. Zheng,2 Z.X. Shen,1 Y. Xu,2 S.L. Lim,1 R. Liu1 and A.C. H. Huan1, 1National University of Singapore, Singapore, 2Chartered Semiconductor Manufacturing Ltd., Singapore, “Characterization of a Low-k Orgainic Spin-on-glass as an Intermetal Dielectric,” Surf. Interface Anal. 28, 97-100 (1999) (survey 29)
25. Hae-Jeong Lee, Juseon Goo, Seong-Ho Kim, Jin-Gi Hong, Hyeon-Deok Lee, Ho-Kyu Kang, Sang-In Lee, and Moon Yong Lee, Samsung Electronics Co, Korea, “A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device,” Jpn. J. Appl. Phys. Vol. 39 (2000), Part 1, No. 7A, July 2000, pp. 3924-3929 (survey 22)
26. Juseon Goo, Eunkee Hong, Hong-Gun Kim, Hyun Jo Kim, Eun Kyung Baek, Sun-Hoo Park, Jubum Lee, Hyeon Deok Lee, Ho-Hyu Kang, Joo-Tae Moon, Samsung Electronics Co., Korea, “A Highly Manufacturable, Low-Thermal Budget, Void and Seam Free Pre-Metal-Dielectric Process Using New SOG for beyond 60nm DRAM and Other Devices,” 2001, IEEE, IEDM 01-271 pp271-274 (survey 23)
27. Jung-Ho Lee, Jung-Sik Choi, Dong-Jun Lee, Sang-Moon Chon, Sun-Sam Hwang, Sang-Deog Cho, Samsung Electronics Co., Korea, “A Study on ILD Process of Simple and CMP Skip using Polysilazane-based SOG,” 2001 IEEE (survey 31)
28. Jin-Hwa Heo, Soo-Jin Hong, Dong-Ho Ahn, Hyun-Duk Cho, Moon-Han Park, Kazuyuki Fujihara, U-In Chung, Yong-Chul Oh and Joo-Tae Moon, Samsung Electronics Co, Korea, “Void Free and Low Stress Shallow Trench Isolation Technology using P-SOG for sub 0.1um Devuce,” 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 132-133 (survey 24)
29. Zhongtao Li, Xiaobing Zhou, Dave Wyman, Mike Spaulding, Ginam Kim, Stelian Grigoras, DK Choi, and Eric Moyer, Dow Corning Corp., U.S.A., “Development of Spin-On Pre Metal Dielectrics (PMD) for 0.10um Design Rule and Beyond,” 2002 Mat. Res. Soc. Symp. Proc. Vol 716 pp. B7.10.1-.6 (survey 15)
30. T. Luoh, C.S. Chen, L.W. Yang, H.H. Shih, K.C. Chen, C. Hsueh, H. Chung, S. Pan, and C.Y. Lu, Macronix International, Taiwan, “Stress Release for Shallow Trench Isolation by Single-Wafer, Rapis Thermal Steam Oxidation,” 10th IEEE International Conference on Advanced Thermal Processing of Semiconductors - RTP 2002 pp. 111-118. (survey 26)
31. L.E. Stillwagon and R.G. Larson, AT&T Bell Laboratories, U.S.A., “Planarization during spin coating,” Phys. Fluids A 4 (5), May 1992, pp. 895-903
32. Loni M. Peurrung and David B. Graves, UC Berkeley, U.S.A., “Spin Coating Over Topography,” IEEE Trans. on Semi. Manufacturing, VOL 6, No. 1, Feb. 1993, pp. 72-76
34
33. S. Hirasawa, Y. Saito, H. Nezu, N. Ohashi, H. Maruyama, Hitachi Limited, Japan, “Analysis of Drying Shrinkage and Flow due to Surface Tension of Spin-Coated Films on Grooved Substrates,” HTD-Vol. 336/FED-Vol. 240, Transport Phenomena in Materials Processing and Manufacturing, ASME 1996 pp. 221-226 (Note: This work also published in IEEE Trans. on Semi. Manuf. Vol. 10, No. 4, Nov. 1997, pp. 438-444)
34. W. Cai, T. Batchelder, Fairchild Technologies Corp.; J. Kennedy, AlliedSignal Corp., U.S.A., “Wafer Planarization with Low-k Spin-Coated Films,” Semiconductor International, June 1997, pp. 117-120
35. S.S. Kucherenko and K. D. Leaver, Imperial College, UK, “Modeling effects of surface tension on surface topology in spin coatings for integrated optics and micromechanics,” J. Micromech. Microeng. 10 (2000) pp. 299-308
36. E. Gurer, T. Zhong, J. Lewellen, E. Lee, Silicon Valley Group, U.S.A, “A novel spin coating technology for 248nm/193nm DUV lithography and low-k spin on dielectrics of 200/300mm wafers,” Advances in Resist Technology and Processing XVII, Francis M. Houlihan, Editor, Proceedings of SPIE Vol. 3999 (2000), pp. 805-817
37. D.E. Haas, D.P. Birnie, III, University of Arizona; M. J. Zecchino, J.T. Figueroa, Veeco Metrology Group, U.S.A., “The effect of radial position and spin speed on striation spacing in spin on glass coatings,” J. of Mat. Science Let. 20, 2001, pp. 1763-1766
38. R. Osredkar, University of Ljubljana, Slovenia, “A Study of the Limits of Spin-On-Glass Planarization Process”, Informacije MIDEM 31 (2001) 2, pp. 102-105
35
2 Planarity and Density Model Approach
2.1 Introduction Details of SOG and SOD history was reviewed in Section 1. The following section will
build upon the understanding to develop a more detailed plan. The basic technique draws
from the planarizing nature of a liquid when applied to surface topography. A useful
model must deal with, at a minimum, the two characteristics that are important for
integration of SOD materials: prediction of planarity and prediction of material
properties. In both cases, the prediction needs to be in terms of the specific feature or
features of interest.
The first characteristic has not been addressed with rigor relative to the interaction
between underlying topography and degree of local and global planarization. The general
concepts are widely known in the industry but little has been done to provide models that
guide the 2D-layout rules of semiconductor circuit design. Now that widely used SOD
materials have been sufficiently refined and new materials developed, it is appropriate to
develop models that will guide optimization of layout to facilitate optimum benefit from
implementation of SOD materials in sub 100 nm semiconductor process technologies.
The second characteristic has been studied as a result of integration evaluations to replace
or complement various CVD layers. Published works over the last few years have begun
to recognize an effect that is unique to small features. Bulk material characterization and
understanding is a necessary but not sufficient step for successful application of SOD
materials. The small feature effect has become a limiting factor in successful integration
of SOD materials for certain applications.
This work reviews some of the details behind modeling the local and global planarization
character of SOD materials in the context of underlying topography and how those results
36
would be used to guide 2D-layout rules and define limitations in the 3D sense. The work
also reviews the background and proposes potential modeling aspects of the small feature
effect.
2.2 Discussion of Available Modeling Approaches for Planarity The work by J.K. Chu et.al.1 provides insight to some of the integration issues associated
with implementation of SOG materials. With regards to planarization, they report, “The
amount of SOG remaining in the device depends on the underlying metal aspect ratio and
the initial CVD dielectric thickness”. As discussed in 1.2, they provide a metric for
degree of planarization for empirical use but did not attempt to model.
Vines and Gupta2, in a joint work, report on inter-metal dielectric planarization using
Allied Chemical Accuglass 204 and 105/305 materials. The researchers report that the
Accuglass 105 forms a thinner layer on top of metal lines than the 305. The distinction
between 105 and 305 is that 105 has a lower viscosity and is blended to achieve a lower
thickness on a bare wafer for a given set of spin conditions. This detail supports the
importance of viscosity as a model input.
Pei-Lin Pai and coworkers3 reported their findings as a result of detailed characterization
of materials properties of polysiloxane. They point out that stress (tensile) can be
attributed to film shrinkage. The film maintains the high tensile stress. The reference to
stress is included because of its potential as a contributing mechanism in the explanation
of the small feature effect. This work was reviewed in more detail in Section 1.2.
The work of Naguib et. al4 examined the implementation of SOG in a 1.2 um design rule
double metal process. The researchers proposed a metric of planarity as a function of the
line-space pitch as discussed in Section 1.2. The general idea is that a small gap (relative
37
to the coat thickness) can be near 100 percent planar while larger features are only
smoothed. Clearly, aspect ratio and absolute gap width will need to be model inputs.
Morimoto and Grant5 define planarity as the slope of the oxide surface between feature
lines. They state that the spin characteristics are also affected by the organic content.
Higher organic content gives better planarity for the same thickness. One specific
example is that higher organic content materials form a local mounding of thick SOG on
wide metal features. Their results support a model factor to reflect organic content and
possibly molecular weight.
Planarization performance of a Tokyo Okha material was measured in work by Yen and
Rao6 on a 1.2 um design rule double metal technology. They reported that degree of
planarity was found to have different ranges depending on step height for the same
spacing as discussed in Section 1.2. The numeric order reflects the expected relation that
for a given step height and coating thickness, the percent planarity will increase as the
spacing decreases. This is one example of how useful a comprehensive model would be
for definition of materials requirements and layout rules.
One of the benchmark materials studies was by Nakano and Ohta7. They studied
inorganic (silicate; silanol Si-OH) and organic (siloxane) SOD materials. They propose
that the solvent is the dominant factor for film quality and coating characteristics. For
direct reference in simulations, their viscosity tables (Table 2-1 and Table 2-2 have been
repeated here from Section 1.2 for convenience.
38
Table 2-1: Table III7 For Viscosity from 2.44 to 5.33 mPa-s
SOG Main Solvent Sub Solvent Viscosity at 25ºC (mPa S)
Striation
A Methanol 1-Propoxy-2-propanol 4.61 + B Methanol 1-Propoxy-2-propanol, water 5.22 + C Ethanol Butyl acetate, Butanol 2.18 - D Methanol 1-Propoxy-2-propanol, water 4.79 ++
E Methanol 2-Propanol 2-Methylpropyl acetate 2.44 -
F Ethanol 2-Propanol, Acetone Butanol 2.54 -
G Ethanol 2-Propanol, Acetone 3.15 + or -
Table 2-2: Table IV7 for viscosity of solvents from 0.59 to 3.18 mPa-s
Solvent Viscosity at 20ºC (mPa - s)
Methanol 0.59 Ethanol 1.22 2-Propanol 2.41 Butanol 2.95 Acetone 0.80 Butyl acetate 0.88 2-Methylpropyl acetate 0.88 1-Propoxy-2-propanol 3.18(1) (1) measured at 25ºC
Note: For reference, 10 Poise = 1 Pa – sec, or 1 cP = 1 mPa-sec, where the units of mPa-sec are
often used in other works. After extensive study, the researchers provide the following broad conclusion:
“There appears to be no obvious relation between gap filling
properties and the chemical compositions. Gap filling phenomena
relate not only to a complex behavior of the surface tension and
viscosity change of the solution as a function of its concentration and
the spinning speed, but also interfacial tension between the solution and
the under layer film.”
This general guidance will be heeded in model development.
39
For material curing, researchers have reported use of electron-beam exposure to cure
siloxane8,9, MSQ10, HSQ11. Others12,13,14 have used thermal processing with a relatively
new material, polysilazane. These works will provide some insight should a small
feature effect model be pursued.
Researchers15 at Dow Corning Corp. have recently (2002) reported on SOD applications
for 0.10 um design rules and below. Their study of SEM cross-sections reveal the
“corner-etch” patterns of HSQ (hydrogen silsesquioxane) after being etched with 200:1
HF for 90 seconds. From their study of cure as a function of aspect ratio of feature being
filled they make the following observation: “The densification of spin on materials in the
sub micron trenches is a complicated process.” They offer the following areas of
discipline: fluid mechanics, chemical reactions, mass transfer, heat transfer and
interfacial science. Though implied by the engineering and science fields mentioned,
modeling mathematics and programming are certainly appropriate. Their points will
prove valuable for potential small feature effect models.
They propose that, in narrow trenches, the densification of HSQ films is constrained by
the capillary effect and surface skin formation. They go on to state that, “the initial shape
and film height in the trenches are determined by the surface tension of the HSQ
solution.” The results of the Dow Corning work support the hypothesis that the cure
process has unique limitations as the aspect ratio is increased. This observation may be a
function of the local curvature and the resulting change in surface area that would
increase evaporation rate. However, aspect ratio alone may not be as important as the
absolute value of the X term when aspect ratio is defined as Y over X. The point will be
expanded in the proposal of work section.
40
2.3 Modeling Spin-Coating Planarization
Stillwagon and Larson16 updated their two-stage flow/shrinkage model to account
qualitatively for solvent evaporation. In the introduction, they point out the simple
relation of the balance between capillary (i.e. surface tension) and centrifugal forces. The
issue of solvent evaporation is included because of the effect on viscosity. The general
idea then is to maintain capillary effects as long a possible because they drive leveling
(i.e. planarization). The centrifugal forces drive the film to a uniform thickness. The
prime example is the so-called casting step in the spin-coat sequence: The rpm selected
sets the film thickness on a bare wafer, and in most cases, on large features (e.g. 1000
um). Their model is a good candidate as a starting point because it includes: density of
fluid, surface tension of fluid to air, angular velocity of spinning substrate, feature width,
feature depth and radial position from center. To first order, the only missing factors
would be a term to describe the nature of the feature before and after the depression being
filled. The work of Stillwagon and Larson is very detailed and will be studied and
exercised to a great extent.
The following discussion reviews the component details of the Stillwagon and Larson
model. For the flow stage of the model, planarization is given as P1. The value of P1 is
calculated based on fundamental lubrication analysis for features with high values of w/d.
Where w is the feature width and d is the feature depth. In deep sub-micron
semiconductor applications the concept of aspect ratio is given as the opposite relation
d/w, or more commonly, h/w. In this case, h is later used to refer to the coating film
thickness so d will be kept as the parameter representing the depth of the feature or step-
height to be planarized. The lubrication analysis is based on a balance between capillary
and apparent centrifugal forces.
They give the following relation as Equation 2-1 to express this balance:
41
Equation 2-1 1
3221
ωh
rw o
γρ
=Ω
Ω = dimensionless value ρ = density of the fluid (SOD Material of interest) γ = surface tension against air w = width of feature (at depth d) h1 = film thickness on flat featureless area (i.e. un-patterened substrate or very large area) ro = radial distance of the feature from the center of the feature (this definition is not supported by any kind of schematic) The model predictions are for trenches arranged in concentric rings. One can interpret
this to mean that the estimates apply to the infinitesimal case where the flow is normal to
the step to be planarized.
In the case of the common 200 mm wafer used in semiconductor applications, the two
factors angular velocity and ro are inter-related in the sense that for a given RPM, the
value of angular velocity changes with ro. Hence, the model will need to comprehend the
complete wafer condition. For example, in the controlled studies, individual features can
be examined for fixed ro and variable omega. While for the whole wafer case, we must
somehow comprehend the effects of omega changing with ro. Research12 has shown a
difference in post-clean dimensional change as a result of differences in RPM (and hence
angular velocity and centripetal forces). In their case, higher RPM was correlated to
higher wet chemical etch rates hole-type features. The value P1 is then plotted against
values of 21Ω with different curves for various values of h1/d for isolated trench-like
features.
Stillwagon and Larson make reference to the work of Emslie et al. who provided the flow
relation:
42
Equation 2-2
2/1
341
−
+= T
rH
o
ω where
fhhH ≡ and
cttT ≡
From this, Stillwagon and Larson define tc as centrifugal time. The value is given by
( ) ofc rh
wt22 ωρ
η≡ where η is the material viscosity. The centrifugal time is defined as
the time required for the local film profile over the feature to come to equilibrium with
the centrifugal field given a fixed film thickness far from the feature. The other factor is
called the spin-down time and is given by
Equation 2-3 wrtt oc
s ≡
The third time factor is the time tL required for leveling from capillary forces. In the
absence of centrifugal forces, this, in general, describes the condition when the film
becomes level. This idea assumes that there is sufficient material to fill the feature. That
is, hf is greater than d.
Equation 2-4 23
4
Ω=≡ cf
L th
tγωη
In a prior work17, Stillwagon and Larson gave typical values for the variables. Those are
reproduced for reference in Table 2-3.
43
Table 2-3: Typical Values for Planarity Variables
Variable Numeric Range Unit of Measure ρ 1 g/ml ω 200-850 (2000-8000) rad/sec (RPM) w 1-200 um ro 1-10 cm γ 20-50 dyn/cm hf 0.5-2 um
hf is the film thickness far from the feature d, the feature depth, is stated to be typically 1 um
For present day semiconductor applications, angular velocity extends down to 1000
RPM, w extends down to below 0.1 um (100 nm), surface tension can be near 10, film
thickness extends down to 0.2 um (200 nm) and d can be in the range of 0.2 to 2 um.
Peurrung and Graves18 followed Stillwagon and Larson to develop a simulation to predict
the effect of an isolated block that disturbs the path of flowing material. They also
include the evaporation effect and specifically point out that drying does not effect the
film shape until the fraction of solvent drops such that the viscosity is high enough to
effectively freeze the film in position. If we follow their assumption that the fraction
shrinkage is constant without regard to thickness, a perfectly planar (global or local)
surface after coat will have depressions where the film is of greatest thickness. This
would suggest that the only method to achieve even local planarity would be to use many
coats. However, present day experience says that such planarity can be achieved even
after high temperature curing of a single coating. One hypothesis is that the surface forms
an inflexible skin such that the feature dependent shrinkage is constrained. This may in
fact be a root cause of the small feature effect. Hence, the need for a model that
comprehends not only the coat and dry parameters but also the scaling effects.
Hirasawa and coworkers19 studied the surface-tension driven flow of liquid (i.e. SOG) on
a two-dimensional grooved substrate during the drying or shrinkage phase. Their
modeling approach makes the assumption that spreading (i.e. flow) driven by the
44
apparent centrifugal force occurs mainly in the first 2 to 3 seconds and the dry shrinking
occurs in the following 10 seconds (approximately). Therefore, they treat the two effects
separately. The equation for the surface tension force includes a term for the pressure of
the surrounding gas. They report some useful empirical relations that will guide
development of models that are fine-tuned for smaller ranges of conditions. It seems
clear from the existing works that a universal planarization and cure model is not
practical, though the idea is not completely absurd.
Control of evaporation during the spin process is covered by various U.S. Patents (circa
1997 to 2000) and reflects the general idea that slowing the evaporation process increases
the length of time that surface tension driven forces can improve planarity. One example
is by Fairchild Technologies Corp.20, they demonstrated improvements in local planarity
of both large (up to 200 um) and small features with 0.7 um steps. The other example is
by Silicon Valley Group22 to be discussed later.
Kucherenko and Leaver21 report on spin coating work in the integrated optics and micro-
mechanics area. They model features in 2D from 0.6 um to as high as 6 um. Their
simplifications and range of features will provide guidance in developing more fine tuned
models for the range of features encountered in deep sub micron semiconductor
processing.
Gurer and coworkers22 report on the closed cup approach to DUV lithography coatings
and low-k SOD materials. Their model results indicate that it is possible to planarize
large steps if the evaporation rate can be sufficiently slowed.
Haas and coworkers23 studied the source of striations that can form in SOD coatings.
They point out that surface tension gradients can develop. These gradients cause high
45
surface tension regions to draw material from low surface tension regions. It is likely that
this is a key factor in modeling the interactions relative to the position of a given feature
from the center of the spinning wafer.
2.4 Proposed Work for Global Planarity The next phase of the work is to take the details of published models and calculate results
based on a group of HSQ, MSQ, polymer and polysilazane materials as applied to various
step height features and coating and cure conditions. The first pass will only cover
enough points to determine where the various approaches fail to predict the existing
planarization and cure (i.e. densification) profiles as a function of radial location, w, d
and the critical aspect ratio of d/w. Prior works have used the ratio w/d but for this
work, the more relevant ratio is the inverse.
The initial results will guide development of new parameters that are beyond the typical
constants or fitting parameters often employed. Yes, such parameters can often serve a
noble purpose but are not appropriate for this exploratory work.
Initial data collection plan is to measure planarity and density for w from 80 nm to 800
nm, d from 250 nm to 400 nm and ro from 0 (i.e. < 2 mm) to 90 mm. The longer view is
to extend to values of w from 8000 nm (8 microns) to 100s of microns.
An example of large feature planarity is shown in Figure 2-1. The plot is created from
the stylus deflection signal of a surface profiler. The double-ended arrow shows the
degree of planarity from the base plane achieved for spaces that are a factor of 30
smaller. Ten units in the Z-axis are equal to one unit in the X-axis.
46
Global Planarity for Large Features
0
5
10
15
20
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
Distance Units
Uni
ts in
Z-a
xis
Normalized base plane
Figure 2-1: Global Planarity for Large Features
The zoomed view in Figure 2-2 shows the symmetry of the space planarity. There is
some evidence of standing wave formation. The results are from an initial test of a thick
coat HSQ material using a dynamic dispense and casting spin with following dry step.
Global Planarity for Large Features - Zoomed View
02468
1012141618
700
750
800
850
900
950
Distance Units
Units
in Z
-Axi
s
Figure 2-2: Global Planarity for Large Features - Zoomed View
47
Optical image showing the region of zoom in Figure 2-2. Fringe lines are consistent with the surface profile results.
Figure 2-3: Optical Image of Large Feature Sample
The preceding figures and associated observations provide a baseline for more detailed
study of the factors that influence the planarization effect. The work is expected to
proceed in an iterative fashion: collect data; make model; calculate outcomes; generate
prediction for comparison to observations; refine the model and parameters; repeat. The
desired outcome is to create a family of models that will guide development of new SOD
materials, coat techniques, and layout/structural rules for future technology.
An initial interpretation of the Stillwagon and Larson model16,17 is provided here for
various conditions to be evaluated. The interpretation examines the unit-less term Ω2 in
the regime of surface tension from 10 to 20 dyn/cm and values of w from 0.1 to 5
microns. The full range is shown in Figure 2-4 while the sub-micron range is shown in
Figure 2-5. The general relation reported in prior works predicts increased planarity for
values of Ω2 below 10-2. The figures show the predicted effect of surface tension of the
SOD in relation to the surface being coated. The inputs to Ω2 are SOD density (SOD in
solvent), wafer angular velocity, trench width, and radial position of trench (9 cm) and
SOD surface tension.
48
Omega2
5000A film, 5000A depth
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
0 1 2 3 4 5 6Trench Width (um)
Surf Tens 40Surf Tens 20Surf Tens 10
Figure 2-4: Calculated Omega2 for expected condition
Omega2
5000A film, 5000A depth
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
Trench Width (um)
Surf Tens 40Surf Tens 20Surf Tens 10
Figure 2-5: Calculated Omega2 in sub-micron range
49
2.5 Proposed Work for Small Feature Effect The small feature effect is defined as the case where a feature filled by SOD is
sufficiently small that the material no longer maintains bulk properties. This condition
may exist as soon as after solvent bake out or as late as the final cure, or reaction, to the
desired bulk property. In this context, bulk property refers to that observed for a blanket
layer coated on un-patterned sample or for a feature that is greater than 50 microns in X
and Y.
Etch rate of blanket films in wet chemistry will be used to provide a measure of bulk film
properties. The same materials used for blanket films will be applied to pattern samples
with various values of w and d. The materials will be applied through a range of
thickness values and then processed through various cure environments. The term cure
will be used in reference to any condition that results in a change in the material. Hence,
this can include simple steps such as hot plate nitrogen treatment up to steps that are more
complex.
One example is when a typical SOD material is exposed to oxygen plasma. The effect is
shown in Figure 2-6 and Figure 2-7. The first shows the porous appearance in the narrow
trench region for a cross-section sample that has not been exposed to any kind of
decoration etch. The second photo shows the effect of a short exposure to an HF based
etch solution. The oxide structure is completely removed as indicated by the dark region
of Figure 2-7.
50
Figure 2-6: Small Feature Image without Etch
Figure 2-7: Small Feature Image with Etch
A second example is for SOD material treated with a combination of steam ambient and
oxygen ambient at temperatures above 800ºC. This example provides a direct
comparison of a region that is smaller by near a factor of 4 in w but with the same value
of d. The arrow in Figure 2-8 indicates the direction of decreasing material density or
change in material character. It is pointed out in this manner because it will be
subsequently shown by TEM image that density alone is not the driving factor to cause
an increase in material removal rate in the etchant used for decoration. This vertical
transition is not evident for the feature shown in Figure 2-9. When the feature size is on
the order of 20 microns in X and Y (in the horizontal plane) optical measurements have
shown that the material has the same wet etch rate (WER) as a blanket film of similar
thickness. Blanket is a term used to refer to a uniform coating on an un-patterned wafer.
Region of Normal Density
51
Figure 2-8: Small Feature Effect
Figure 2-9: Wide Feature Density
The effect shown in Figure 2-6 through Figure 2-9 is known in the semiconductor
industry but is not well understood. To a certain extent, cost effective implementation is
limited by the need to complete a single coat and then react the material to the desired
characteristic. Though multi-step sequences can overcome much of this effect, they are
not cost effective. Therefore, this work will focus on finding the limiting mechanisms for
the case shown.
One factor must be diffusion of oxidizing species through the material and removal of
gaseous by products. If this is a main effect, then the amount of material above the small
feature should have some influence on the etch rate. The two cases shown in Figure 2-10
support that simple diffusion may not be a primary factor for the model.
52
Case A: SOD fills just to near the top of the
trench feature.
Case B: SOD is approximately 40 to 50 percent
of trench depth above the top of the trench.
Figure 2-10: Thickness Effect of Densification Reaction
The photos shown in Figure 2-11 of the wider features support uniform etch rate through
the complete depth without regard to amount of SOD material above the feature opening.
It is also important to note that the curvature over the wide feature does not indicate that
material shrinkage is different within the limitation of the SEM photo as metrology. For
solvent-based materials (like photo chemicals) shrinkage is generally stated as a
percentage. Therefore, if SOD was acting primarily with linear shrinkage, the radius of
curvature should have decreased proportionate to the difference in thickness of region A
compared to region B (right side of Figure 2-11).
53
Wide Feature from Case A, Figure 2-10 Wide Feature from Case B, Figure 2-10
Figure 2-11: Thickness Effect of Densification Reaction
2.6 Materials and Structures There are three general material categories: hydrogen silsesquioxane (HSQ), methyl
silsesquioxane (MSQ) and polysilazane. Treatments for densification are expected to
include, but are not limited to, thermal treatments in various ambient gas environments,
electron beam exposure, plasma exposure and various wet chemical exposures. The work
is expected to include combinations as required.
All work will be completed using 200-mm silicon substrates with topography. Materials
will be dispensed either automatically or by hand depending on the material being
evaluated. Coated samples will all include a minimum amount of hot plate baking to
reduce solvent levels prior to subsequent cure reaction steps.
A
B
54
2.7 Analytical Methods FTIR will be used as a reference method to determine the bulk character of materials
after reaction treatments. Optical methods will be used to determine film thickness
changes and refractive index. SEM section samples will be used to determine the relative
etch rate of material in narrow and wide features. WER (wet etch rate) of large area
features and blanket films will be collected as a reference for correlation to small feature
etching. Section samples will be etched in various wet chemical solutions for correlation
to the blanket films. Auger (and others as made available) elemental mapping will be
used to determine distribution of expected components.
Surface profiles (contact stylus and AFM) will be collected to determine degree of
planarity. Optical measurements will be made to corroborate the surface profile
measurements.
2.8 Next Steps
Define initial set of conditions for screening experiment and run samples using one or
more of PZ, HSQ, and MSQ materials. Samples will be measured by surface profile and
optical methods. The optical method is currently limited to larger features (e.g. greater
than 5 um). Samples will then be processed through the appropriate densification step
and measured again by surface profile and optical methods. Finally, for small feature
effect investigations, samples will be cross-sectioned and etched with various chemistries
to determine the nature of bonding and composition in small features compared to large
features.
55
2.9 Section 2 Notes
1. John K. Chu, Jagir S. Multani, Sanjiv K. Mittal, John T. Orton, and Robert Jecmen, Intel Corporation, U.S.A.,“Spin-On-Glass Dielectric Planarization for Double Metal CMOS Technology,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, pp. 474-483 (survey 12)
2. Landon B. Vines, Mostek Corporation, U.S.A., Satish K. Gupta, Allied-Signal Corporation, U.S.A., “Interlevel Dielectric Planarization with Spin-On Glass Films,” Proceedings of 3rd Intl. IEEE V-MIC Conference, June 1986, p506-515 (survey 14)
3. Pei-Lin Pai, Arun Chetty, Robert Roat, Neal Cox, and Chiu Ting, Intel Corporation, Components Research, U.S.A., “Material Characteristics of Spin-On Glasses for Interlayer Dielectric Applications”, J. Electrochem. Soc.: Solid-State Science and Technology, Vol. 134, No. 11, November 1987, pp.2829-2834 (survey 3)
4. H.M. Naguib, C. Jang, T.F. Klemme, K. Wong, A. Rangappan, W.W. Yao and R.T. Fulks, Xerox, U.S.A., “The Evaluation of Planarization Techniques for Double Level Metallization in 1.2 Micron CMOS Technology,” Proceedings of 4th Intl. IEEE V-MIC Conference, June 1987, pp. 93-102 (survey 4)
5. Seiichi Morimoto and Sarah Queller Grant, Intel Corporation, U.S.A., Manufacturable and Reliable Spin-On-Glass Planarization Process for 1 um CMOS Double Layer Metal Technology,” Proceedings of 5th Intl. V-MIC Conference, June 1988, pp. 411-418 (survey 5)
6. Daniel L.W. Yen and Gopal K. Rao, Philips Research Laboratories, The Netherlands, “Process Integration with Spin-On-Glass Sandwich as an Intermetal Dielectric Layer for 1.2um CMOS DLM Process,” Proceedings of 5th Intl. V-MIC Conference, June 1988, pp. 85-94. (survey 6)
7. Tadashi Nakano and Tomohiro Ohta, LSI Research Laboratories, Kawasaki Steel Corporation, Japan, “Relationship Between Chemical Composition and Film Properties of Organic Spin-on Glass,” J. Electrochem Soc., Vol. 142, No. 3, March 1995, pp. 918-925 (survey 1)
8. L. Forester, S.B. Kimo, D.K. Choi, J.H. Koo, J.C. Kimo, M. Ross*, W.R. Livesay*, and J.J. Yang, AlliedSignal, U.S.A., oHyundai Electronics, Korea, *Electron Vision, U.S.A., “Novel Flood Exposure Siloxane Spin-On Glass Elctron-Beam Curing and Application to Non-Etchback Process,” June 1996, 13th Intl. VMIC Conference Proceedings, pp. 119-121 (survey 21)
9. J.J.Yang, D.K.Choi, L Forester and M. Ross, Allied Signal Inc.,U.S.A., “Electron Beam Curing of Siloxane SOG for Non-Etch Back Process,” Conference Proceedings ULSI XII, 1997, Materials Research Society, pp.505-509 (survey 20)
10. Chi-Fa Lin, I-Chung Tung and Ming-Shiann Feng, Winbond Electronics Corporation, Taiwan, “Effects of Methyl Silsesquioxane Electron-Beam Curing on Device Characterizatics of Logic and Four-Transistor Static Random-Access
56
Memory”, Jpn. J. Appl. Phys. Vol. 38 (1999), Part 1, No. 11, November 1999, pp. 6253-6257 (survey 19)
11. Hae-Jeong Lee, Juseon Goo, Seong-Ho Kim, Jin-Gi Hong, Hyeon-Deok Lee, Ho-Kyu Kang, Sang-In Lee, and Moon Yong Lee, Samsung Electronics Co, Korea, “A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device,” Jpn. J. Appl. Phys. Vol. 39 (2000), Part 1, No. 7A, July 2000, pp. 3924-3929 (survey 22)
12. Juseon Goo, Eunkee Hong, Hong-Gun Kim, Hyun Jo Kim, Eun Kyung Baek, Sun-Hoo Park, Jubum Lee, Hyeon Deok Lee, Ho-Hyu Kang, Joo-Tae Moon, Samsung Electronics Co., Korea, “A Highly Manufacturable, Low-Thermal Budget, Void and Seam Free Pre-Metal-Dielectric Process Using New SOG for beyond 60nm DRAM and Other Devices,” 2001, IEEE, IEDM 01-271 pp271-274 (survey 23)
13. Jung-Ho Lee, Jung-Sik Choi, Dong-Jun Lee, Sang-Moon Chon, Sun-Sam Hwang, Sang-Deog Cho, Samsung Electronics Co., Korea, “A Study on ILD Process of Simple and CMP Skip using Polysilazane-based SOG,” 2001 IEEE (survey 31)
14. Jin-Hwa Heo, Soo-Jin Hong, Dong-Ho Ahn, Hyun-Duk Cho, Moon-Han Park, Kazuyuki Fujihara, U-In Chung, Yong-Chul Oh and Joo-Tae Moon, Samsung Electronics Co, Korea, “Void Free and Low Stress Shallow Trench Isolation Technology using P-SOG for sub 0.1um Devuce,” 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 132-133 (survey 24)
15. Zhongtao Li, Xiaobing Zhou, Dave Wyman, Mike Spaulding, Ginam Kim, Stelian Grigoras, DK Choi, and Eric Moyer, Dow Corning Corp., U.S.A., “Development of Spin-On Pre Metal Dielectrics (PMD) for 0.10um Design Rule and Beyond,” 2002 Mat. Res. Soc. Symp. Proc. Vol 716 pp. B7.10.1-.6 (survey 15)
16. L.E. Stillwagon and R.G. Larson, AT&T Bell Laboratories, U.S.A., “Planarization during spin coating,” Phys. Fluids A 4 (5), May 1992, pp. 895-903
17. L.E. Stillwagon and R.G. Larson, AT&T Bell Laboratories, U.S.A., “Leveling of thin films over uneven substrates during spin coating.” Phys. Fluids A 2 (11) November 1990, pp. 1937-1944
18. Loni M. Peurrung and David B. Graves, UC Berkeley, U.S.A., “Spin Coating Over Topography,” IEEE Trans. on Semi. Manufacturing, VOL 6, No. 1, Feb. 1993, pp. 72-76
19. S. Hirasawa, Y. Saito, H. Nezu, N. Ohashi, H. Maruyama, Hitachi Limited, Japan, “Analysis of Drying Shrinkage and Flow due to Surface Tension of Spin-Coated Films on Grooved Substrates,” HTD-Vol. 336/FED-Vol. 240, Transport Phenomena in Materials Processing and Manufacturing, ASME 1996 pp. 221-226 (Note: This work also published in IEEE Trans. on Semi. Manuf. Vol. 10, No. 4, Nov. 1997, pp. 438-444)
20. W. Cai, T. Batchelder, Fairchild Technologies Corp.; J. Kennedy, AlliedSignal Corp., U.S.A., “Wafer Planarization with Low-k Spin-Coated Films,” Semiconductor International, June 1997, pp. 117-120
57
21. S.S. Kucherenko and K. D. Leaver, Imperial College, UK, “Modeling effects of surface tension on surface topology in spin coatings for integrated optics and micromechanics,” J. Micromech. Microeng. 10 (2000) pp. 299-308
22. E. Gurer, T. Zhong, J. Lewellen, E. Lee, Silicon Valley Group, U.S.A, “A novel spin coating technology for 248nm/193nm DUV lithography and low-k spin on dielectrics of 200/300mm wafers,” Advances in Resist Technology and Processing XVII, Francis M. Houlihan, Editor, Proceedings of SPIE Vol. 3999 (2000), pp. 805-817
23. D.E. Haas, D.P. Birnie, III, University of Arizona; M. J. Zecchino, J.T. Figueroa, Veeco Metrology Group, U.S.A., “The effect of radial position and spin speed on striation spacing in spin on glass coatings,” J. of Mat. Science Let. 20, 2001, pp. 1763-1766
58
3 Experimental Plan and Results
3.1 Introduction
This work was carried out to provide a baseline of empirical results to help guide
development of planarity simulation models. The samples were created on 200 mm
silicon wafers. The step in the silicon was created using spaced features in groupings
defined as quadrants in the region to be evaluated. The idea was to provide a macro-level
representation of semiconductor chip features to be planarized. The first objective was
to understand the limitations of coating induced planarity as a function of fixed step
height and variable spacing on a micrometer scale. For this case, the step height was 1.4
microns and the spaces were from the smallest of 1 micron to the largest of 1000
microns. Two different spin-on-dielectric (SOD) materials were used for this study:
SOD1, containing solids of hydrogen-silsesquioxane and SOD2, containing solids of
poly-silazane. Both are commercially available materials.
3.2 Experimental
The wafers were prepared in a manner consistent with semiconductor photo and dry
etching technologies. The step height was measured using a Tencor model P-20H
surface profiler. The instrument uses a stylus to collect z-axis changes at fixed intervals
during a linear scan. Each scan results in from 900 to near 2000 pairs of X and Z data
pairs that are then used to represent the cross-sectional surface profile of the area of
interest. Prior to saving the raw data, a leveling algorithm is used in the P-20H software
to normalize all z-axis values consistent with a selected pair of regions expected to be at
the same z-axis position. The samples were then spin coated with the SOD material of
choice (Table 3-1). A dispense volume of 2 cc was used with casting RPM in the range
of 1000 to 4000. After spin dry, the wafers are processed through the appropriate hot
59
plate conditions to remove solvents and cross-link the polymers as appropriate. The
samples were then scanned again using the P-20H. Collected z-axis results are leveled
using the same method as used for the pre-coat step profiles using regions expected to be
level in reference to the z-axis. For example, from other work, it is known that features
with a width greater than, say, 500 microns will tend to have a final thickness near that of
an un-patterned wafer.
Table 3-1: Sample Treatment
Material Sample (date)
Nominal Step
Casting RPM
Spread/Stop Step
(seconds)
Bare Thickness Average/%σ (Angstroms)
SOD1 7114_03 (3-26-03)
1.4 µm 1000 5/90 ~11600
SOD1 7114_08 (3-15-03) 1.4 µm 1000 3/0 11195/0.88%
SOD1 7114_09 (3-15-03) 1.4 µm 2000 3/0 7685/0.43%
3.3 Test Pattern Layout The test pattern is laid out as shown in Figure 3-1. Each of the 4 quadrants is identical.
The dashed outline represents the extents of the pattern. This pattern is repeated many
times across the wafer surface.
Quadrant I Quadrant II
Quadrant III Quadrant IV
60
Figure 3-1: Test Pattern Schematic - Quadrant Position
Each quadrant has two halves with mirror symmetry as shown in Figure 3-2. The overall
layout has vertical and horizontal symmetry. The dark circles ( ) indicate locations of
interest for global planarity while the open arrows ( ) represent typical locations
used for surface profile scans.
Figure 3-2: Test Pattern Schematic - Quadrant Spacing Dimensions
The final structural details are shown through the combination of Figure 3-3 and Figure
3-4. The smallest islands for this test pattern are the 60 by 90 micron rectangles and the
smallest spaces are 1 micron. This layout permits comparison of the fill character of
progressively smaller spaces with large islands. Because of the radial nature of the
centrifugal forces, it is also possible to study effects of spreading through ninety degrees
of symmetry. The next phase of work is intended to address equal space and island
features. The features described here will be used to feed inputs to the initial planarity
models.
1000
650
990
3600
170
LOW
HIGH
All dimensions in microns
61
Figure 3-3: Test Pattern Schematic - Quadrant Detail
Figure 3-4: Test Pattern Schematic - Minimum Feature Detail
90
60
1
21
HIG1
See following figure for inset detail
62
3.4 Experimental Results
Three wafers were coated and hot plate baked prior to being measured. Two samples
used a typical spin-coat method and one used a method that employs a short stop after the
initial spread of the material. The results for the typical spin-coat are reported here. The
nominal film thickness for all samples was on the order of 7 to 12 thousand angstroms.
The data is reported in two parts: optical and surface profile.
3.4.1 Optical Results The optical measurements were made using the Optiprobe multi-wavelength system from
ThermaWave Inc. The measurements were made using a 30 micron or 1 um spot size.
Because of the large (i.e. compared to the 1 um spot option) spot size, the goodness of fit
(GOF) value for measurements made with the 30 um spot is an indicator of the surface
slope across the measurement spot. This effect was observed and is reported here.
Figure 3-5: Optical microscope example of measurement points
Because of the color fringes and the need to measure within the 20 micron space, the 1
um spot was used to measure at the sites indicated by red spots in Figure 3-5. To
63
represent the global height, the measured thickness was added to the silicon reference.
The result is shown in Figure 3-6 where the bars are a schematic representation of the
silicon islands. For comparison, the same measurement scheme was used to examine the
global planarity from one pattern to the next. This is shown in Figure 3-7 and reflects
similar results though the space between quadrants is 400 microns less. Subsequent
surface profile results support the minima and maxima relation shown by the optical
readings.
7114_08 HSQ-type SOD 1.4um Step 11195A Bare Test Wafer Thickness
0
5000
10000
15000
20000
25000
30000
-5.3
2-5
.27
-5.2
1-5
.16
-5.1
0-5
.05
-4.9
9-4
.92
-4.7
4-4
.45
-4.2
5-3
.97
-3.8
9-3
.84
-3.7
8-3
.72
-3.6
7-3
.61
-3.5
6
X Position (mm)
Ang
stro
ms
Figure 3-6: Optical measurements 7114_08 quadrant I to quadrant II (same pattern)
64
7114_08 HSQ-type SOD1.4um Step 11195A Bare Test Wafer Thickness
0
5000
10000
15000
20000
25000
30000
-0.7
1-0
.65
-0.5
9-0
.54
-0.4
8-0
.42
-0.3
7-0
.30
-0.0
60.
250.
320.
370.
430.
490.
540.
600.
65
X position (mm)
Angs
trom
s
Figure 3-7: Optical measurements for 7114_08 quadrant II to quadrant I (next pattern)
The next example shows the GOF decrease as the slope of the SOD surface changes. The
measurement point schematic and optical view are shown in Figure 3-8. The color
fringes were used as a general guide to select points that would have either a flat or
sloped surface.
Figure 3-8: Measurement sites for GOF measurements
The thickness measurement results are shown in Figure 3-9. The open squares indicate
the optical SOD thickness added to the silicon height while the closed diamonds indicate
the optical thickness of SOD only. The open squares show the expected surface profile
over the silicon step.
65
7114 08: Step Planarity by Optical Measurement
0
5000
10000
15000
20000
25000
30000
-1.08 -1.06 -1.04 -1.02 -1 -0.98 -0.96 -0.94
Y Position (mm)
Ang
stro
ms
SOD THKSOD+Si Step
Figure 3-9: Step planarity by optical measurement
When the GOF is plotted as a function of the Y position (Figure 3-10) it is clear that the
surface curvature can be approximated by the GOF value. This could be a useful means
of quickly approximating local slope without contact profiling.
7114 08: Large Spot GOF by Position
0.20.30.4
0.50.60.70.8
0.91
-1.08 -1.06 -1.04 -1.02 -1 -0.98 -0.96 -0.94
Y Position (mm)
G.O
.F.
Figure 3-10: Large spot GOF by position
Sample 7114 09 and 08 can be compared to examine the effect of increased casting RPM
to decrease nominal thickness. The measurements are shown in Figure 3-11 and clearly
indicate that the approximately 7600 angstroms un-patterned thickness is not sufficient to
fill the 20 micron spaces between silicon islands. The combined results of 08 and 09 will
66
be used to calculate the thickness required to achieve 100 percent fill in the 20, 600, and
1000 micron spaces. The combined results are shown in Figure 3-12. Notice that the
difference in thickness between silicon islands (i.e. the 20 µm spaces) is greater than the
difference on top of islands. Note also that the thickness difference in the 600 µm space
is essentially the bare wafer thickness difference. This phenomenon can be thought of as
the planarity efficiency as a function of space and bare wafer thickness for a given step
height.
7114_09 HSQ-type SOD1.4um step 7685A Bare Test Wafer Thickness
0
5000
10000
15000
20000
25000
-0.7
1-0
.65
-0.6
0-0
.54
-0.4
9-0
.43
-0.3
8-0
.31
-0.2
6-0
.04
0.23
0.31
0.37
0.42
0.48
0.54
0.59
0.64
X position (mm)
Angs
trom
s
Figure 3-11: Optical measurements for 7114_09 quadrant II to quadrant I (next pattern)
Global Planarity: 7114 08 vs. 09
05000
1000015000200002500030000
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8X position (mm)
Ang
stro
ms
7114_09 7114_08
Figure 3-12: Optical measurements for 7114 08 vs. 09 quadrant II to quadrant I (next pattern)
67
The data for sample 08 and 09 are compared using three criteria: percent fill of the 1.4 m
step; percentage of test wafer thickness; fill efficiency. The most common approach is to
fill just above the step and then use chemical mechanical polish (CMP) to achieve global
planarity. The results in Figure 3-13 show that targeting 7685 Å for un-patterned (i.e.
bare) test wafer thickness is not quite sufficient to completely (i.e. 100 %) fill the 20 µm
space.
Step Fill for 7114 08 and 09(bare TW shown at X=0)
40.060.080.0
100.0120.0140.0160.0
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8X position (mm)
Perc
ent
7114 09 7114 08 09 TW 08 TW
Figure 3-13: Percent Fill 7114 08 vs. 09
The second comparison is to examine the test pattern measurements as a percentage of
the bare test wafer thickness. This method shows that the optical thickness values
generally match the bare test wafer values in the large 600 µm space while the 20 µm
spaces fill to 65 to 75 percent more.
68
Percent of Test Wafer for 7114 08 and 09
60.080.0
100.0120.0140.0160.0180.0200.0
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8X position (mm)
Perc
ent
7114 09 7114 08
Figure 3-14: Percent of Test Wafer for 7114 08 and 09
The fill efficiency can then be described by expressing the test wafer thickness as a
percent of the step to be planarized and plotting it against the percent fill in the space of
interest. This result is shown in Figure 3-15. The initial data suggests that the gap would
have been completely filled with a test wafer thickness of 57 to 58 percent of the step.
The data for the 600 um space shows that the fill is essentially the bare test wafer
thickness using any of the three comparison methods. This suggests that there is a
threshold at which the amount of fill begins to exceed the bare wafer coat thickness.
Fill Efficiency for 20 um Gap and 1.4 um Step
70.080.090.0
100.0110.0120.0130.0140.0150.0
40 50 60 70 80 90Test Wafer Thickness as Percent of Step
Fill
Perc
ent o
f Ste
p
7685 A11195 A
Figure 3-15: Fill Efficiency for 20 µm gap 7500 Å and 11000 Å nominal
69
The uniformity from top to bottom and left to right of a quadrant is shown in Figure 3-16
with locations as shown previously in Figure 3-3. The sites in quadrant II are represented
by L-RQ, C-RQ and R-RQ labels on x-axis. The data above label R-LQ would then
represent the right side of quadrant I. The data are in reasonable agreement.
7114 08 Global Points (Measured SOD)
105001070010900111001130011500117001190012100
R-LQ L-RQ C-RQ R-RQ
Agns
trom
s
TOPMIDBOT
Figure 3-16: 7114 08 within quadrant uniformity
Assessment of global uniformity continues with measurements of the right side of 7114
08 quadrant I at a site near the center of the wafer. Consistent with prior measurements,
this is done on the top of silicon islands and in the gaps between at top, middle and
bottom of the quadrant section. The results are shown in Figure 3-17. The 14,000 Å
nominal steps are reduced to 5637 Å on average for the 20 µm gap. Measurements made
in the adjacent 1000 µm gap show 10 kÅ to 11 kÅ readings that are consistent with the
bare test wafer value. This finding suggests that for a 14kÅ step, a layout rule requiring
all gaps to be 20 µm or less would permit significant global planarity gain with a single
coat of about 11 kÅ. By comparison, the 7.5 kÅ sample (Figure 3-12) did not quite fill
the gaps to the top of the step and only reduced planarity to a 10 kÅ step.
70
7114 08 Global Uniformity(Right Side of Quadrant)
18000190002000021000220002300024000250002600027000
1 2 3 4 5 6 7Measurement Site(2,4,6 are in gaps)
Ang
stro
ms
(SO
D +
Si)
TOPCTRBOT
Figure 3-17: 7114 08 global uniformity right side of quadrant
3.4.2 Surface Profile Results The previously reviewed optical results were then cross-checked with surface profile
measurements. The horizontal resolution is approximately 1 µm per x-scan increment.
The samples were profiled in left center and top locations to measure centrifugal
spreading effects relative to orientation of the test structure features. The scan data peaks
and valleys (Figure 3-18) appear to be in general agreement with the optical results taken
in the vicinity of the same regions. The pattern recognition algorithm was not always
accurate so all scans did not include two quadrants as can be seen in Figure 3-18. The
previously reviewed optical results suggest that the apparent upward trend in peaks and
valleys is most likely a result of the metrology over such a long scan distance. The
leveling algorithm is generally effective but does not remove the entire systematic slope.
71
7114_03 Scan 1: Complete
02000400060008000
1000012000140001600018000
0 200 400 600 800 1000 1200x axis scan increment
z ax
is d
imen
sion
Figure 3-18: 7114_03 scan 1 complete
Individual segments were selected to permit fitting of a second order polynomial for
more direct comparison of surface curvature. The segments were selected to be over the
90 µm wide silicon islands. For sample 7114_03 and 7114_0, each full scan and segment
analysis is shown. These are presented in Figure 3-20 through Figure 3-29.
7114_03 Scan 1: Segment 300-600
02000400060008000
1000012000140001600018000
300 350 400 450 500 550 600x axis scan increment
z ax
is d
imen
sion
Figure 3-19: 7114 03 scan 1 segment 300 to 600
The crown over the first two islands (Figure 3-19) is selected for initial fitting (Figure
3-20) so that the transition from positive to negative curvature does not yet need to be
considered. Were line and space to be the same, it is expected that a simple sinusoid
could be considered.
72
7114_03 Scan 1: Segment 300-600
y = -2.5201x2 + 2053.7x - 402808R2 = 0.976
y = -2.1286x2 + 2203x - 554537R2 = 0.9678
10000
11000
12000
13000
14000
15000
16000
17000
18000
350 400 450 500 550 600x axis scan increment
z ax
is d
imen
sion
Figure 3-20: 7114_03 Scan 1 segment 350 to 600
7114_03 Scan 2: Complete
0
5000
10000
15000
20000
0 200 400 600 800 1000 1200x-axis scan increment
z-ax
is d
imen
sion
Figure 3-21: 7114_03 Scan 2 complete
73
7114_03 Scan 2: 700 to 950 Segment
y = -2.5903x2 + 4051.4x - 2E+06R2 = 0.9826
y = -2.043x2 + 3629.6x - 2E+06R2 = 0.9883
10000
11000
12000
13000
14000
15000
16000
17000
18000
700 750 800 850 900 950x-axis scan increment
z-ax
is d
imen
sion
Figure 3-22: 7114_03 Scan 2 segment 700 to 950
7114_03 Scan 3: Complete
0
5000
10000
15000
20000
0 200 400 600 800 1000 1200x-axis scan increment
z-ax
is d
imen
sion
Figure 3-23: 7114_03 Scan 3 complete
74
7114_03 Scan 3: Segments
y = -2.6778x2 + 4149.8x - 2E+06R2 = 0.9784
y = -1.8536x2 + 3268.4x - 1E+06R2 = 0.9437
10000
11000
12000
13000
14000
15000
16000
17000
18000
700 750 800 850 900 950x-axis scan increment
z-ax
is d
imen
sion
Figure 3-24: 7114_03 Scan 3 segment 700 to 950
Fit equations of sample 7114 03 show (Table 3-2) reasonable agreement for all three
coefficients.
Table 3-2: 7114 03 fit equation summary
Scan First Island Second Island 1 y = -2.5201x2 + 2053.7x - 402808 R2 = 0.976 y = -2.1286x2 + 2203x - 554537 R2 = 0.968
2 y = -2.5903x2 + 4051.4x - 2E+06 R2 = 0.983 y = -2.043x2 + 3629.6x - 2E+06 R2 = 0.988
3 y = -2.6778x2 + 4149.8x - 2E+06 R2 = 0.9784 y = -1.8536x2 + 3268.4x - 1E+06 R2 = 0.944
The first scan of 7114 08 failed to capture the pattern correctly and therefore is not
included in the analysis. The scan 1 result is shown (Figure 3-25) for the record.
75
7114 08 Scan 1 Complete
17000
19000
21000
23000
25000
27000
0 200 400 600 800 1000 1200x-axis scan increment
z-ax
is d
imes
nion
Figure 3-25: 7114 08 scan 1 complete
7114_08 Scan 2: Complete
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
0 200 400 600 800 1000 1200x-axis scan increment
z-ax
is d
imen
sion
Figure 3-26: 7114_08 Scan 2 Complete
76
7114_08 Scan 2: Segment 750 to 1000
y = -2.9962x2 + 4990.2x - 2E+06R2 = 0.9883
y = -2.2505x2 + 4236x - 2E+06R2 = 0.9814
10000
11000
12000
13000
14000
15000
16000
17000
18000
750 800 850 900 950 1000x-axis scan increment
z-ax
is d
imen
sion
Figure 3-27: 7114_08 Scan 2 segment 750 to 1000
7114_08 Scan 3: Complete
02000400060008000
1000012000140001600018000
0 200 400 600 800 1000 1200x-axis scan increment
z-ax
is d
imen
sion
Figure 3-28: 7114_08 Scan 3 Complete
77
7114_08 Scan 3: Segment 750 to 1000
y = -2.7452x2 + 4516x - 2E+06R2 = 0.9739
y = -1.9151x2 + 3564.7x - 2E+06R2 = 0.9829
10000
11000
12000
13000
14000
15000
16000
17000
18000
750 800 850 900 950 1000x-axis scan increment
z-ax
is d
imen
sion
Figure 3-29: 7114_08 Scan 3 segment 750 to 1000
Table 3-3: 7114 08 fit equation summary
Scan First Island Second Island 1 not available not available
2 y = -2.9962x2 + 4990.2x - 2E+06 R2 = 0.988 y = -2.2505x2 + 4236x - 2E+06 R2 = 0.981
3 y = -2.7452x2 + 4516x - 2E+06 R2 = 0.974 y = -1.9151x2 + 3564.7x - 2E+06 R2 = 0.983
The results can be put in perspective by taking a small section such that one can get a
better sense of the relative scale of the z and x distances. The x-scan increment is
approximately 1 micron. The z-axis dimension can be converted to microns. This
relation for a small portion of 7114 03 scan 3 is shown in Figure 3-30 along with the
linear fit result. A sinusoidal shape can also be seen even though the r-squared value is
high. This segment represents the right hand side of the right curve of Figure 3-24.
78
7114_03 Scan 3: Segment 886 to 926
y = -0.0092x + 9.8501R2 = 0.9444
1
1.2
1.4
1.6
1.8
880
885
890
895
900
905
910
915
920
925
930
x-axis scan increment (~um)
y-ax
is d
imen
sion
(um
)
Figure 3-30: 7114 03 scan 3 segment 886 to 926 linear fit
The sinusoidal nature may be a result of how the stylus moves across the surface of the
SOD material. Related SEM section and AFM work does not indicate that the surface
actually has this type of shape. The P-20h stylus cannot fit into the 1 micron space
between the 60 by 90 micron mesa regions so AFM was used to determine the degree of
planarity in the 1 micron region. Two regions of the gap were scanned to permit
comparison at edge of gap and near center of the cap (i.e. 45 microns from each edge).
The sample was selected from a region near the center of the wafer such that centripetal
forces to maintain the material in a circular path would be very low as would the apparent
centrifugal force. The scan data was then sectioned in three places to compare the degree
of planarity (Figure 3-31).
79
Figure 3-31: 7114_08 AFM Analysis Locations
21 um
80
The markers permit comparison of two horizontal and vertical positions along the scan
line selected. The step height results for the edge and center of feature are shown in
Figure 3-32 and Figure 3-33. The section analysis at the edge (Figure 3-32) shows both
increasing thickness over the step region, as expected from the long-scan P20h profiles,
and a nearly constant degree of planarity for the gap region.
Figure 3-32: 7114_08 AFM scan line vertical step at edge of feature
Edge 1
Edge 3
Edge 2
81
The analysis in the middle of the feature (Figure 3-33) shows an improvement in the
degree of planarity and clear symmetry about the center scan. The step at the surface is
reduced by nearly 30 nm.
Figure 3-33: 7114_08 AFM scan line vertical results at center of feature
Center 2
Center 3
Center 1
82
The combined results in order from edge scan inward are shown in Table 3-4. This
shows the nearly 30 nm step height reduction that translates to about 2 percentage points
of planarity improvement.
Table 3-4: 7114_08 Planarity as function of feature position
Scan Wafer Center Vertical Step
Wafer Center Percent Planarity
Edge 1 107.8 92.81 Edge 2 117.2 92.19 Edge 3 113.9 92.41
Center 1 84.5 94.37 Center 2 85.3 94.31 Center 3 86.9 94.21
The final AFM comparison is to examine the profile across the 21 micron gap for
comparison to the P-20h profile results. The scan area is shown in Figure 3-34 and
reflects a shape similar to the one indicated by P-20h profile (Figure 3-35).
83
Figure 3-34: 7114_08 AFM scan of 21 micron gap
7114_08 Scan 2: Segment 750 to 1000
8000
10000
12000
14000
16000
18000
840 850 860 870 880 890 900 910 920x-axis scan increment
z-ax
is d
imen
sion
Figure 3-35: 7114_08 P-20h scan for AFM comparison
Indication of smooth surface
84
4 Conclusions and Model Development
4.1 Conclusions Review of the literature supports the value of developing a robust planarity model for
complex structures and a variety of material parameters. Study to date of the
planarization character of SOD supports the following points. Optical measurement can
be used to estimate surface curvature consistent with the color fringes observed using an
optical microscope. AFM and contact stylus surface profiling techniques have been
shown to have sufficient overlap in useful distance scale to determine both local and
global planarity in a non-destructive way. The combined results of optical thickness
measurement and surface profile measurement show that the characteristic planarity as a
result of applying SOD material to a topography pattern has symmetry that will permit
useful modeling of short range curvature. Though the initial intent was to develop and
rationalize a modeling approach for both the small feature effect and planarity, it became
clear that one needed to be selected for this portion of the work. Some of the ideas
presented along the journey were not closed as part of this work. They remain as
valuable ideas that may enter again as avenues to expand upon.
This work justifies continuation of effort to develop a planarity model followed by a
model to explain the small feature effect. It is likely that mechanisms that explain
portions of planarity will give insight to the small feature effect. Hence, the motivation
to recommend developing the planarity model first.
4.2 Model Development Plan Model development will be completed using COMSOL’s FEMLABTM 3.0 software. The
following is taken from introductory notes provided by application specialist Leigh
Soutter in private communication.
85
The finite element method (FEM) is a numerical method designed to estimate the solution of a PDE (partial differential equation) by solving a system of equations that closely approximates the PDE. The first step in FEM, is to define an integral equation that will approximate the PDE. The second step is to choose the type of function of "basis function" that will be used to transfer the integral approximation to each location in the model domain. Next, the geometry to be analyzed is discretized, creating a mesh of elements with a characteristic shape. The integral approximations (including boundary conditions) are applied to all locations on the mesh. In this way, the PDE is replaced by a system of equations, which is solved at each time step.
From the previous literature reviews, the initial models will be derived from the
approaches taken by Stillwagon and Larson1,2, Peurrung and Graves3, as well as the
benchmark work of Washo4. The first model will demonstrate ability to predict blanket
wafer coating thickness for given material and coater input parameters. The second
model will predict local planarity for various gap features. The final model objective is
to predict both local and global planarity for combinations of gap features. The model
results will be presented as part of a planned Dissertation on the same topic.
86
4.3 Section 4 Notes
1. L.E. Stillwagon and R.G. Larson, AT&T Bell Laboratories, U.S.A., “Planarization during spin coating,” Phys. Fluids A 4 (5), May 1992, pp. 895-903
2. L.E. Stillwagon and R.G. Larson, AT&T Bell Laboratories, U.S.A., “Leveling of thin films over uneven substrates during spin coating.” Phys. Fluids A 2 (11) November 1990, pp. 1937-1944
3. Loni M. Peurrung and David B. Graves, UC Berkeley, U.S.A., “Spin Coating Over Topography,” IEEE Trans. on Semi. Manufacturing, VOL 6, No. 1, Feb. 1993, pp. 72-76
4. B.D. Washo, IBM, U.S.A., “Rheology and Modeling of the Spin Coating Process”, IBM J. Res. Develop., March 1977, pp. 190-198
87
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