Sequential Statements

Osman Hasan

COEN 313

COEN 313: Sequential Statements

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Outline

VHDL process Sequential signal assignment statement Variable assignment statement

If statement

COEN 313: Sequential Statements

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VHDL Process Group of Instructions that are executed sequentially

Syntaxprocess declarations;begin sequential statement; sequential statement; . . .end process;

The whole process is a concurrent statement

COEN 313: Sequential Statements

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VHDL Process - Types With Sensitivity list

Process (sensitivity list) declarations;begin sequential statement; sequential statement; . . .end process;

A process is activated when a signal in the sensitivity list changes its value

Example: 3 input AND gatesignal a,b,c,y: std_logic;

process(a,b,c)begin y <= a and b and c;end process;

What happens if a is removed from the sensitivity list?

COEN 313: Sequential Statements

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VHDL Process - Types With Wait statement

Process declarations;begin sequential statement; sequential statement;

wait on signals . . .end process;

No sensitivity list Process continues the execution until a wait

statement is reached and then suspended

Example: 3 input AND gateprocessbegin y <= a and b and c; wait on a, b, c; end process;

COEN 313: Sequential Statements

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Points to Remember

A process may or may not be mapped to physical hardware

For a combinational circuit, all inputs should be included in the sensitivity list

Process with sensitivity list is preferred for synthesis

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Sequential signal assignment statement Identical to the simple concurrent signal

assignment Syntax : signal_name <= value_expression; Inside a process, a signal can be assigned multiple

times, but only the last assignment takes effect

Example: process(a,b,c,d)begin -- yentry := y y <= a or c; -- yexit := a or c; y <= a and b; -- yexit := a and b; y <= c and d; -- yexit := c and d;end process; -- y <= yexit

Example: process(a,b,c,d)begin y <= c and d;end process;

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Variable assignment statement Like variables in C/C++ Syntax : variable_name := value_expression; Assignment takes effect immediately

What happens if := is replaced with <=

Example: process(a,b,c) variable tmp: std_logic;begin tmp := '0'; tmp := tmp or a; tmp := tmp or b; y <= tmp;end process;

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Quiz 1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY sig_ass IS END ENTITY;

ARCHITECTURE beh OF sig_ass IS SIGNAL sum1,sum2 : INTEGER := 0;

BEGIN p0: PROCESS BEGIN WAIT FOR 10 ns; sum1 <= sum1 + 1; sum2 <= sum1 + 1; END PROCESS; END beh;

Time sum sum20

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10 + 1 Δ

20 + 1 Δ

30 + 1 Δ

20

30

0 0

0 0

1 1

1 1

2 2

3 3

2 2

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Quiz 2 ENTITY and_or IS PORT ( a,b,c,d : IN STD_LOGIC; output : OUT STD_ULOGIC);END ENTITY;

ARCHITECTURE beh OF and_or IS SIGNAL x,y : STD_LOGIC;

BEGINmy_process : PROCESS (a,b,c,d) BEGIN x <= a OR b; y <= c OR d; output <= x AND y; END PROCESS;END beh;

•Signals are updated at the end of a process.

•If a process is reading the value of signal, it will read the old (non-updated) value!

•How to Solve this Bug!

COEN 313: Sequential Statements

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Outline

VHDL process Sequential signal assignment statement Variable assignment statement

If statement

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If Statement Sequential Conditional Statement in VHDL Syntax

if boolean_expr_1 then sequential_statements;elsif boolean_expr_2 then sequential_statements;elsif boolean_expr_3 then sequential_statements;. . .else sequential_statements;end if;

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Example: 4x1 Mux

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Example: 2x4 Binary Decoder

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Example: 4-to-4 Priority Encoder

•4-to-2 priority encoder

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Last Quiz LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ARCHITECTURE beh OF mystery ISBEGIN p0: PROCESS (data_in1, select_in) BEGIN IF select_in = '0' THEN output <= data_in1; ELSE output <= data_in2; END IF; END PROCESS; END beh;