sequential logic

EE415 VLSI Design

Sequential LogicSequential Logic

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design

Project PresentationsWhat to include in presentation?•Reason for choosing the design•Final/Intended application•Design constraints•What it does/How it works•Simulations!, Simulations!!, Simulations!!!•Layout•Post-layout simulations!•Achieved goal? Unexpected glitches? Future work•Contrast proposed schedule with actual schedule

EE415 VLSI Design

Sequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

EE415 VLSI Design

Meta-Stability

Gain should be larger than 1 in the transition region

A

C

d

B

Vi2

5V

o1

Vi1 5Vo2

A

C

d

B

Vi2

5V

o1Vi1 5Vo2

EE415 VLSI Design

Mux-Based Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ

EE415 VLSI Design

Mux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks

D

EE415 VLSI Design

Mux-Based Latch

CLK

CLK

CLK

D

Q

EE415 VLSI Design

Writing into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

EE415 VLSI Design

Reduced Clock Load Master-Slave Register

D QT1 I1

CLK

CLK

T2

CLK

CLKI2

I3

I4

EE415 VLSI Design

Avoid Clock Overlap

CLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

EE415 VLSI Design

Storage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static

Very fast

Was popular, now too risky

EE415 VLSI Design

Making a Dynamic Latch Pseudo-Static

D

CLK

CLK

D

Weak inverter

EE415 VLSI Design

SR-Flip Flop

QS

R Q

S R Q Q

0101

0011

Q100

Q010

S

R

Q

Q

QS

R Q

S R Q Q

1010

1100

Q101

Q011

Forbidden State

Forbidden State

S Q

R Q

EE415 VLSI Design

Cross-Coupled NOR

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Cross-coupled NORsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

•Transistors M5-M8 are

wider to switch the state

SQ

RQ

EE415 VLSI Design

Sizing Issues

Output voltage dependence on transistor width

Transient responseFor various W/L 5 and 6

4.03.53.0W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q (

Vo

lts)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 m

3

Vo

lts

Q S

W = 0.9 m

W = 0.8 m

W = 0.7 mW = 0.6 m

W = 0.5 m

EE415 VLSI Design

Naming Conventions

In our text:» a latch is level sensitive» a register is edge-triggered

There are many different naming conventions» For instance, many books call edge-

triggered elements flip-flops» This leads to confusion however

EE415 VLSI Design

Latch versus Register

Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Register

stores data when clock rises

Clk Clk

D D

Q Q

Falls with data Falls with clock

EE415 VLSI Design

Latch-Based Design

• N latch is transparentwhen = 0

• P latch is transparent when = 1

NLatch

Logic

Logic

PLatch

EE415 VLSI Design

Master-Slave (Edge-Triggered) Register

Two opposite latches trigger on edgeAlso called master-slave latch pair

1

0D

CLK

QM

Master

0

1

CLK

Q

Slave

QM

Q

D

EE415 VLSI Design

Master-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair

EE415 VLSI Design

Timing Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q

Propagation delay time affects the clock period

Set-up and hold times are needed to produce a stable output

EE415 VLSI Design

Characterizing Timing

Register Latch

Clk

D Q

tC 2 Q

Clk

D Q

tC 2 Q

tD 2 Q

EE415 VLSI Design

Maximum Clock Frequency

FF

’s

LOGIC

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delaytclk-Q + tp,comb + tsetup =

T

Minimum clock perioddecides - the maximum operating frequency of a sequential circuit

EE415 VLSI Design

Clk-Q Delay

D

Q

CLK

2 0.5

0.5

1.5

2.5

tc2 q(lh)

0.5 1 1.5 2 2.50time, nsec

Volt

s

tc2 q(hl)

D

Clk

Q

EE415 VLSI Design

Timing of Master-Slave Register

In the multiplexer-based latch pairassume that propagation delays of inverters and transmission gates are tpd_inv and tpd_tx

The setup time states how long before the rising edge of CLK data D must be stable. D has to propagate through I1, T1, I3, and I4 before the rising edge of CLK, so tsetup=3 tpd_inv+tpd_tx

The propagation delay is the time to propagate signal from QM to Q. Since the output I4 is valid before the rising edge of the clock, so tc-

q=tpd_tx+tpd_inv

The hold time (time for the input to be stable after rising edge of the clock)is 0 since D and clock are delayed by the same amount before reaching the T1 gate, so a change of D after rising edge of the clock will reach T1 after it is shut down and will not affect its output.

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

EE415 VLSI Design

Setup Time

Output failure

D

Q

QM

CLK

I2 2 T2

2 0.5

Volt

s

0.0

0.2 0.4time (nsec)

(a) Tsetup5 0.21 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

DQ

QM

CLK

I2 2 T2

2 0.5V

olt

s

0.0

0.2 0.4time (nsec)

(b) Tsetup5 0.20 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

= =

EE415 VLSI Design

More Precise Setup Time

tD 2 C

t

t

t

tC 2 Q1.05tC 2 Q

tSu

tH

Clk

D

Q

Setup and hold times defined when delay increases by 5%

delay

EE415 VLSI Design

Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1

EE415 VLSI Design

Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataTSetup-1



D

CN

QM

CP

D1SM

Inv1

Inv2TG1

EE415 VLSI Design

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1



EE415 VLSI Design

Timet=0

ClockDataTSetup-1

D

CN

QM

CP

D1SM

Inv1

Inv2TG1



Clk-Q Delay

TSetup-1

TClk-Q

Time

EE415 VLSI Design


Hold-1 case

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1

0

Clk-Q Delay

THold-1

TClk-Q

Time

EE415 VLSI Design

Clk-Q Delay

THold-1

TClk-Q

Time

Timet=0

DataClockTHold-1


Hold-1 case

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

0

EE415 VLSI Design

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1


Hold-1 case

0

EE415 VLSI Design

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


Hold-1 case

0

EE415 VLSI Design

Other Latches/Registers: C2MOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

“Keepers” can be added to make circuit pseudo-static

EE415 VLSI Design

Insensitive to Clock-Overlap

timesametheatKLCandCLK 0

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

timesametheatKLCandCLK 1

EE415 VLSI Design

Other Latches/Registers: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

Only single phase clocks are used. When is high the latch is in the evaluate mode. When is low the latch is in hold-mode.

EE415 VLSI Design

Including Logic in TSPC

CLKIn CLK

VDDVDD

QPUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

AND latchExample: logic inside the latch

EE415 VLSI Design

TSPC Register

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4

EE415 VLSI Design

Master-Slave Flip-flops

VDD

D

VDD

VDD

D

VDD

VDD

D

VDD

D

VDD

VDD

D

VDD

D

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY

EE415 VLSI Design

Pulse-Triggered LatchesAn Alternative Approach

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

Need to generate the glitch pulse

EE415 VLSI Design

Pulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

XMP

MN

(a) register (b) glitch generation

EE415 VLSI Design

Pulsed Latches

Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2

EE415 VLSI Design

Hybrid Latch-FF Timing

20.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.20.0 0.4

QD

time (ns)

Vo

lts

0.6 0.8 1.0

CLKDCLK

Data not properly captured due to insufficient hold time

EE415 VLSI Design

PipeliningR

EG

RE

G

RE

G

log

a

CLK

CLK

CLK

Out

b

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

RE

G

CLK

RE

G

CLK

Out

b

Reference Pipelined

EE415 VLSI Design

Latch-Based Pipeline

F G

CLK

CLK

In Out

C1 C2

CLK

C3

CLK

CLK

Compute F compute G

EE415 VLSI Design

Non-Bistable Sequential Circuits─

Schmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes

EE415 VLSI Design

Noise Suppression using Schmitt Trigger

Vin

t0

VM

VM

t

Vout

t0 + tp t

EE415 VLSI Design

CMOS Schmitt Trigger

These transistors resist the change in the X signalMove switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3

EE415 VLSI Design

CMOS Schmitt Trigger

V DD

V in Vou t

M 1

M 2

M 3

M 4

X

Increasing kn/kp ratio decreases the logical switching threshold

If Vin=0 the Vout (connected to M4) is also zero So effectively the input is connected to M2 and M4 in parallelThis increases kp and the switching threshold

If Vin=0 the situation is reversed and kn increases reducing the switching threshold

EE415 VLSI Design

Schmitt Trigger Simulated VTC

2.5

Vout(V)

VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

Vout(V)

EE415 VLSI Design

CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6

With input low and output high X is charged to VDD –Vth M2 is cutoff until the input is larger than VX +Vth With output being pulled downM5 is cut off and the output transition is very rapidThis delays transition from high to low values on the output.Symmetrical analysis can be performed for low to high output transition

EE415 VLSI Design

Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

EE415 VLSI Design

Transition-Triggered Monostable

DELAY

td

In

Outtd

EE415 VLSI Design

Monostable Trigger (RC-based)

RC delay regulates the width of the generated pulse

VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.

EE415 VLSI Design

Astable Multivibrators (Oscillators)

0 1 2 N-1

0 1 2 3 4 5

t (nsec)

-1.0

1.0

3.0

5.0

V (

Vol

t)

V1V3 V5

Ring Oscillator

simulated response of 5-stage oscillator

EE415 VLSI Design

Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

EE415 VLSI Design

Voltage Controller Oscillator (VCO)

Current Iref is a quadratic function of Vcontr

This effects the delay time

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5V contr (V)

0.0

2

4

6

t pH

L (

n sec

)

propagation delay as a functionof control voltage

EE415 VLSI Design

Differential Delay Element and VCO

in2

two stage VCO

v1

v2

v3

v4

Vctrl

Vo2 Vo1

in1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

20.51.5

V1 V2 V3 V4

time (ns)2.5 3.5

EE415 VLSI Design

JK- Flip Flop

S

R

Q

Q Q

J

K

Jn Kn Qn+1

0

0

11

0

1

01

Qn

0

1Qn

(c)

Q

(a) QJ

K Q

(b)

Problem – if JK flip-flop in a toggle state (J=K=1) can flip againFor instance when Q=1, and J=K=1, then only R goes low andand Q changes to 0. If the clock is still high, the feedback disables K and enables J and FF changes its output again

For clock=0S=R=1 and FFmaintains its previous state

When J=K=1then S=Qand FF toggles

S R Q Q

1

0

10

1

1

00

Q

1

01

Q

0

11

EE415 VLSI Design

Other Flip-Flops

QJ

KQ

T

QJ

KQ

D

Q

Q

T Q

Q

D

Toggle Flip-Flop Delay Flip-Flop (D-latch)

EE415 VLSI Design

Race Problem

Q

Q

D

1

t

t

tloop

Signal can race around during = 1

EE415 VLSI Design

Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

MASTER SLAVE

QJ

K Q

PRESET

CLEAR

SI

RI

Master transmits the signal to the output during the high clock phase and slave is waiting for the clock to change this prevents race conditions

EE415 VLSI Design

Propagation Delay Based Edge-Trigger

In X

N2N1

Out

In

X

Out

tpLH

= Mono-Stable Multi-Vibrator

Circuit which produces a short output impulseused in edge triggered devices

EE415 VLSI Design

Edge Triggered Flip-Flop

S

R

Q

Q

Q

J

K

Q

QJ

KQ

No need for master-slave configuration

sequential logic

Documents