sequential digital design laboratory manual...
TRANSCRIPT
The Islamic University of Gaza
Engineering Faculty
Department of Computer Engineering
Spring 2018
ECOM 2022
Khaleel I. Shaheen
Sequential Digital Design
Laboratory Manual
Experiment #7
Counters
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Objectives
• To be familiar with different types of counters, and their design and applications.
Theoretical Background
Counters
A counter is a sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses. The input pulses (count pulses) of the counter is clock pulses, or
from some external source, and may occur at prescribed intervals of time or at random.
Counters can be classified into two broad categories according to the way they are clocked:
1. Asynchronous (ripple) counters: the first FF is clocked by the external clock pulse, and
then each successive FF is clocked by the Q or Q’ output of the previous FF.
2. Synchronous counters – all FFs are simultaneously triggered by the same clock.
The counter follows the binary number sequence or other sequence of states. A counter that
follows the binary sequence is called a binary counter. An n-bit binary counter consists of n flip-
flops and can count in binary from 0 to 2n-1.
First: Synchronous counters
If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a
counter is called as synchronous counter.
Binary Up Counter
It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to
each of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied
together in toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected
HIGH, logic “1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous
counter follows a predetermined sequence of states in response to the common clock signal,
advancing one state for each pulse.
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The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are
also supplied with signals from the input and output of the previous stage. These additional
AND gates generate the required logic for the JK inputs of the next stage.
Binary Down Counter
As well as counting “up” from zero and increasing or incrementing to some preset value, it is
sometimes necessary to count “down” from a predetermined value to zero allowing us to
produce an output that activates when the zero count or some other pre-set value is reached.
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Bidirectional Counters
Bidirectional counters are capable of counting in either the up direction or the down direction
through any given count sequence
Bidirectional counters, also known as Up/Down counters, are capable of counting in either
direction through any given count sequence and they can be reversed at any point within their
count sequence by using an additional control input as shown below.
Generally, most bidirectional counter chips can be made to change their count direction either
up or down at any point within their counting sequence. This is achieved by using an additional
input pin which determines the direction of the count, either Up or Down and the timing diagram
gives an example of the counters operation as this Up/Down input changes state.
BCD Counters
A 4-bit decade synchronous counter can also be built using synchronous binary counters to
produce a count sequence from 0 to 9. A standard binary counter can be converted to a
decade (decimal 10) counter with the aid of some additional logic to implement the desired
state sequence. After reaching the count of “1001”, the counter recycles back to “0000”. We
now have a decade or Modulo-10 counter.
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The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10) and
causes flip-flop FFD to toggle on the next clock pulse. Flip-flop FFA toggles on every clock pulse.
Thus, the count is reset and starts over again at “0000” producing a synchronous decade
counter.
We could quite easily re-arrange the additional AND gates in the above counter circuit to
produce other count numbers such as a Mod-12 counter which counts 12 states from ”0000″
to “1011” (0 to 11) and then repeats making them suitable for clocks, etc.
Ring counter
A ring counter is a type of counter composed of a circular shift register. The output of the last
shift register is fed to the input of the first register.
Johnson counter
Synchronous counter where the complement of the output of the last shift register is connected
to the input of the first register and circulates a stream of ones followed by zeros around the
ring as shown in the figure below.
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Second: Asynchronous (ripple) counters
Asynchronous Counters use flip-flops that are serially connected together so that the input
clock pulse ripples through the counter giving them the name of ripple counter.
Binary Ripple Counter
A binary ripple counter consists of a series connection of complementing flip flops, with the
output of each flip flop connected to the CLK input of the next higher order flip-flop. The flip
flop holding the least significant bit receives the incoming count pulses.
The logic diagram of a 3-bit ripple up counter is shown in figure. The toggle (T) flip-flop are
being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1
or using D flip-flop with input is connected to the complemented output. External clock is applied
to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop.
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Operation
Condition Operation
Initially all the FFs are in the reset state Q2Q1Q0 = 000 initially
After 1st negative clock edge As soon as the first negative clock edge is
applied, FF-0 will toggle and Q0 will be equal
to 1.
Q0 is connected to clock input of FF-1. Since
Q0 has changed from 0 to 1, it is treated as
the positive clock edge by FF-1. There is no
change in Q1 because FF-1 is a negative
edge triggered FF.
Q2Q1Q0 = 001 after the first clock pulse.
After 2nd negative clock edge On the arrival of second negative clock
edge, FF-0 toggles again and Q0 = 0.
The change in Q0 acts as a negative clock
edge for FF-1. So, it will also toggle, and Q1
will be 1.
Q2Q1Q0 = 010 after the second clock pulse.
After 3rd negative clock edge On the arrival of 3rd negative clock edge,
FF-A toggles again and Q0 become 1 from 0.
Since this is a positive going change, FF-1
does not respond to it and remains inactive.
So Q1 does not change and continues to be
equal to 1.
Q2Q1Q0 = 011 after the third clock pulse.
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BCD Ripple Counter (غير مطلوب)
A decimal counter follows a sequence of ten states and returns to 0 after the count of 9. Such
counter must have at least four flip-flops to represent each decimal digit, since a decimal digit
is represented by a binary code with at least four bits. The sequence of states in a decimal
counter is indicated by the binary code used to represent a decimal digit. If BCD is used, the
sequence of states is as shown in the state diagram in the figure. This is similar to a binary
counter, except that the state after 1001 (code for decimal 9) is 0000 (code for decimal 0).
The logic diagram of a BCD ripple counter is shown in figure 9.5. The four outputs are designed
by the letter symbol Q with a numeric subscript equal to the binary weight of the corresponding
bit in the BCD code. The flip-flops trigger on the negative edge. Note that the output Q1 is
applied to the Clk inputs of both Q2 and Q8 and the output of Q2 is applied to the Clk input of
Q4. The J and K inputs are connected either to a permanent 1 signal or to outputs of flip-flops,
as shown in the diagram.
The following are the conditions for each flip-flop state transition:
1. Q1 is complemented on the negative edge of every count pulse.
2. Q2 is complemented if Q8 = 0 and Q1 goes from 1 to 0.
Q2 is cleared if Q8 = 1 and Q1 goes from 1 to 0.
3. Q4 is complemented when Q2 goes from 1 to 0.
4. Q8 is complemented when Q4Q2 = 11 and Q1 goes from 1 to 0.
Q8 is cleared if either Q4 or Q2 is 0 and Q1 goes from 1 to 0.
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Other presentation of BCD ripple counter will be as follows:
1. We need four flip-flops, for example JK flip flops where J and K are high.
2. Count from 0-9, so when counter reaches 9 it will make the 10 to be 0.
3. Decimal 10 = (1010)2, clear = D C' B A'
4. Take ones as inputs of NAND and take output of NAND to CLR.
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Counter ICs
Synchronous Binary counter (74LS93)
Synchronous BCD counter with parallel load (74LS160)
Synchronous UP/Down BCD counter with parallel load (74LS190)
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Lab Work
Equipments required
• Circuit Wizard Simulation Software.
• KL-31001 trainer kit.
• IC 7404(NOT), IC 7408(AND), IC 7432(OR), IC 7400(NAND), IC 7402(NOR).
• Connecting wires and Breadboard.
• The Datasheets of the IC’s.
Implementation
Use Circuit Wizard to design, test and simulate the circuits in the examples above, then
implement the circuits practically in the laboratory.
Exercises:
1. Implement a ripple down counter from 15 to 0 using JK flip flops with negative edge
triggered.
2. Design the 74LS160 to count in the sequence (4,5,6,7,8).
Good Luck
😊