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ContentsArticles

Pulse-density modulation 1Delta-sigma modulation 4Current mirror 16Pulse-width modulation 24Smart transducer 31Translinear circuit 31

ReferencesArticle Sources and Contributors 35Image Sources, Licenses and Contributors 36

Article LicensesLicense 37

Pulse-density modulation 1

Pulse-density modulationPulse-density modulation, or PDM, is a form of modulation used to represent an analog signal with digital data. Ina PDM signal, specific amplitude values are not encoded into pulses of different size as they would be in PCM.Instead, it is the relative density of the pulses that corresponds to the analog signal's amplitude. Pulse-widthmodulation (PWM) is the special case of PDM where all the pulses corresponding to one sample are contiguous inthe digital signal.

DescriptionIn a pulse-density modulation bitstream a 1 corresponds to a pulse of positive polarity (+A) and a 0 corresponds to apulse of negative polarity (-A). Mathematically, this can be represented as:

where x[n] is the bipolar bitstream (either -A or +A) and a[n] is the corresponding binary bitstream (either 0 or1).

A run consisting of all 1s would correspond to the maximum (positive) amplitude value, all 0s would correspond tothe minimum (negative) amplitude value, and alternating 1s and 0s would correspond to a zero amplitude value. Thecontinuous amplitude waveform is recovered by low-pass filtering the bipolar PDM bitstream.

ExamplesA single period of the trigonometric sine function, sampled 100 times and represented as a PDM bitstream, is:0101011011110111111111111111111111011111101101101010100100100000010000000000000000000001000010010101

An example of PDM of 100 samples of one period a sine wave. 1s represented by blue, 0s represented by white, overlaid with the sinewave.

Two periods of a higher frequency sine wave would appear as:0101101111111111111101101010010000000000000100010011011101111111111111011010100100000000000000100101

or In pulse-density modulation, a high density of 1s occurs at the peaks of the sine wave, while a low density of 1soccurs at the troughs of the sine wave.

Analog-to-digital conversionA PDM bitstream is encoded from an analog signal through the process of delta-sigma modulation. This process usesa one bit quantizer that produces either a 1 or 0 depending on the amplitude of the analog signal. A 1 or 0corresponds to a signal that is all the way up or all the way down, respectively. Because in the real world analogsignals are rarely all the way in one direction there is a quantization error, the difference between the 1 or 0 and theactual amplitude it represents. This error is fed back negatively in the ΔΣ process loop. In this way every errorsuccessively influences every other quantization measurement and its error. This has the effect of averaging out thequantization error.

Pulse-density modulation 2

Digital-to-analog conversionThe process of decoding a PDM signal into an analog one is simple: one only has to pass the PDM signal through alow-pass filter. This works because the function of a low-pass filter is essentially to average the signal. The averageamplitude of pulses is measured by the density of those pulses over time, thus a low pass filter is the only steprequired in the decoding process.

Relationship to biologyNotably, one of the ways animal nervous systems represent sensory and other information is through rate codingwhereby the magnitude of the signal is related to the rate of firing of the sensory neuron. In direct analogy, eachneural event - called an action potential - represents one bit (pulse), with the rate of firing of the neuron representingthe pulse density.

Algorithm

Pulse-density modulation of a sine wave using this algorithm.

A digital model of pulse-density modulationcan be obtained from a digital model of thedelta-sigma modulator. Consider a signal

in the discrete time domain as theinput to a first-order delta-sigma modulator,with the output. In the discretefrequency domain, the delta-sigmamodulator's operation is represented by

Rearranging terms, we obtain

Here, is the frequency-domainquantization error of the delta-sigmamodulator. The factor representsa high-pass filter, so it is clear that contributes less to the output at low frequencies, and more at high frequencies. This demonstrates the noiseshaping effect of the delta-sigma modulator: the quantization noise is "pushed" out of the low frequencies up into thehigh-frequency range.Using the inverse Z-transform, we may convert this into a difference equation relating the input of the delta-sigmamodulator to its output in the discrete time domain,

There are two additional constraints to consider: first, at each step the output sample is chosen so as tominimize the "running" quantization error . Second, is represented as a single bit, meaning it can take ononly two values. We choose for convenience, allowing us to write

This, finally, gives a formula for the output sample in terms of the input sample . The quantization errorof each sample is fed back into the input for the following sample.

Pulse-density modulation 3

The following pseudo-code implements this algorithm to convert a pulse-code modulation signal into a PDM signal:

// Encode samples into pulse-density modulation

// using a first-order sigma-delta modulator

function pdm(real[0..s] x)

var int[0..s] y

var real[-1..s] qe

qe[-1] := 0 // initial running error is zero

for n from 0 to s

if x[n] >= qe[n-1]

y[n] := 1

else

y[n] := -1

qe[n] := y[n] - x[n] + qe[n-1]

return y, qe // return output and running error

ApplicationsPDM is the encoding used in Sony's Super Audio CD (SACD) format, under the name Direct Stream Digital.

External links• 1-bit A/D and D/A Converters [1] — Discusses delta modulation, PDM (also known as Sigma-delta modulation or

SDM), and relationships to Pulse-code modulation (PCM)

References[1] http:/ / www. cs. tut. fi/ sgn/ arg/ rosti/ 1-bit/

Delta-sigma modulation 4

Delta-sigma modulationDelta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding high-resolution or analog signals intolower-resolution digital signals. The conversion is done using error feedback, where the difference between the twosignals is measured and used to improve the conversion. The low-resolution signal typically changes more quicklythan the high-resolution signal and it can be filtered to recover the high-resolution signal with little or no loss offidelity. This technique has found increasing use in modern electronic components such as analog-to-digitalconverters (ADCs) and digital-to-analog converters (DACs), frequency synthesizers, switched-mode power suppliesand motor controllers.A very popular application of delta-sigma conversion is in audio applications where a digital audio signal, as from anMP3 player, is converted into the analog audio signal which will be amplified and output by speakers or headphones.Because most of the modulator is a digital circuit, it is cheap to construct. Since the output of this modulatortypically has only two levels, the generation of the analog output signal is power efficient. Further, because themodulator's output signal changes much faster than the desired audio signal, it can be heavily filtered and theresulting analog signal has high enough fidelity for use in professional applications.Low cost, low power, and high fidelity make delta-sigma modulators very popular.

Motivation

Why convert an analog signal into a stream of pulses?In brief, because it is very easy to regenerate pulses at the receiver into the ideal form transmitted. The only part ofthe transmitted waveform required at the receiver is the time at which the pulse occurred. Given the timinginformation the transmitted waveform can be reconstructed electronically with great precision. In contrast, withoutconversion to a pulse stream but simply transmitting the analog signal directly, all noise in the system is added to theanalog signal, reducing its quality.Each pulse is made up of a step up followed after a short interval by a step down. It is possible, even in the presenceof electronic noise, to recover the timing of these steps and from that regenerate the transmitted pulse stream almostnoiselessly. Then the accuracy of the transmission process reduces to the accuracy with which the transmitted pulsestream represents the input waveform.

Why delta-sigma modulation?Delta-sigma modulation converts the analog voltage into a pulse frequency and is alternatively known as PulseDensity modulation or Pulse Frequency modulation. In general, frequency may vary smoothly in infinitesimal steps,as may voltage, and both may serve as an analog of an infinitesimally varying physical variable such as acousticpressure, light intensity, etc. The substitution of frequency for voltage is thus entirely natural and carries in its trainthe transmission advantages of a pulse stream. The different names for the modulation method are the result of pulsefrequency modulation by different electronic implementations, which all produce similar transmitted waveforms.

Why use delta-sigma modulation on a CD?Delta-sigma modulation is unrelated to the physical encoding of a CD, DVD, or SACD. Digital data is physicallyrepresented as a transition (or not) between a light and dark reflection of the laser by the disc. The brightness of thereflected signal is converted using an analog to digital converter; the required rates of conversion make a delta-sigmaADC unsuitable. Once the physical data is recovered from the disc, the logical data is recovered using a number ofsteps, including error corrective coding. Audio data on a CD is logically encoded using PCM and so can easily beconverted into an audible analog signal using a variety of conversion methods, delta-sigma included.

Delta-sigma modulation 5

Why the delta-sigma analog to digital conversion?The ADC converts the mean of an analog voltage into the mean of an analog pulse frequency and counts the pulsesin an known interval so that the pulse count divided by the interval gives an accurate digital representation of themean analog voltage during the interval. This interval can be chosen to give any desired resolution or accuracy andthe method is cheaply produced by modern methods. Thus it is popular and widely used. ΣΔ is the mathematicalsymbol for the summation of delta pulses and is read sigma-delta.

Analog to digital conversion

DescriptionThe analog to digital converter, ADC, generates a pulse stream in which the frequency of pulses in the stream isproportional to the analog voltage input, , so that the frequency, where k is a constant for theparticular implementation.A counter sums the number of pulses that occur in a predetermined period, P so that the sum, , is

.is chosen so that a digital display of the count, , is a display of with a predetermined scaling factor.

Because may take any designed value it may be made large enough to give any desired resolution or accuracy.Each pulse of the pulse stream has a known, constant amplitude and duration , and thus has a known integral

but variable separating interval.In a formal analysis an impulse such as integral is treated as the Dirac δ (delta) function and is specified by the

step produced on integration. Here we indicate that step as .

The interval between pulses, p, is determined by a feedback loop arranged so that .

The action of the feedback loop is to monitor the integral of v and when that integral has incremented by , whichis indicated by the integral waveform crossing a threshold, then subtracting from the integral of v so that thecombined waveform sawtooths between the threshold and ( threshold - ). At each step a pulse is added to thepulse stream.

Between impulses the slope of the integral is proportional to . Whence

.It is the pulse stream which is transmitted for delta-sigma modulation but the pulses are counted to form sigma in thecase of analogue to digital conversion.

Delta-sigma modulation 6

Analysis

Fig. 1: Block diagram and waveforms for a sigma delta ADC.

Fig. 1a: Effect of clocking impulses

Shown below the block diagramillustrated in Fig. 1 are waveforms atpoints designated by numbers 1 to 5for an input of 0.2 volts on the left and0.4 volts on the right.In most practical applications thesumming interval is large comparedwith the impulse duration and forsignals which are a significant fractionof full scale the variable separatinginterval is also small compared withthe summing interval. TheNyquist–Shannon sampling theoremrequires two samples to render avarying input signal. The samplesappropriate to this criterion are twosuccessive Σ counts taken in twosuccessive summing intervals. Thesumming interval, which mustaccommodate a large count in order toachieve adequate precision, isinevitably long so that the convertercan only render relatively lowfrequencies. Hence it is convenient andfair to represent the input voltage (1) asconstant over a few impulses.

Consider first the waveforms on theleft.1 is the input and for this short intervalis constant at 0.2 V. The stream ofdelta impulses is shown at 2 and thedifference between 1 and 2 is shown at3. This difference is integrated toproduce the waveform 4. The thresholddetector generates a pulse 5 whichstarts as the waveform 4 crosses thethreshold and is sustained until thewaveform 4 falls below the threshold.Within the loop 5 triggers the impulsegenerator and external to the loopincrements the counter. The summing interval is a prefixed time and at its expiry the count is strobed into the bufferand the counter reset.It is necessary that the ratio between the impulse interval and the summing interval is equal to the maximum (fullscale) count. It is then possible for the impulse duration and the summing interval to be defined by the same clock

Delta-sigma modulation 7

with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined withabsolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that theamplitude of the impulse be accurately defined.On the right the input is now 0.4 V and the sum during the impulse is −0.6 V as opposed to −0.8 V on the left. Thusthe negative slope during the impulse is lower on the right than on the left.Also the sum is 0.4 V on the right during the interval as opposed to 0.2 V on the left. Thus the positive slope outsidethe impulse is higher on the right than on the left.The resultant effect is that the integral (4) crosses the threshold more quickly on the right than on the left. A fullanalysis would show that in fact the interval between threshold crossings on the right is half that on the left. Thus thefrequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left whichis consistent with the input voltage being doubled.Construction of the waveforms illustrated at (4) is aided by concepts associated with the Dirac delta function in thatall impulses of the same strength produce the same step when integrated, by definition. Then (4) is constructed usingan intermediate step (6) in which each integrated impulse is represented by a step of the assigned strength whichdecays to zero at the rate determined by the input voltage. The effect of the finite duration of the impulse isconstructed in (4) by drawing a line from the base of the impulse step at zero volts to intersect the decay line from(6) at the full duration of the impulse.As stated, Fig. 1 is a simplified block diagram of the delta-sigma ADC in which the various functional elements havebeen separated out for individual treatment and which tries to be independent of any particular implementation.Many particular implementations seek to define the impulse duration and the summing interval from the same clockas discussed above but in such a way that the start of the impulse is delayed until the next occurrence of theappropriate clock pulse boundary. The effect of this delay is illustrated in Fig. 1a for a sequence of impulses whichoccur at a nominal 2.5 clock intervals, firstly for impulses generated immediately the threshold is crossed aspreviously discussed and secondly for impulses delayed by the clock. The effect of the delay is firstly that the rampcontinues until the onset of the impulse, secondly that the impulse produces a fixed amplitude step so that theintegral retains the excess it acquired during the impulse delay and so the ramp restarts from a higher point and isnow on the same locus as the unclocked integral. The effect is that, for this example, the undelayed impulses willoccur at clock points 0, 2.5, 5, 7.5, 10, etc. and the clocked impulses will occur at 0, 3, 5, 8, 10, etc. The maximumerror that can occur due to clocking is marginally less than one count. Although the Sigma-Delta converter isgenerally implemented using a common clock to define the impulse duration and the summing interval it is notabsolutely necessary and an implementation in which the durations are independently defined avoids one source ofnoise, the noise generated by waiting for the next common clock boundary. Where noise is a primary considerationthat overrides the need for absolute amplitude accuracy; e.g., in bandwidth limited signal transmission, separatelydefined intervals may be implemented.

Delta-sigma modulation 8

Practical Implementation

Fig. 1b: circuit diagram

Fig. 1c: ADC waveforms

A circuit diagram for a practicalimplementation is illustrated, Fig 1band the associated waveforms Fig. 1c.A scrap view of an alternative frontend is shown in Fig. 1b which has theadvantage that the voltage at the switchterminals are relatively constant andclose to 0.0 V. Also the currentgenerated through R by −Vref isconstant at −Vref/R so that much lessnoise is radiated to adjacent parts ofthe circuit. Then this would be thepreferred front end in practice but, inorder to show the impulse as a voltagepulse so as to be consistent withprevious discussion, the front endgiven here, which is an electricalequivalent, is used.

From the top of Fig 1c the waveforms,labelled as they are on the circuitdiagram, are:-The clock.(a) Vin. This is shown as varying from0.4 V initially to 1.0 V and then to zerovolts to show the effect on thefeedback loop.

(b) The impulse waveform. It will bediscovered how this acquires its formas we traverse the feedback loop.(c) The current into the capacitor, Ic, isthe linear sum of the impulse voltageupon R and Vin upon R. To show thissum as a voltage the product R × Ic isplotted. The input impedance of theamplifier is regarded as so high that thecurrent drawn by the input isneglected.

(d) The negated integral of Ic. Thisnegation is standard for the op. amp.implementation of an integrator and comes about because the current into the capacitor at the amplifier input is thecurrent out of the capacitor at the amplifier output and the voltage is the integral of the current divided by thecapacitance of C.

Delta-sigma modulation 9

(e) The comparator output. The comparator is a very high gain amplifier with its plus input terminal connected forreference to 0.0 V. Whenever the negative input terminal is taken negative with respect the positive terminal of theamplifier the output saturates positive and conversely negative saturation for positive input. Thus the output saturatespositive whenever the integral (d) goes below the 0 V reference level and remains there until (d) goes positive withrespect to the reference level.(f) The impulse timer is a D type positive edge triggered flip flop. Input information applied at D is transferred to Qon the occurrence of the positive edge of the clock pulse. thus when the comparator output (e) is positive Q goespositive or remains positive at the next positive clock edge. Similarly, when (e) is negative Q goes negative at thenext positive clock edge. Q controls the electronic switch to generate the current impulse into the integrator.Examination of the waveform (e) during the initial period illustrated, when Vin is 0.4 V, shows (e) crossing thethreshold well before the trigger edge (positive edge of the clock pulse) so that there is an appreciable delay beforethe impulse starts. After the start of the impulse there is further delay while (e) climbs back past the threshold.During this time the comparator output remains high but goes low before the next trigger edge. At that next triggeredge the impulse timer goes low to follow the comparator. Thus the clock determines the duration of the impulse.For the next impulse the threshold is crossed immediately before the trigger edge and so the comparator is onlybriefly positive. Vin (a) goes to full scale, +Vref, shortly before the end of the next impulse. For the remainder of thatimpulse the capacitor current (c) goes to zero and hence the integrator slope briefly goes to zero. Following thisimpulse the full scale positive current is flowing (c) and the integrator sinks at its maximum rate and so crosses thethreshold well before the next trigger edge. At that edge the impulse starts and the Vin current is now matched by thereference current so that the net capacitor current (c) is zero. Then the integration now has zero slope and remains atthe negative value it had at the start of the impulse. This has the effect that the impulse current remains switched onbecause Q is stuck positive because the comparator is stuck positive at every trigger edge. This is consistent withcontiguous, butting impulses which is required at full scale input.Eventually Vin (a) goes to zero which means that the current sum (c) goes fully negative and the integral ramps up.It shortly thereafter crosses the threshold and this in turn is followed by Q, thus switching the impulse current off.The capacitor current (c) is now zero and so the integral slope is zero, remaining constant at the value it had acquiredat the end of the impulse.(g) The countstream is generated by gating the negated clock with Q to produce this waveform. Thereafter thesumming interval, sigma count and buffered count are produced using appropriate counters and registers. The Vinwaveform is approximated by passing the countstream (g) into a low pass filter, however it suffers from the defectdiscussed in the context of Fig. 1a. One possibility for reducing this error is to halve the feedback pulse length to halfa clock period and double its amplitude by halving the impulse defining resistor thus producing an impulse of thesame strength but one which never butts onto its adjacent impulses. Then there will be a threshold crossing for everyimpulse. In this arrangement a monostable flip flop triggered by the comparator at the threshold crossing will closelyfollow the threshold crossings and thus eliminate one source of error, both in the ADC and the sigma deltamodulator.

RemarksIn this section we have mainly dealt with the analogue to digital converter as a stand alone function which achievesastonishing accuracy with what is now a very simple and cheap architecture. Initially the Delta-Sigma configurationwas devised by INOSE et al. to solve problems in the accurate transmission of analog signals. In that application itwas the pulse stream that was transmitted and the original analog signal recovered with a low pass filter after thereceived pulses had been reformed. This low pass filter performed the summation function associated with Σ. Thehighly mathematical treatment of transmission errors was introduced by them and is appropriate when applied to thepulse stream but these errors are lost in the accumulation process associated with Σ to be replaced with the errorsassociated with the mean of means when discussing the ADC. For those uncomfortable with this assertion consider

Delta-sigma modulation 10

this.It is well known that by Fourier analysis techniques the incoming waveform can be represented over the summinginterval by the sum of a constant plus a fundamental and harmonics each of which has an exact integer number ofcycles over the sampling period. It is also well known that the integral of a sine wave or cosine wave over one ormore full cycles is zero. Then the integral of the incoming waveform over the summing interval reduces to theintegral of the constant and when that integral is divided by the summing interval it becomes the mean over thatinterval. The interval between pulses is proportional to the inverse of the mean of the input voltage during thatinterval and thus over that interval, ts, is a sample of the mean of the input voltage proportional to V/ts. Thus theaverage of the input voltage over the summing period is VΣ/N and is the mean of means and so subject to littlevariance.Unfortunately the analysis for the transmitted pulse stream has, in many cases, been carried over, uncritically, to theADC.It was indicated in section 2.2 Analysis that the effect of constraining a pulse to only occur on clock boundaries is tointroduce noise, that generated by waiting for the next clock boundary. This will have its most deleterious effect onthe high frequency components of a complex signal. Whilst the case has been made for clocking in the ADCenvironment, where it removes one source of error, namely the ratio between the impulse duration and the summinginterval, it is deeply unclear what useful purpose clocking serves in a transmission environment since it is a source ofboth noise and complexity.A very accurate transmission system with constant sampling rate may be formed using the full arrangement shownhere by transmitting the samples from the buffer protected with redundancy error correction. In this case there willbe a trade off between bandwidth and N, the size of the buffer. The signal recovery system will require redundancyerror checking, digital to analog conversion,and sample and hold circuitry. A possible further enhancement is toinclude some form of slope regeneration.This amounts to PCM (pulse code modulation) with digitization performedby a sigma-delta ADC.The above description shows why the impulse is called delta. The integral of an impulse is a step. A one bit DACmay be expected to produce a step and so must be a conflation of an impulse and an integration. The analysis whichtreats the impulse as the output of a 1-bit DAC hides the structure behind the name (sigma delta) and causeconfusion and difficulty interpreting the name as an indication of function. This analysis is very widespread but isdeprecated.A modern alternative method for generating voltage to frequency conversion is discussed in synchronous voltage tofrequency converter (SVFC) which may be followed by a counter to produce a digital representation in a similarmanner to that described above.[1]

Digital to analog conversion

DiscussionDelta-sigma modulators are often used in digital to analog converters (DACs). In general, a DAC converts a digitalnumber representing some analog value into that analog value. For example, the analog voltage level into a speakermay be represented as a 20 bit digital number, and the DAC converts that number into the desired voltage. Toactually drive a load (like a speaker) a DAC is usually connected to or integrated with an electronic amplifier.This can be done using a delta-sigma modulator in a Class D Amplifier. In this case, a multi-bit digital number isinput to the delta-sigma modulator, which converts it into a faster sequence of 0's and 1's. These 0's and 1's are thenconverted into analog voltages. The conversion, usually with MOSFET drivers, is very efficient in terms of powerbecause the drivers are usually either fully on or fully off, and in these states have low power loss.

Delta-sigma modulation 11

The resulting two-level signal is now like the desired signal, but with higher frequency components to change thesignal so that it only has two levels. These added frequency components arise from the quantization error of thedelta-sigma modulator, but can be filtered away by a simple low-pass filter. The result is a reproduction of theoriginal, desired analog signal from the digital values.The circuit itself is relatively inexpensive. The digital circuit is small, and the MOSFETs used for the poweramplification are simple. This is in contrast to a multi-bit DAC which can have very stringent design conditions toprecisely represent digital values with a large number of bits.The use of a delta-sigma modulator in the digital to analog conversion has enabled a cost-effective, low power, andhigh performance solution.

Relationship to Δ-modulation

Fig. 2: Derivation of ΔΣ- from Δ-modulation

ΔΣ modulation (SDM) is inspired by Δmodulation (DM), as shown in Fig. 2.If quantization was homogeneous (e.g.,if it was linear), the following wouldbe a sufficient derivation of theequivalence of DM and SDM:

1.1. Start with a block diagram of aΔ-modulator/demodulator.

2. The linearity property of integration( ) makes itpossible to move the integrator,which reconstructs the analog signalin the demodulator section, in frontof the Δ-modulator.

3.3. Again, the linearity property of theintegration allows the twointegrators to be combined and aΔΣ-modulator/demodulator blockdiagram is obtained.

However, the quantizer is not homogeneous, and so this explanation is flawed. It's true that ΔΣ is inspired byΔ-modulation, but the two are distinct in operation. From the first block diagram in Fig. 2, the integrator in thefeedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for deltamodulation of input signal , the low-pass filter sees the signal

However, sigma-delta modulation of the same input signal places at the low-pass filter

In other words, SDM and DM swap the position of the integrator and quantizer. The net effect is a simplerimplementation that has the added benefit of shaping the quantization noise away from signals of interest (i.e.,signals of interest are low-pass filtered while quantization noise is high-pass filtered). This effect becomes moredramatic with increased oversampling, which allows for quantization noise to be somewhat programmable. On theother hand, Δ-modulation shapes both noise and signal equally.

Delta-sigma modulation 12

Additionally, the quantizer (e.g., comparator) used in DM has a small output representing a small step up and downthe quantized approximation of the input while the quantizer used in SDM must take values outside of the range ofthe input signal, as shown in Fig. 3.

Fig. 3: An example of SDM of 100 samples of one period a sine wave. 1-bit samples (e.g., comparator output) overlaid with sine wavewhere logic high (e.g., ) represented by blue and logic low (e.g., ) represented by white.

In general, ΔΣ has some advantages versus Δ modulation:•• The whole structure is simpler:

•• Only one integrator is needed•• The demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal• The quantizer (e.g., comparator) can have full-scale outputs

•• The quantized value is the integral of the difference signal, which makes it less sensitive to the rate of change ofthe signal.

PrincipleThe principle of the ΔΣ architecture is explained at length in section 2. Initially, when a sequence starts, the circuitwill have an arbitrary state which is dependant on the integral of all previous history. In mathematical terms thiscorresponds to the arbitrary integration constant of the indefinite integral. This follows from the fact that at the heartof the method there is an integrator which can have any arbitrary state dependant on previous input, see Fig. 1c (d).From the occurrence of the first pulse onward the frequency of the pulse stream is proportional to the input voltageto be transformed. A demonstration applet is available online to simulate the whole architecture.[2]

VariationsThere are many kinds of ADC that use this delta-sigma structure. The above analysis focuses on the simplest1st-order, 2-level, uniform-decimation sigma-delta ADC. Many ADCs use a second-order 5-level sinc3 sigma-deltastructure.

2nd order and higher order modulator

Fig. 4: Block diagram of a 2nd order ΔΣ modulator

The number of integrators, andconsequently, the numbers of feedbackloops, indicates the order of aΔΣ-modulator; a 2nd order ΔΣmodulator is shown in Fig. 4. Firstorder modulators are unconditionallystable, but stability analysis must beperformed for higher order modulators.

Delta-sigma modulation 13

3-level and higher quantizerThe modulator can also be classified by the number of bits it has in output, which strictly depends on the output ofthe quantizer. The quantizer can be realized with a N-level comparator, thus the modulator has log2N-bit output. Asimple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a "1.5" bit quantizer; a 4-levelquantizer is a 2 bit quantizer; a 5-level quantizer is called a "2.5 bit" quantizer.[3]

Decimation structuresThe conceptually simplest decimation structure is a counter that is reset to zero at the beginning of each integrationperiod, then read out at the end of the integration period.The multi-stage noise shaping (MASH) structure has a noise shaping property, and is commonly used in digitalaudio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each ofwhich is equivalent to a first-order sigma delta modulator. The carry outputs are combined through summations anddelays to produce a binary output, the width of which depends on the number of stages (order) of the MASH.Besides its noise shaping function, it has two more attractive properties:• simple to implement in hardware; only common digital blocks such as accumulators, adders, and D flip-flops are

required•• unconditionally stable (there are no feedback loops outside the accumulators)A very popular decimation structure is the sinc filter. For 2nd order modulators, the sinc3 filter is close tooptimum.[4][5]

Quantization theory formulasWhen a signal is quantized, the resulting signal approximately has the second-order statistics of a signal withindependent additive white noise. Assuming that the signal value is in the range of one step of the quantized valuewith an equal distribution, the root mean square value of this quantization noise is

In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idletones and pattern noise in Sigma-Delta converters.

Oversampling ratio, where is the sampling frequency and is Nyquist rate

The rms noise voltage within the band of interest can be expressed in terms of OSR

Delta-sigma modulation 14

Oversampling

Fig. 5: Noise shaping curves and noise spectrum in ΔΣ modulator

Let's consider a signal at frequency and a sampling frequency of muchhigher than Nyquist rate (see fig. 5). ΔΣmodulation is based on the technique ofoversampling to reduce the noise in theband of interest (green), which alsoavoids the use of high-precision analogcircuits for the anti-aliasing filter. Thequantization noise is the same both in aNyquist converter (in yellow) and in anoversampling converter (in blue), but itis distributed over a larger spectrum. InΔΣ-converters, noise is further reducedat low frequencies, which is the bandwhere the signal of interest is, and it isincreased at the higher frequencies,where it can be filtered. This technique is known as noise shaping.

For a first order delta sigma modulator, the noise is shaped by a filter with transfer function .Assuming that the sampling frequency , the quantization noise in the desired signal bandwidth can beapproximated as:

.

Similarly for a second order delta sigma modulator, the noise is shaped by a filter with transfer function. The in-band quantization noise can be approximated as:

.

In general, for a -order ΔΣ-modulator, the variance of the in-band quantization noise:

.

When the sampling frequency is doubled, the signal to quantization noise is improved by for a -order ΔΣ-modulator. The higher the oversampling ratio, the higher the signal-to-noise ratio and the higher theresolution in bits.Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after themodulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies),but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of averaging of thehigher data rate bitstream.

Delta-sigma modulation 15

Example of decimationLet's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110,counting the number of ones, the decimation result is 4/8 = 0.5 = 100b (binary); in other words,•• the sample frequency is reduced by a factor of eight•• the serial (1-bit) input bus becomes a parallel (3-bits) output bus.

NamingThe technique was first presented in the early 1960s by prof. Haruhiko Yasuda while he was student at WasedaUniversity, Tokyo, Japan, The name Delta-Sigma comes directly from the presence of a Delta modulator and anintegrator, as firstly introduced by Inose et al. in their patent application.[6] That is, the name comes from integratingor "summing" differences, which are operations usually associated with Greek letters Sigma and Delta respectively.Both names Sigma-Delta and Delta-Sigma are frequently used.

References[1] Voltage-to-Frequency Converters (http:/ / www. analog. com/ static/ imported-files/ tutorials/ MT-028. pdf) by Walt Kester and James Bryant

2009. Analog Devices.[2] Analog Devices : Virtual Design Center : Interactive Design Tools : Sigma-Delta ADC Tutorial (http:/ / designtools. analog. com/ dt/

sdtutorial/ sdtutorial. html)[3] Sigma-delta class-D amplifier and control method for a sigma-delta class-D amplifier (http:/ / www. faqs. org/ patents/ app/ 20090072897) by

Jwin-Yen Guo and Teng-Hung Chang[4] A Novel Architecture for DAQ in Multi-channel, Large Volume, Long Drift Liquid Argon TPC (http:/ / www. slac. stanford. edu/ econf/

C0604032/ papers/ 0232. PDF) by S. Centro, G. Meng, F. Pietropaola, S. Ventura 2006[5] A Low Power Sinc3 Filter for ΣΔ Modulators (http:/ / ieeexplore. ieee. org/ xpl/ freeabs_all. jsp?arnumber=4253561) by A. Lombardi, E.

Bonizzoni, P. Malcovati, F. Maloberti 2007[6][6] H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- ΔΣ Modulation", IRE Trans on Space Electronics and

Telemetry, Sep. 1962, pp. 204-209.

• Walt Kester (2008-10). "ADC Architectures III: Sigma-Delta ADC Basics" (http:/ / www. analog. com/ static/imported-files/ tutorials/ MT-022. pdf) (PDF). Analog Devices. Retrieved 2010-11-02.

• R. Jacob Baker (2009). CMOS Mixed-Signal Circuit Design (http:/ / CMOSedu. com/ ) (2nd ed.). Wiley-IEEE.ISBN 978-0-470-29026-2.

• R. Schreier, G. Temes (2005). Understanding Delta-Sigma Data Converters. ISBN 0-471-46585-2.• S. Norsworthy, R. Schreier, G. Temes (1997). Delta-Sigma Data Converters. ISBN 0-7803-1045-4.• J. Candy, G. Temes (1992). Oversampling Delta-sigma Data Converters. ISBN 0-87942-285-8.

External links• 1-bit A/D and D/A Converters (http:/ / www. cs. tut. fi/ sgn/ arg/ rosti/ 1-bit/ )• Sigma-delta techniques extend DAC resolution (http:/ / www. embedded. com/ / showArticle.

jhtml?articleID=22101730) article by Tim Wescott 2004-06-23• Tutorial on Designing Delta-Sigma Modulators: Part I (http:/ / www. commsdesign. com/ design_corner/

showArticle. jhtml?articleID=18402743) and Part II (http:/ / www. commsdesign. com/ design_corner/showArticle. jhtml?articleID=18402763) by Mingliang (Michael) Liu

• Gabor Temes' Publications (http:/ / eecs. oregonstate. edu/ research/ members/ temes/ pubs. html)• Simple Sigma Delta Modulator example (http:/ / electronjunkie. wordpress. com/ tag/ sigma-delta-modulation/ )

Contains Block-diagrams, code, and simple explanations• Example Simulink model & scripts for continuous-time sigma-delta ADC (http:/ / www. circuitdesign. info/ blog/

2008/ 09/ example-simulink-model-scripts/ ) Contains example matlab code and Simulink model• Bruce Wooley's Delta-Sigma Converter Projects (http:/ / www-cis. stanford. edu/ icl/ wooley-grp/ projects. html)

Delta-sigma modulation 16

• An Introduction to Delta Sigma Converters (http:/ / www. beis. de/ Elektronik/ DeltaSigma/ DeltaSigma. html)(which covers both ADC's and DAC's sigma-delta)

• Demystifying Sigma-Delta ADCs (http:/ / www. maxim-ic. com/ appnotes. cfm/ an_pk/ 1870/ CMP/ WP-10).This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter.

• Motorola digital signal processors: Principles of sigma-delta modulation for analog-to-digital converters (http:/ /digitalsignallabs. com/ SigmaDelta. pdf)

• One-Bit Delta Sigma D/A Conversion Part I: Theory (http:/ / www. digitalsignallabs. com/ presentation. pdf)article by Randy Yates presented at the 2004 comp.dsp conference

• MASH (Multi-stAge noise SHaping) structure (http:/ / www. holmea. demon. co. uk/ Frac2/ Mash. htm) withboth theory and a block-level implementation of a MASH

• How a Sigma-Delta ADC Works at TechOnline (http:/ / www. techonline. com/ learning/ course/ 100152) freeregistration required to read the article

• Continuous time sigma-delta ADC noise shaping filter circuit architectures (http:/ / www. circuitdesign. info/blog/ 2008/ 11/ continuous-time-sigma-delta-adc-noise-shaping-filter-circuit-architectures-2/ ) discussesarchitectural trade-offs for continuous-time sigma-delta noise-shaping filters

• Some intuitive motivation for why a Delta Sigma modulator works (http:/ / www. cardinalpeak. com/ blog/?p=392/ )

Current mirrorA current mirror is a circuit designed to copy a current through one active device by controlling the current inanother active device of a circuit, keeping the output current constant regardless of loading. The current being'copied' can be, and sometimes is, a varying signal current. Conceptually, an ideal current mirror is simply an idealinverting current amplifier that reverses the current direction as well or it is a current-controlled current source(CCCS). The current mirror is used to provide bias currents and active loads to circuits

Mirror characteristicsThere are three main specifications that characterize a current mirror. The first is the transfer ratio (in the case of acurrent amplifier) or the output current magnitude (in the case of a constant current source CCS). The second is itsAC output resistance, which determines how much the output current varies with the voltage applied to the mirror.The third specification is the minimum voltage drop across the output part of the mirror necessary to make it workproperly. This minimum voltage is dictated by the need to keep the output transistor of the mirror in active mode.The range of voltages where the mirror works is called the compliance range and the voltage marking the boundarybetween good and bad behavior is called the compliance voltage. There are also a number of secondary performanceissues with mirrors, for example, temperature stability.

Current mirror 17

Practical approximationsFor small-signal analysis the current mirror can be approximated by its equivalent Norton impedance .In large-signal hand analysis, a current mirror is usually and simply approximated by an ideal current source.However, an ideal current source is unrealistic in several respects:•• it has infinite AC impedance, while a practical mirror has finite impedance•• it provides the same current regardless of voltage, that is, there are no compliance range requirements•• it has no frequency limitations, while a real mirror has limitations due to the parasitic capacitances of the

transistors•• the ideal source has no sensitivity to real-world effects like noise, power-supply voltage variations and component

tolerances.

Circuit realizations of current mirrors

Basic idea

A current mirror consists of two cascaded inverse converters with mirrored transfercharacteristic.

A bipolar transistor can be used as thesimplest current-to-current converterbut its transfer ratio would highlydepend on temperature variations, βtolerances, etc. To eliminate theseundesired disturbances, a currentmirror is composed of two cascadedcurrent-to-voltage andvoltage-to-current converters placed atthe same conditions and having reverse characteristics. They have not to be obligatory linear; the only requirement istheir characteristics to be mirrorlike (for example, in the BJT current mirror below, they are logarithmic andexponential). Usually, two identical converters are used but the characteristic of the first one is reversed by applyinga negative feedback. Thus a current mirror consists of two cascaded equal converters (the first - reversed and thesecond - direct).

Figure 1: A current mirror implemented with npnbipolar transistors using a resistor to set the reference

current IREF; VCC = supply voltage

Basic BJT current mirror

If a voltage is applied to the BJT base-emitter junction as an inputquantity and the collector current is taken as an output quantity,the transistor will act as an exponential voltage-to-currentconverter. By applying a negative feedback (simply joining thebase and collector) the transistor can be "reversed" and it willbegin acting as the opposite logarithmic current-to-voltageconverter; now it will adjust the "output" base-emitter voltage soas to pass the applied "input" collector current.

The simplest bipolar current mirror (shown in Figure 1)implements this idea. It consists of two cascaded transistor stagesacting accordingly as a reversed and direct voltage-to-currentconverters. Transistor Q1 is connected to ground. Its collector-basevoltage is zero as shown. Consequently, the voltage drop across Q1

Current mirror 18

is VBE, that is, this voltage is set by the diode law and Q1 is said to be diode connected. (See also Ebers-Mollmodel.) It is important to have Q1 in the circuit instead of a simple diode, because Q1 sets VBE for transistor Q2. If Q1and Q2 are matched, that is, have substantially the same device properties, and if the mirror output voltage is chosenso the collector-base voltage of Q2 is also zero, then the VBE-value set by Q1 results in an emitter current in thematched Q2 that is the same as the emitter current in Q1. Because Q1 and Q2 are matched, their β0-values also agree,making the mirror output current the same as the collector current of Q1. The current delivered by the mirror forarbitrary collector-base reverse bias VCB of the output transistor is given by (see bipolar transistor):

,

where IS = reverse saturation current or scale current, VT = thermal voltage and VA = Early voltage. This current isrelated to the reference current IREF when the output transistor VCB = 0 V by:

as found using Kirchhoff's current law at the collector node of Q1:

The reference current supplies the collector current to Q1 and the base currents to both transistors — when bothtransistors have zero base-collector bias, the two base currents are equal, IB1=IB2=IB.

Parameter β0 is the transistor β-value for VCB = 0 V.

Output resistance

If VCB is greater than zero in output transistor Q2, the collector current in Q2 will be somewhat larger than for Q1 dueto the Early effect. In other words, the mirror has a finite output (or Norton) resistance given by the rO of the outputtransistor, namely (see Early effect):

,where VA = Early voltage and VCB = collector-to-base bias.

Compliance voltage

To keep the output transistor active, VCB ≥ 0 V. That means the lowest output voltage that results in correct mirrorbehavior, the compliance voltage, is VOUT = VCV = VBE under bias conditions with the output transistor at the outputcurrent level IC and with VCB = 0 V or, inverting the I-V relation above:

where VT = thermal voltage and IS = reverse saturation current or scale current.

Current mirror 19

Extensions and complications

When Q2 has VCB > 0 V, the transistors no longer are matched. In particular, their β-values differ due to the Earlyeffect, with

where VA is the Early voltage and β0 = transistor β for VCB = 0 V. Besides the difference due to the Early effect, thetransistor β-values will differ because the β0-values depend on current, and the two transistors now carry differentcurrents (see Gummel-Poon model).Further, Q2 may get substantially hotter than Q1 due to the associated higher power dissipation. To maintainmatching, the temperature of the transistors must be nearly the same. In integrated circuits and transistor arrayswhere both transistors are on the same die, this is easy to achieve. But if the two transistors are widely separated, theprecision of the current mirror is compromised.Additional matched transistors can be connected to the same base and will supply the same collector current. In otherwords, the right half of the circuit can be duplicated several times with various resistor values replacing R2 on each.Note, however, that each additional right-half transistor "steals" a bit of collector current from Q1 due to the non-zerobase currents of the right-half transistors. This will result in a small reduction in the programmed current.An example of a mirror with emitter degeneration to increase mirror resistance is found in two-port networks.

For the simple mirror shown in the diagram, typical values of will yield a current match of 1% or better.

Figure 2: An n-channel MOSFET current mirror with aresistor to set the reference current IREF; VDD is the

supply voltage

Basic MOSFET current mirror

The basic current mirror can also be implemented using MOSFETtransistors, as shown in Figure 2. Transistor M1 is operating in thesaturation or active mode, and so is M2. In this setup, the outputcurrent IOUT is directly related to IREF, as discussed next.

The drain current of a MOSFET ID is a function of both thegate-source voltage and the drain-to-gate voltage of the MOSFETgiven by ID = f (VGS, VDG), a relationship derived from thefunctionality of the MOSFET device. In the case of transistor M1of the mirror, ID = IREF. Reference current IREF is a knowncurrent, and can be provided by a resistor as shown, or by a"threshold-referenced" or "self-biased" current source to ensurethat it is constant, independent of voltage supply variations.[1]

Using VDG=0 for transistor M1, the drain current in M1 is ID = f(VGS,VDG=0), so we find: f (VGS, 0) = IREF, implicitly determiningthe value of VGS. Thus IREF sets the value of VGS. The circuit in the diagram forces the same VGS to apply totransistor M2. If M2 is also biased with zero VDG and provided transistors M1 and M2 have good matching of theirproperties, such as channel length, width, threshold voltage etc., the relationship IOUT = f (VGS,VDG=0 ) applies, thussetting IOUT = IREF; that is, the output current is the same as the reference current when VDG=0 for the outputtransistor, and both transistors are matched.

The drain-to-source voltage can be expressed as VDS=VDG +VGS. With this substitution, the Shichman-Hodgesmodel provides an approximate form for function f (VGS,VDG):[1]

Current mirror 20

where, is a technology related constant associated with the transistor, W/L is the width to length ratio of thetransistor, VGS is the gate-source voltage, Vth is the threshold voltage, λ is the channel length modulation constant,and VDS is the drain source voltage.

Output resistance

Because of channel-length modulation, the mirror has a finite output (or Norton) resistance given by the ro of theoutput transistor, namely (see channel length modulation):

,where λ = channel-length modulation parameter and VDS = drain-to-source bias.

Compliance voltage

To keep the output transistor resistance high, VDG ≥ 0 V.[2] (see Baker).[3] That means the lowest output voltage thatresults in correct mirror behavior, the compliance voltage, is VOUT = VCV = VGS for the output transistor at the outputcurrent level with VDG = 0 V, or using the inverse of the f-function, f −1:

.For Shichman-Hodges model, f -1 is approximately a square-root function.

Extensions and reservations

A useful feature of this mirror is the linear dependence of f upon device width W, a proportionality approximatelysatisfied even for models more accurate than the Shichman-Hodges model. Thus, by adjusting the ratio of widths ofthe two transistors, multiples of the reference current can be generated.It must be recognized that the Shichman-Hodges model[4] is accurate only for rather dated technology, although itoften is used simply for convenience even today. Any quantitative design based upon new technology uses computermodels for the devices that account for the changed current-voltage characteristics. Among the differences that mustbe accounted for in an accurate design is the failure of the square law in Vgs for voltage dependence and the verypoor modeling of Vds drain voltage dependence provided by λVds. Another failure of the equations that proves verysignificant is the inaccurate dependence upon the channel length L. A significant source of L-dependence stems fromλ, as noted by Gray and Meyer, who also note that λ usually must be taken from experimental data.[1]

Current mirror 21

Feedback assisted current mirror

Figure 3: Gain-boosted current mirror with op amp feedback to increase outputresistance

Figure 4: MOSFET version of wide-swing current mirror; M1 and M2 are in activemode, while M3 and M4 are in Ohmic mode and act like resistors

Figure 3 shows a mirror using negativefeedback to increase output resistance.Because of the op amp, these circuits aresometimes called gain-boosted currentmirrors. Because they have relatively lowcompliance voltages, they also are calledwide-swing current mirrors. A variety ofcircuits based upon this idea are inuse,[5][6][7] particularly for MOSFETmirrors because MOSFETs have rather lowintrinsic output resistance values. AMOSFET version of Figure 3 is shown inFigure 4 where MOSFETs M3 and M4operate in Ohmic mode to play the samerole as emitter resistors RE in Figure 3, andMOSFETs M1 and M2 operate in activemode in the same roles as mirror transistorsQ1 and Q2 in Figure 3. An explanationfollows of how the circuit in Figure 3 works.

The operational amplifier is fed thedifference in voltages V1 - V2 at the top ofthe two emitter-leg resistors of value RE.This difference is amplified by the op ampand fed to the base of output transistor Q2. Ifthe collector base reverse bias on Q2 isincreased by increasing the applied voltageVA, the current in Q2 increases, increasingV2 and decreasing the difference V1 - V2entering the op amp. Consequently, the basevoltage of Q2 is decreased, and VBE of Q2decreases, counteracting the increase inoutput current.

If the op amp gain Av is large, only a verysmall difference V1 - V2 is sufficient togenerate the needed base voltage VB for Q2,namely

Consequently, the currents in the two legresistors are held nearly the same, and theoutput current of the mirror is very nearlythe same as the collector current IC1 in Q1,which in turn is set by the reference current as

Current mirror 22

where β1 for transistor Q1 and β2 for Q2 differ due to the Early effect if the reverse bias across the collector-base ofQ2 is non-zero.

Figure 5: Small-signal circuit to determine output resistance of mirror; transistor Q2is replaced with its hybrid-pi model; a test current IX at the output generates a

voltage VX, and the output resistance is Rout = VX / IX.

Output resistance

An idealized treatment of output resistance is given in the footnote.[8] A small-signal analysis for an op amp withfinite gain Av but otherwise ideal is based upon Figure 5 (β, rO and rπ refer to Q2). To arrive at Figure 5, notice thatthe positive input of the op amp in Figure 3 is at AC ground, so the voltage input to the op amp is simply the ACemitter voltage Ve applied to its negative input, resulting in a voltage output of −Av Ve. Using Ohm's law across theinput resistance rπ determines the small-signal base current Ib as:

Combining this result with Ohm's law for RE, Ve can be eliminated, to find:[9]

Kirchhoff's voltage law from the test source IX to the ground of RE provides:

Substituting for Ib and collecting terms the output resistance Rout is found to be:

For a large gain Av >> rπ / RE the maximum output resistance obtained with this circuit is

a substantial improvement over the basic mirror where Rout = rO.

The small-signal analysis of the MOSFET circuit of Figure 4 is obtained from the bipolar analysis by setting β = gmrπ in the formula for Rout and then letting rπ → ∞. The result is

This time, RE is the resistance of the source-leg MOSFETs M3, M4. Unlike Figure 3, however, as Av is increased(holding RE fixed in value), Rout continues to increase, and does not approach a limiting value at large Av.

Current mirror 23

Compliance voltage

For Figure 3, a large op amp gain achieves the maximum Rout with only a small RE. A low value for RE means V2also is small, allowing a low compliance voltage for this mirror, only a voltage V2 larger than the compliance voltageof the simple bipolar mirror. For this reason this type of mirror also is called a wide-swing current mirror, because itallows the output voltage to swing low compared to other types of mirror that achieve a large Rout only at theexpense of large compliance voltages.With the MOSFET circuit of Figure 4, like the circuit in Figure 3, the larger the op amp gain Av, the smaller RE canbe made at a given Rout, and the lower the compliance voltage of the mirror.

Other current mirrorsThere are many sophisticated current mirrors that have higher output resistances than the basic mirror (more closelyapproach an ideal mirror with current output independent of output voltage) and produce currents less sensitive totemperature and device parameter variations and to circuit voltage fluctuations. These multi-transistor mirror circuitsare used both with bipolar and MOS transistors. These circuits include:• the Widlar current source• the Wilson current source•• the Cascoded current sources

Notes[1] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer (2001). Analysis and Design of Analog Integrated Circuits (Fourth Edition

ed.). New York: Wiley. p. 308–309. ISBN 0471321680.[2] Keeping the output resistance high means more than keeping the MOSFET in active mode, because the output resistance of real MOSFETs

only begins to increase on entry into the active region, then rising to become close to maximum value only when VDG ≥ 0 V.[3] R. Jacob Baker (2010). CMOS Circuit Design, Layout and Simulation (Third ed.). New York: Wiley-IEEE. pp. 297, §9.2.1 and Figure 20.28,

p. 636. ISBN 978-0-470-88132-3.[4] NanoDotTek Report NDT14-08-2007, 12 August 2007 (http:/ / www. nanodottek. com/ NDT14_08_2007. pdf)[5] R. Jacob Baker. § 20.2.4 pp. 645–646. ISBN 978-0-470-88132-3.[6] Ivanov VI and Filanovksy IM (2004). Operational amplifier speed and accuracy improvement: analog circuit design with structural

methodology (http:/ / books. google. com/ books?id=IuLsny9wKIIC& pg=PA110& dq=gain+ boost+ wide+ + "current+ mirror"#PPA107,M1)(The Kluwer international series in engineering and computer science, v. 763 ed.). Boston, Mass.: Kluwer Academic. p. §6.1, p. 105–108.ISBN 1-4020-7772-6. .

[7] W. M. C. Sansen (2006). Analog design essentials. New York ; Berlin: Springer. p. §0310, p. 93. ISBN 0-387-25746-2.[8] An idealized version of the argument in the text, valid for infinite op amp gain, is as follows. If the op amp is replaced by a nullor, voltage V2

= V1, so the currents in the leg resistors are held at the same value. That means the emitter currents of the transistors are the same. If the VCB ofQ2 increases, so does the output transistor β because of the Early effect: β = β0 ( 1 + VCB / VA ). Consequently the base current to Q2 given byIB = IE / (β + 1) decreases and the output current Iout = IE / (1 + 1 / β) increases slightly because β increases slightly. Doing the math,

where the transistor output resistance is given by rO = ( VA + VCB ) / Iout. That is, the ideal mirror resistance for thecircuit using an ideal op amp nullor is Rout = ( β + 1 ) rO, in agreement with the value given later in the text when thegain → ∞.[9] Notice that as Av → ∞, Ve → 0 and Ib → IX.

Current mirror 24

References

External links• Patent (1968) by RJ Widlar: Biasing scheme especially suited for integrated circuits (http:/ / www. google. com/

patents?hl=en& id=IhlMAAAAEBAJ& dq=+ "Biasing+ scheme+ especially+ suited+ for+ integrated+ circuits"&printsec=frontcover& source=web& ots=Oq1T4owqMu& sig=oYenqTCaZip9QTcLwVjIcOgIc-U& sa=X&oi=book_result& resnum=4& ct=result#PPP3,M1)

• Current mirrors (http:/ / www. google. bg/ search?hl=en& source=hp& biw=1266& bih=641& q=current+mirror& oq=current+ mirror& aq=f& aqi=g10& aql=& gs_sm=e&gs_upl=1781l6281l0l14l14l0l3l3l0l328l2455l0. 4. 6. 1)

• 4QD tec - Current sources and mirrors (http:/ / www. 4qdtec. com/ csm. html) Compendium of circuits anddescriptions

Pulse-width modulation

An example of PWM in an AC motor drive: the phase-to-phase voltage (blue) ismodulated as a series of pulses that results in a sine-like flux density waveform (red) in

the magnetic circuit of the motor. The smoothness of the resultant waveform can becontrolled by the width and number of modulated impulses (per given cycle)

Pulse-width modulation (PWM), orpulse-duration modulation (PDM), isa commonly used technique forcontrolling power to inertial electricaldevices, made practical by modernelectronic power switches.

The average value of voltage (andcurrent) fed to the load is controlled byturning the switch between supply andload on and off at a fast pace. Thelonger the switch is on compared to theoff periods, the higher the powersupplied to the load is.

The PWM switching frequency has tobe much faster than what would affectthe load, which is to say the device thatuses the power. Typically switchingshave to be done several times a minutein an electric stove, 120 Hz in a lamp dimmer, from few kilohertz (kHz) to tens of kHz for a motor drive and wellinto the tens or hundreds of kHz in audio amplifiers and computer power supplies.

The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time; a low duty cyclecorresponds to low power, because the power is off for most of the time. Duty cycle is expressed in percent, 100%being fully on.The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there ispractically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being theproduct of voltage and current, is thus in both cases close to zero. PWM also works well with digital controls, which,because of their on/off nature, can easily set the needed duty cycle.PWM has also been used in certain communication systems where its duty cycle has been used to conveyinformation over a communications channel.

Pulse-width modulation 25

HistoryIn the past, when only partial power was needed (such as for a sewing machine motor), a rheostat (located in thesewing machine's foot pedal) connected in series with the motor adjusted the amount of current flowing through themotor, but also wasted power as heat in the resistor element. It was an inefficient scheme, but tolerable because thetotal power was low. This was one of several methods of controlling power. There were others—some still inuse—such as variable autotransformers, including the trademarked 'Autrastat' for theatrical lighting; and the Variac,for general AC power adjustment. These were quite efficient, but also relatively costly.For about a century, some variable-speed electric motors have had decent efficiency, but they were somewhat morecomplex than constant-speed motors, and sometimes required bulky external electrical apparatus, such as a bank ofvariable power resistors or rotating converter such as Ward Leonard drive .However, in addition to motor drives for fans, pumps and robotic servos, there was a great need for compact and lowcost means for applying adjustable power for many devices, such as electric stoves and lamp dimmers.One early application of PWM was in the Sinclair X10, a 10 W audio amplifier available in kit form in the 1960s. Ataround the same time PWM started to be used in AC motor control [1]

Principle

Fig. 1: a pulse wave, showing the definitions of , and D.

Pulse-width modulation uses arectangular pulse wave whose pulsewidth is modulated resulting in thevariation of the average value of thewaveform. If we consider a pulsewaveform with a low value

, a high value and a dutycycle D (see figure 1), the averagevalue of the waveform is given by:

As is a pulse wave, its value isfor and for . The above expression then becomes:

This latter expression can be fairly simplified in many cases where as . From this, it isobvious that the average value of the signal ( ) is directly dependent on the duty cycle D.

Pulse-width modulation 26

Fig. 2: A simple method to generate the PWM pulse train corresponding to a given signalis the intersective PWM: the signal (here the red sinewave) is compared with a sawtoothwaveform (blue). When the latter is less than the former, the PWM signal (magenta) is in

high state (1). Otherwise it is in the low state (0).

The simplest way to generate a PWMsignal is the intersective method,which requires only a sawtooth or atriangle waveform (easily generatedusing a simple oscillator) and acomparator. When the value of thereference signal (the red sine wave infigure 2) is more than the modulationwaveform (blue), the PWM signal(magenta) is in the high state,otherwise it is in the low state.

Delta

In the use of delta modulation forPWM control, the output signal isintegrated, and the result is comparedwith limits, which correspond to aReference signal offset by a constant.Every time the integral of the outputsignal reaches one of the limits, thePWM signal changes state.

Fig. 3 : Principle of the delta PWM. The output signal (blue) is compared with the limits(green). These limits correspond to the reference signal (red), offset by a given value.Every time the output signal reaches one of the limits, the PWM signal changes state.

Delta-sigma

In delta-sigma modulation as a PWMcontrol method, the output signal issubtracted from a reference signal toform an error signal. This error isintegrated, and when the integral of theerror exceeds the limits, the outputchanges state.

Pulse-width modulation 27

Fig. 4 : Principle of the sigma-delta PWM. The top green waveform is the referencesignal, on which the output signal (PWM, in the bottom plot) is subtracted to form the

error signal (blue, in top plot). This error is integrated (middle plot), and when the integralof the error exceeds the limits (red lines), the output changes state.

Space vector modulation

Space vector modulation is a PWMcontrol algorithm for multi-phase ACgeneration, in which the referencesignal is sampled regularly; after eachsample, non-zero active switchingvectors adjacent to the reference vectorand one or more of the zero switchingvectors are selected for the appropriatefraction of the sampling period in orderto synthesize the reference signal asthe average of the used vectors.

Direct torque control (DTC)

Direct torque control is a method usedto control AC motors. It is closelyrelated with the delta modulation (seeabove). Motor torque and magneticflux are estimated and these arecontrolled to stay within theirhysteresis bands by turning on new combination of the device's semiconductor switches each time either of the signaltries to deviate out of the band.

Time proportioningMany digital circuits can generate PWM signals (e.g. many microcontrollers have PWM outputs). They normally usea counter that increments periodically (it is connected directly or indirectly to the clock of the circuit) and is reset atthe end of every period of the PWM. When the counter value is more than the reference value, the PWM outputchanges state from high to low (or low to high).[2] This technique is referred to as time proportioning, particularlyas time-proportioning control[3] – which proportion of a fixed cycle time is spent in the high state.The incremented and periodically reset counter is the discrete version of the intersecting method's sawtooth. Theanalog comparator of the intersecting method becomes a simple integer comparison between the current countervalue and the digital (possibly digitized) reference value. The duty cycle can only be varied in discrete steps, as afunction of the counter resolution. However, a high-resolution counter can provide quite satisfactory performance.

Pulse-width modulation 28

Types

Fig. 5 : Three types of PWM signals (blue): leading edge modulation (top), trailing edgemodulation (middle) and centered pulses (both edges are modulated, bottom). The greenlines are the sawtooth waveform (first and second cases) and a triangle waveform (third

case) used to generate the PWM waveforms using the intersective method.

Three types of pulse-width modulation(PWM) are possible:1. The pulse center may be fixed in

the center of the time window andboth edges of the pulse moved tocompress or expand the width.

2.2. The lead edge can be held at thelead edge of the window and the tailedge modulated.

3.3. The tail edge can be fixed and thelead edge modulated.

Spectrum

The resulting spectra (of the threecases) are similar, and each contains adc component, a base sidebandcontaining the modulating signal andphase modulated carriers at eachharmonic of the frequency of the pulse.The amplitudes of the harmonic groupsare restricted by a envelope (sinc function) and extend to infinity.

On the contrary, the delta modulation is a random process that produces continuous spectrum without distinctharmonics.

Applications

TelecommunicationsIn telecommunications, the widths of the pulses correspond to specific data values encoded at one end and decodedat the other.Pulses of various lengths (the information itself) will be sent at regular intervals (the carrier frequency of themodulation).

_ _ _ _ _ _ _ _

| | | | | | | | | | | | | | | |

Clock | | | | | | | | | | | | | | | |

__| |____| |____| |____| |____| |____| |____| |____| |____

_ __ ____ ____ _

PWM Signal | | | | | | | | | |

| | | | | | | | | |

_________| |____| |___| |________| |_| |___________

Data 0 1 2 4 0 4 1 0

The inclusion of a clock signal is not necessary, as the leading edge of the data signal can be used as the clock if asmall offset is added to the data value in order to avoid a data value with a zero length pulse.

Pulse-width modulation 29

_ __ ___ _____ _ _____ __ _

| | | | | | | | | | | | | | | |

PWM Signal | | | | | | | | | | | | | | | |

__| |____| |___| |__| |_| |____| |_| |___| |_____

Data 0 1 2 4 0 4 1 0

Power deliveryPWM can be used to control the amount of power delivered to a load without incurring the losses that would resultfrom linear power delivery by resistive means. Potential drawbacks to this technique are the pulsations defined bythe duty cycle, switching frequency and properties of the load. With a sufficiently high switching frequency and,when necessary, using additional passive electronic filters, the pulse train can be smoothed and average analogwaveform recovered.High frequency PWM power control systems are easily realisable with semiconductor switches. As explained above,almost no power is dissipated by the switch in either on or off state. However, during the transitions between on andoff states, both voltage and current are non-zero and thus power is dissipated in the switches. By quickly changingthe state between fully on and fully off (typically less than 100 nanoseconds), the power dissipation in the switchescan be quite low compared to the power being delivered to the load.Modern semiconductor switches such as MOSFETs or Insulated-gate bipolar transistors (IGBTs) are well suitedcomponents for high efficiency controllers. Frequency converters used to control AC motors may have efficienciesexceeding 98 %. Switching power supplies have lower efficiency due to low output voltage levels (often even lessthan 2 V for microprocessors are needed) but still more than 70-80 % efficiency can be achieved.Variable-speed fan controllers for computers usually use PWM, as it is far more efficient when compared to apotentiometer or rheostat. (Neither of the latter is practical to operate electronically; they would require a small drivemotor.)Light dimmers for home use employ a specific type of PWM control. Home-use light dimmers typically includeelectronic circuitry which suppresses current flow during defined portions of each cycle of the AC line voltage.Adjusting the brightness of light emitted by a light source is then merely a matter of setting at what voltage (orphase) in the AC halfcycle the dimmer begins to provide electrical current to the light source (e.g. by using anelectronic switch such as a triac). In this case the PWM duty cycle is the ratio of the conduction time to the durationof the half AC cycle defined by the frequency of the AC line voltage (50 Hz or 60 Hz depending on the country).These rather simple types of dimmers can be effectively used with inert (or relatively slow reacting) light sourcessuch as incandescent lamps, for example, for which the additional modulation in supplied electrical energy which iscaused by the dimmer causes only negligible additional fluctuations in the emitted light. Some other types of lightsources such as light-emitting diodes (LEDs), however, turn on and off extremely rapidly and would perceivablyflicker if supplied with low frequency drive voltages. Perceivable flicker effects from such rapid response lightsources can be reduced by increasing the PWM frequency. If the light fluctuations are sufficiently rapid, the humanvisual system can no longer resolve them and the eye perceives the time average intensity without flicker (see flickerfusion threshold).In electric cookers, continuously-variable power is applied to the heating elements such as the hob or the grill using adevice known as a Simmerstat. This consists of a thermal oscillator running at approximately two cycles per minuteand the mechanism varies the duty cycle according to the knob setting. The thermal time constant of the heatingelements is several minutes, so that the temperature fluctuations are too small to matter in practice.

Pulse-width modulation 30

Voltage regulationPWM is also used in efficient voltage regulators. By switching voltage to the load with the appropriate duty cycle,the output will approximate a voltage at the desired level. The switching noise is usually filtered with an inductorand a capacitor.One method measures the output voltage. When it is lower than the desired voltage, it turns on the switch. When theoutput voltage is above the desired voltage, it turns off the switch.

Audio effects and amplificationPWM is sometimes used in sound (music) synthesis, in particular subtractive synthesis, as it gives a sound effectsimilar to chorus or slightly detuned oscillators played together. (In fact, PWM is equivalent to the difference of twosawtooth waves. [4]) The ratio between the high and low level is typically modulated with a low frequencyoscillator, or LFO. In addition, varying the duty cycle of a pulse waveform in a subtractive-synthesis instrumentcreates useful timbral variations. Some synthesizers have a duty-cycle trimmer for their square-wave outputs, andthat trimmer can be set by ear; the 50% point was distinctive, because even-numbered harmonics essentiallydisappear at 50%.A new class of audio amplifiers based on the PWM principle is becoming popular. Called "Class-D amplifiers",these amplifiers produce a PWM equivalent of the analog input signal which is fed to the loudspeaker via a suitablefilter network to block the carrier and recover the original audio. These amplifiers are characterized by very goodefficiency figures (≥ 90%) and compact size/light weight for large power outputs. For a few decades, industrial andmilitary PWM amplifiers have been in common use, often for driving servo motors. They offer very good efficiency,commonly well above 90%. Field-gradient coils in MRI machines are driven by relatively-high-power PWMamplifiers.Historically, a crude form of PWM has been used to play back PCM digital sound on the PC speaker, which is drivenby only two voltage levels, typically 0 V and 5 V. By carefully timing the duration of the pulses, and by relying onthe speaker's physical filtering properties (limited frequency response, self-inductance, etc.) it was possible to obtainan approximate playback of mono PCM samples, although at a very low quality, and with greatly varying resultsbetween implementations.In more recent times, the Direct Stream Digital sound encoding method was introduced, which uses a generalizedform of pulse-width modulation called pulse density modulation, at a high enough sampling rate (typically in theorder of MHz) to cover the whole acoustic frequencies range with sufficient fidelity. This method is used in theSACD format, and reproduction of the encoded audio signal is essentially similar to the method used in class-Damplifiers.

References[1] Schönung, A.; Stemmler, H. (August 1964). "Geregelter Drehstrom-Umkehrantrieb mit gesteuertem Umrichter nach dem

Unterschwingungsverfahren". BBC Mitteilungen (Brown Boveri et Cie) 51 (8/9): 555–577.[2] www.netrino.com – Introduction to Pulse Width Modulation (PWM) (http:/ / www. netrino. com/ Embedded-Systems/ How-To/

PWM-Pulse-Width-Modulation)[3] Fundamentals of HVAC Control Systems, by Robert McDowall, p. 21 (http:/ / books. google. com/ books?id=UMk1EUp-W-UC&

pg=PA21& dq="time+ proportioning")[4] http:/ / www. soundonsound. com/ sos/ Mar03/ articles/ synthsecrets47. asp

Pulse-width modulation 31

External links• An Introduction to Delta Sigma Converters (http:/ / www. beis. de/ Elektronik/ DeltaSigma/ DeltaSigma. html)• Introductory Tutorial (http:/ / www. embedded. com. au/ pages/ Motor_Interface. html) on PWM and Quadrature

Encoding

Smart transducer

A smart transducer containing a transducer, processing unit and communication interface.

A smart transducer is an analog ordigital transducer or actuator combinedwith a processing unit and acommunication interface.

As sensors and actuators become morecomplex they provide support forvarious modes of operation andinterfacing. Some applications requireadditionally fault-tolerance anddistributed computing. Such high-level functionality can be achieved by adding an embedded microcontroller to theclassical sensor/actuator, which increases the ability to cope with complexity at a fair price.

In the machine vision field, a single compact unit which combines the imaging functions and the complete imageprocessing functions is often called a smart sensor.

Translinear circuitA translinear circuit is a circuit that carries out its function using the translinear principle. These are current-modecircuits that can be made using transistors that obey an exponential current-voltage characteristic—this includesBJTs and CMOS transistors in weak inversion.The word translinear (TL) was invented by Barrie Gilbert in 1975[1] to describe circuits that used the exponentialcurrent-voltage relation of BJTs[2][3]. By using this exponential relationship, this class of circuits can implementmultiplication, amplification and power-law relationships. When Barrie Gilbert described this class of circuits healso described the translinear principle (TLP) which made the analysis of these circuits possible in a way that theprevious view of BJTs as linear current amplifiers did not allow. TLP was later extended to include other elementsthat obey an exponential current-voltage relationship (such as CMOS transistors in weak inversion).The TLP has been used in a variety of circuits including vector arithmetic circuits[4], current conveyors,current-mode operational amplifiers, and RMS-DC converters[5]. It has been in use since the 1960s (by Gilbert), butwas not formalized until 1975[1]. In the 1980s, Evert Seevinck's work helped to create a systematic process fortranslinear circuit design. In 1990 Seevinck invented a circuit he called a companding current-mode integrator[6] thatwas effectively a first-order log-domain filter. A version of this was generalized in 1993 by Douglas Frey and theconnection between this class of filters and TL circuits was made most explicit in the late 90s work of Jan Mulder etal. where they describe the dynamic translinear principle. More work by Seevinck led to synthesis techniques forextremely low-power TL circuits[7]. More recent work in the field has led to the voltage-translinear principle,multiple-input translinear element networks, and field-programmable analog arrays (FPAAs).

Translinear circuit 32

The Translinear PrincipleThe translinear principle is that in a closed loop containing an even number of translinear elements (TEs) with anequal number of them arranged clockwise and counter-clockwise, the product of the currents through the clockwiseTEs equals the product of the currents through the counter-clockwise TEs or

The TLP is dependent on the exponential current-voltage relationship of a circuit element. Thus, an ideal TE followsthe relationship

where is a pre-exponential scaling current, is a dimensionless multiplier to , is a dimensionlessmultiplier to the gate-emitter voltage and is the thermal voltage .In a circuit, TEs are described as either clockwise (CW) or counterclockwise (CCW). If the arrow on the emitterpoint clockwise, it's considered a CW TE, if it points counterclockwise, it's considered a CCW TE. Consider anexample:

A circuit with a translinear loop

By Kirchoff's Voltage Law, the voltage around the loop that goes from to must be 0. In other words, thevoltage drops must equal the voltage increases. When a loop that only goes through the emitter-gate connections ofTEs exists, we call it a translinear loop. Mathematically, this becomes

Because of the exponential current-voltage relationship, this implies TLP:

this is effectively because current is used as the signal. Because of this, voltage is the log of the signal and additionin the log domain is like multiplication of the original signal (ie ). This rule, that theproduct of the current through CW TEs is equal to the current through CCW TEs in a translinear loop is known asthe translinear principle.For a detailed derivation of the TLP, and physical interpretations of the parameters in the ideal TE law, please referto [2] or [3].A derivation of the TLP based on graph theory concepts has been given by Rafael Vargas-Bernal et al. in 2000[8][9].In this work, it is illustrated as a graphical representation can be used for the future development of a verificationtool that plays an important and fundamental role in the structured design of translinear circuits.

Translinear circuit 33

Example Translinear Circuits

Squaring Circuit

A TL squaring circuit using an alternating TLloop

According to TLP, . This means that where is the unit scaling current (ie

the definition of unity for the circuit). This is effectively a squaring circuit where . This particular circuit is

designed in what is known as an alternating topology, which means that CW TEs alternate with CCW TEs. Here'sthe same circuit in a stacked topology.

A TL squaring circuit using a stacked TL loop

The same equation applies to this circuit as to the alternating topology according to TLP. Neither of these circuitscan be implemented in real life without biasing the transistors such that the currents expected to flow through themcan actually do so. Here are some example biasing schemes:

A biasing scheme for the alternating squaringcircuit using diode connections.

A biasing scheme for the alternating squaringcircuit using diode connections and a feedbackconnection between the collector and emitter of

the TE (EP connection).

A biasing scheme for the stacked squaring circuitusing diode connections and an EP connection.

Translinear circuit 34

2-Quadrant MultiplierThe design of a 2-quadrant multiplier can be easily done using TLP. The first issue with this circuit is that negativevalues of currents need to be represented. Since all currents must be positive for the exponential relationship to hold(the log operation is not defined for negative numbers), positive currents must represent negative currents. The waythis is done is by defining two positive currents whose difference is the current of interest.A two quadrant multiplier has the relationship hold while allowing to be either positive or negative.We'll let and . Also note that and etc. Plugging these

values into the original equation yields . This can be rephrased as

. By equating the positive and negative portions of the equation, twoequations that can be directly built as translinear loops arise:

The following are the alternating loops that implement the desired equations and some biasing schemes for thecircuit.

The translinear loops that implement our desiredequations.

A biasing scheme for the alternating TLtwo-quadrant multiplier circuit using diode

connections and an EP connection.

A biasing scheme that consolidates some currentsources.

References[1] Gilbert, Barrie (1975-01-09). "Translinear circuits: a proposed classification".

Electronics Letters 11 (1): 14–16. doi:10.1049/el:19750011.[2] Liu, Shih-Chii; Jörg Kramer, Giacomo Indiveri, Tobias Delbrück, and Rodney

Douglas (2002). Analog VLSI: Circuits and Principles (http:/ / books. google. com/?id=ewqb4aurZtMC& printsec=frontcover& dq=analog+ vlsi). MIT Press.ISBN 0262122553. .

[3] Minch, Bradley A. (2000) (PDF). Analysis and Synthesis of Translinear Circuits(http:/ / www. csl. cornell. edu/ TR/ CSL-TR-2000-1002. pdf). . Retrieved2008-02-21.

[4] Gilbert, Barrie (1976-05-27). "High-accuracy vector-difference and vector-sumcircuits". Electronics Letters 12 (11): 293–294. doi:10.1049/el:19760226.

[5] Ashok, S. (1976-04-15). "Translinear root-difference-of-squares circuit". ElectronicsLetters 12 (8): 194–195. doi:10.1049/el:19760150.

[6] Seevinck, Evert (1990-11-22). "Companding current-mode integrator: a new circuitprinciple for continuous-time monolithic filters". Electronics Letters 26 (24):2046–2047. doi:10.1049/el:19901319.

[7] Seevinck, Evert; Vittoz, E.A.; Du Plessi, M.; Joubert, T.H.; Beetge, W. (December,2000). "CMOS Translinear Circuits for Minimum Supply Voltage". IEEETransactions on Circuits and Systems-II: Analog and Digital Signal Processing 47(12): 1560–1564. doi:10.1109/82.899656.

[8] Vargas-Bernal, Rafael; Reyes, Arturo Sarmiento; Serdijn, Wouter A. (28–31 May2000). "Identifying Translinear Loops in the Circuit Topology". Proceedings of theIEEE International Symposium on Circuits and Systems (ISCAS), Geneva,Switzerland. 2. pp. 585–588. doi:10.1109/ISCAS.2000.856396. ISBN 0-7803-5482-6

[9] Vargas-Bernal, Rafael (November 2002). "Prediction of Multiple DC OperatingPoints in a CMOS Log-Domain Filter". Proceedings of the IEEE Latin-AmericanCAS Tour, Puebla Mexico. pp. 70–73.

Article Sources and Contributors 35

Article Sources and ContributorsPulse-density modulation  Source: http://en.wikipedia.org/w/index.php?oldid=474453198  Contributors: ABCD, Andux, Chzz, Damian Yerrick, Dcoetzee, Dpbsmith, EBB, Graham87,Hephaestos, Jaxl, Jbinder, Kaldosh, Kghose, Maximus Rex, Michael Hardy, Mjb, Moxfyre, NicholasKinar, Nunh-huh, Oleg Alexandrov, Oxymoron83, Pcap, Rbj, Reywas92, Rjf ie, Ross Fraser,SchreiberBike, Serrano24, Smack, Starx, Sylvain Leroux, TedPavlic, Wdwd, Xavier Giró, 25 anonymous edits

Delta-sigma modulation  Source: http://en.wikipedia.org/w/index.php?oldid=476791488  Contributors: 121a0012, Alain r, Ali@gwc.org.uk, Altzinn, Atlant, Bappi48, Beetelbug, Bob Bermani,Bpromo7, Bratsche, CapitalR, Charles Matthews, Cojoco, CyrilB, Damian Yerrick, DavidCary, Denisarona, DmitTrix, Edokter, Epugachev, Gaius Cornelius, Gerweck, GregorB, Hankwang,Hanspi, HenningThielemann, Icarus4586, Jd8837, Jim.henderson, Jkl, Jwinius, Katanzag, Krishnavedala, Kvng, Lanugo, Lm317t, Lulo.it, Lv131, Mahira75249, Margin1522, Markhurd, Mild BillHiccup, Mortense, MrOllie, Mwarren us, NOW, Ohconfucius, Omegatron, Onionmon, Optimale, Ozfest, Puffingbilly, Qdr, Requestion, Rich Farmbrough, Rjf ie, Rjwilmsi, S Roper, Sam8,Sanjosanjo, SchuminWeb, Serrano24, Snood1, Southcaltree, StradivariusTV, TedPavlic, Tetvesdugo, The Anome, Voidxor, Wsmarz, Yates, 152 anonymous edits

Current mirror  Source: http://en.wikipedia.org/w/index.php?oldid=472931941  Contributors: Albert Castillo, Albugwiki, Alfred Centauri, Azaghal of Belegost, Bjf, BorgQueen, Brews ohare,Chowbok, Circuit dreamer, DabMachine, Dr.K., Editor at Large, Everyking, Hooperbloob, ICE77, Iandiver, Inductiveload, Iridescent, Kungfuadam, Leonard G., Light current, Lindenh248,Lovibond, Mako098765, Matt B., Mboverload, Msiddalingaiah, Omegatron, Pdn, Petrb, Pgadfor, Rich Farmbrough, Rogerbrent, Rohitbd, Ronz, Royboycrashfan, Rpyle731, Rsashwinkumar,Searchme, Slasher-fun, Soap, Zangar, 91 anonymous edits

Pulse-width modulation  Source: http://en.wikipedia.org/w/index.php?oldid=467460285  Contributors: Adambro, Ademkader, Alll, Allmightyduck, Andy Dingley, Arjayay, Asher196,Bobo192, CapitalR, Chrike, Circuit dreamer, Ckatz, CyrilB, DARTH SIDIOUS 2, DMChatterton, DV8 2XL, Damian Yerrick, DavidCary, Deconstructhis, Dermeister, Deville, Dicklyon,DoostdarWKP, EnOreg, EpiVictor, Everyking, Fish and karate, Funky Monkey, Fæ, GB fan, GRAHAMUK, GandalfDaGraay, Gerry Ashton, Giftlite, Glenn, Glrx, Gurch, Heron, Hooperbloob,Ian Pitchford, Ixfd64, JKN abb, Jaberwocky6669, Jaeger5432, Jeepday, Joel Saks, Johncatsoulis, Kenyon, KnightRider, Krishnavedala, Kubing, Lambtron, Leopold Stotch, Lumpbucket,ML1986, Matt B., Mayflowerone, Meestaplu, Michael Hardy, Mikey likes mountains, Mschlindwein, Nahum Reduta, Nbarth, Nick Wilson, Nikevich, Nit vs atwiki, OlEnglish, Phoenix7777,PierreAbbat, Politepunk, R'n'B, RJFJR, RandomAct, Rivertorch, Rohitbd, Rsutherland, RuM, S Roper, SCEhardt, Sam8, Selket, Shfork, Shulini, Simon Brady, SimonP, Sonett72, Spinningspark,Spook`, Squall line, Starx, Sven Manguard, TedPavlic, Teslaton, Tim Starling, Toffile, Twas Now, Wikipelli, Wizard191, Xzapro4, Yngvarr, Zangar, Zureks, 216 anonymous edits

Smart transducer  Source: http://en.wikipedia.org/w/index.php?oldid=442321089  Contributors: Huon, KJG2007, Kauai68, Malcolma, Michael Devore, North8000, Voin.legourski, 3anonymous edits

Translinear circuit  Source: http://en.wikipedia.org/w/index.php?oldid=453455957  Contributors: Bdieseldorff, Bminch, Casmemsnano, Giftlite, Que, R'n'B, RTC, Rich Farmbrough, Roopunk,1 anonymous edits

Image Sources, Licenses and Contributors 36

Image Sources, Licenses and ContributorsImage:Pulse-density modulation 1 period.gif  Source: http://en.wikipedia.org/w/index.php?title=File:Pulse-density_modulation_1_period.gif  License: Public Domain  Contributors: Kaldosh,WdwdImage:Pulse-density modulation 2 periods.gif  Source: http://en.wikipedia.org/w/index.php?title=File:Pulse-density_modulation_2_periods.gif  License: Public Domain  Contributors: Kaldosh,WdwdImage:Pulse density modulation.svg  Source: http://en.wikipedia.org/w/index.php?title=File:Pulse_density_modulation.svg  License: Creative Commons Attribution-Sharealike 3.0,2.5,2.0,1.0 Contributors: Original uploader was Moxfyre at en.wikipediaImage:Block Diagram Delta-Sigma.svg  Source: http://en.wikipedia.org/w/index.php?title=File:Block_Diagram_Delta-Sigma.svg  License: GNU Free Documentation License  Contributors:Fuhghettaboutit, Puffingbilly, 1 anonymous editsImage:Fig 1a.svg  Source: http://en.wikipedia.org/w/index.php?title=File:Fig_1a.svg  License: GNU Free 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License 37

LicenseCreative Commons Attribution-Share Alike 3.0 Unported//creativecommons.org/licenses/by-sa/3.0/