scsi controller

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This document contains information on a product under development at Advanced Micro Devices Inc. The information is intendedto help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Publication# 16506 Rev. C Amendment/0

Issue Date: May 1993

AdvancedMicro

DevicesAm53C94/Am53C96High Performance SCSI Controller

PRELIMINARY

DISTINCTIVE CHARACTERISTICS

Pin/function compatible with NCR53C94/53C96

AMDs Patented GLITCH EATERTMCircuitry onREQandACKinputs

5 Mbytes per second synchronous SCSItransfer rate

20 Mbytes per second DMA transfer rate

16-bit DMA Interface plus 2 bits of parity

Flexible three bus architecture

Single ended SCSI bus supported byAm53C94

Single ended and differential SCSI bussupported by Am53C96

Selection of multiplexed or non-multiplexedaddress and data bus

High current drivers (48 mA) for directconnection to the single ended SCSI bus

Supports Disconnect and Reselect commands

Supports burst mode DMA operation with athreshold of 8

Supports 3-byte-tagged queuing as per theSCSI-2 specification

Supports group 2 and 5 command recognitionas per the SCSI-2 specification

Advanced CMOS process for low power

consumption

Am53C94 available in 84-pin PLCC package

Am53C96 available in 100-pin PQFP package

GENERAL DESCRIPTION

The High Performance SCSI Controller (HPSC) has aflexible three bus architecture. The HPSC has a 16-bitDMA interface, an 8 bit host data interface and an 8-bitSCSI data interface. The HPSC is designed to minimizehost intervention by implementing common SCSI se-quences in hardware. An on-chip state machine re-

duces protocol overheads by performing the requiredsequences in response to a single command from thehost. Selection, reselection, information transfer anddisconnection commands are directly supported.

The 16-byte-internal FIFO further assists in minimizinghost involvement. The FIFO provides a temporary stor-age for all command, data, status and message bytes asthey are transferred between the 16 bit host data busand the 8 bit SCSI data bus. During DMA operations theFIFO acts as a buffer to allow greater latency in the DMAchannel. This permits the DMA channel to be sus-pended for higher priority operations such as DRAM re-fresh or reception of an ISDN packet.

Parity on the DMA bus is optional. Parity can either begenerated and checked or it can be simply passedthrough.

The patented GLITCH EATER Circuitry in the High Per-formance SCSI Controller detects signal changes thatare less than or equal to 15 ns and filters them out. It isdesigned to dramatically increase system performanceand reliability by detecting and filtering glitches that cancause system failure.

The GLITCH EATER Circuitry is implemented on theACKandREQlines only. These lines often encountermany electrical anomalies which degrade system per-formance and reliability. The two most common are Re-flections and Voltage Spikes. Reflections are a result ofhigh current SCSI signals that are mismatched by stubs,cables and terminators. These reflections vary from ap-plication to application and can trigger false handshakesignals on theACKandREQlines if the voltage ampli-tude is at the TTL threshold levels. Spikes are generatedby high current SCSI signals switching concurrently. Onthe control signals (ACKandREQ) they can trigger falsedata transfers which result in loss of data, addition ofrandom data, double clocking and reduced system reli-ability. AMDs GLITCH EATER Circuitry helps maintainexcellent system performance by treating the glitches.Refer to the diagram on the next page.


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P R E L I M I N A R YAMD

2 Am53C94/Am53C96

SCSI Environment

Valid Signal Glitches

>15 ns


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P R E L I M I N A R Y AMD

3Am53C94/Am53C96

SYSTEM BUS MODE DIAGRAMS

16506C-3

8-Bit Data Bus

Address Bus

DMAController

HostProcessor

Am53C94/96

BusControllerDMA 70

A 30

RD

WR

DMAWR

BUSMD 0

BUSMD 1

DREQDACK

Bus Mode 0

16506C-4

Data Bus

Address Bus

RD

WR

DMAWR

DREQDACK

DMAController

HostProcessor

Am53C94/96

BusController

DMA 150

A 30

BUSMD 0

BUSMD 1

816

VDD

Bus Mode 1


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4 Am53C94/Am53C96

SYSTEM BUS MODE DIAGRAMS

DMARD

VDD

8-Bit Data Bus

16506C-5

DMAController

HostProcessor

Am53C94/96

DMA 150

AD 70

WR

DMAWR

BUSMD 0

BUSMD 1

DREQ

DACK

RD

BHE

AS0

ALE

16-Bit Data Bus

Bus Mode 2

VDD

Address Bus

16506C-6

DMAController

HostProcessor

Am53C94/96

DMA 150

A 30

WR

DMAWR

BUSMD 0

BUSMD 1

DREQ

DACK

RD

16-Bit Data Bus

8-Bit Data Bus

AD 70

Bus Mode 3


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5Am53C94/Am53C96

BLOCK DIAGRAM

16506C-7

Bus

Interface

Un

it

18 1816 x 9 FIFO(including parity)

Parity Logic

Da

ta

Trance

ivers

SCSICon

tro

lMUX

8

8

8

9

CLK

6

4

DMA15-0

DMAP1-0

DMA Control

AD7-0

Host Control

BUSMD1-0

RESET

CS

9SCSI Control

SCSI BusData + Parity(Single Ended)

MainSequencer

SCSISequencer

RegisterBank

DFMODE

9SCSI BusData + ParityDirection Control

7 SCSI ControlDirection Control


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6 Am53C94/Am53C96

CONNECTION DIAGRAMS

Top View

16506C-8

DMA11

DMA10

DMA9

DMA8

DMA7

DMA3

DMA2

DMA1

DMA0

DMA4

DMAP0

DMAP1

DMA14

DMA13

DMA12

DMA15

DMA5

DMA6

AD3

AD2

AD1

AD0

CLK

ALE [A3]

DMARD[A2]

BHE [A1]

AS0 [A0]

AD4

AD5

DREQ

DACK

DMAWR

AD6

AD7

CS

RD

WR

BSYC

REQC

MSG

C/DI/O

ATN

RSTC

SEL

BSY

REQ

ACK

RST

BUSMD

0

INT

RESET

SELC

BUSMD

1

ACKC

12

13

1415

16

17

18

19

20

21

22

23

24

25

26

27

28

2930

31

32

74

73

7271

70

69

68

67

66

65

64

63

62

61

59

58

5756

55

54

60

33 34 3 5 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

Am53C9484-Pin PLCC

SD6

SD7

SDP

VDD

VSS

VSS

SD3

SD4

SD5

SD0

SD1

SD2

SDC3

SDC0

SDC1

SDC2

SDC6

SDC7

SDCP

SDC4

SDC5

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

NC

ISEL

TSEL

DMA0

DMA1

DMA2

DMA3

DMA4

DMA5

DMA6

DMA7

DMAP0

DMA8

DMA9

DMA10

DMA11

DMA12

DMA13

DMA14

DMA15

DMAP1

NC

SD0

SD1

DACK

DMAWR

NC

S

DC

7

SDC

P

BUSMD

0

BUSMD

1

RST

ACK

REQ

SEL

ATN

I/O C/D

MSG

ACKC

REQC

BSYC

VSS

RSTC

BSY

RD

NC

RESET

INT

WR

SELC

VSS

NC

SDC6CS

AS0 [A0]

BHE [A1]

DMARD[A2]

ALE [A3]

CLK

DFMODE

NC

AD0

AD1

AD2

AD3

VSS

VSS

AD4

AD5

AD6

AD7

DREQ

VSS

VSS

VSS

VSS

VSS

VSS

VDD

VDD

SDC0

SDC1

SDC2

SDC3

SDC4

SDC5

SD2

SD3

VSS

VSS

SD4

SD5

SD6

SD7

SDP

VSS

VSS

31

32

33

34

35

36

37

38

39

40

41

42

43

45

46

47

48

49

50

44

Am53C96

100-Pin PQFP

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

291 2 3 4 5 6 7 8 9 1 0 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30

5280 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 51

VSS

VSS

16506C-9


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7Am53C94/Am53C96

LOGIC SYMBOL

SDCP

BUSMD10

*DFMODE

INT

CS

WR

RD

Am53C94/96

SD70

SDP

BSYC

MSG

C/DI/O

ATN

SELC

RSTC

REQC

ACKC

SDC70

BSY

SEL

RST

REQ

ACK

*ISEL

*TSEL

DMA150

DMAP10

DREQ

BHE [A1]

AS0 [A0]

ALE [A3]

AD70

DMARD[A2]

DACK

DMAWR

CLK

RESET

Note:

*Pins available on the Am53C96 only.16506C-10

RELATED AMD PRODUCTS

Part Number Description

85C30 Enhanced Serial CommuncaitonController

26LSXX Line Drivers/Receivers

33C93A Enhanced CMOS SCSI BusInterface Controller

80C186 Highly Integrated 16-BitMicroprocessor

80C286 High-Performance 16-Bit80286 Microprocessor

Part Number Description

Am386TM

High-Performance 32-BitMicroprocessor

80188 Highly Integrated 8-Bit Microprocessor

53C80A SCSI Bus Controller

85C80 Combination 53C80A SCSI and85C30 ESCC

53C94LV Low Voltage, High PerformanceSCSI Controller


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8 Am53C94/Am53C96

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) isformed by a combination of:

TEMPERATURE RANGEC = Commercial

PACKAGE TYPEJ = 84-Pin PLCC (PL 084)K = 100-Pin PQFP (PQR100)

DEVICE NUMBER/DESCRIPTIONAm53C94/Am53C96High Performance SCSI Conroller

AM53C94

AM53C96

AM53C96 K C

Valid Combinations

Valid Combinations list configurations planned to besupported in volume for this device. Consult the lo-cal AMD sales office to confirm availability of specificvalid combinations or to check on newly releasedcombinations.

JC

KC, KC/W

Valid Combinations

ALTERNATE PACKAGING OPTION/W = Trimmed and Formed in a Tray (PQJ100)Blank = Molded Carrier Ring (35 mm)

/W


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9Am53C94/Am53C96

SCSI OUTPUT CONNECTIONS

Am53C94

Am53C94 Single Ended SCSI Bus Configuration

SDC70, P

SELC,BSYC,REQC,ACKC,RSTC

SD70, P

SEL,BSY,REQ,ACK,RST

MSG,C/D,I/O,ATN

16506C-11


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10 Am53C94/Am53C96

SCSI OUTPUT CONNECTIONS

Am53C96

Am53C96 Single Ended SCSI Bus Configuration

SDC70, P

SELC,BSYC,REQC,ACKC,RSTC

SD70, P

SEL,BSY,REQ,ACK,RST

MSG,C/D,I/O,ATN

DFMODE VCC

16506C-12

SDC70, P

SELC,BSYC,RSTC

SD70, P

SEL,BSY,RST

MSG,C/D,I/O,REQ

DFMODE

ATN,ACK

Am53C96 Differential SCSI Bus Configuration

TSEL

ISEL

Am53C96DT

DT

DT

DT

16506C-13


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11Am53C94/Am53C96

TSEL

Vcc

Differential Transceiver Connections for the Differential SCSI Bus ConfigurationUsing 75ALS170 and 75ALS171 Transceivers

VccSELC

GND

SEL+ SEL

SEL

BSYC

GND

BSY+ BSY BSY

RSTC

GND

RST+ RST RST

GND

75ALS171

SDC 6SD6

SD 6

+ SD 6

SDC7

SD7

SD 7

+ SD 7

SDCP

SD P

SD P

+ SD P

75ALS170

SDC3

SD3

SD 3

+ SD 3

SDC 4

SD 4

SD 4+ SD 4

SDC5

SD 5

SD 5

+ SD 5

75ALS170

SDC 0

SD0

SD 0+ SD 0

SDC 1

SD 1

SD 1+ SD 1

SDC2

SD2

SD 2+ SD 2

75ALS170

ATN

ISEL

ATN+ ATN

75ALS170

MSG+ MSG

C/D

TSEL

MSG

TSEL

C/D

+ C/D

TSELI/O

I/O+ I/O

75ALS170

REQC

ACKC

REQ+ REQ

REQ

ISEL

ACK+ ACK

ACK

75ALS171

GND

16506C-14


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12 Am53C94/Am53C96

SDC 6

SD 6

Differential Transceiver Connections for the DifferentialSCSI Bus Configuration Using 75176A Transceiver

SD 6

+ SD 6SD 6

SDC 6

RSTC

GND

RST + RST

RST

GND

SDC0

SD0

SD 0

+ SD 0

SDC 0

SD0

TSEL

MSG

MSG

+ MSGMSG

TSEL

SDC1

SD 1

SD 1

+ SD 1SD1

SDC 1

TSEL

C/D

C/D

+ C/DC/D

TSEL

SDC 2

SD2

SD 2

+ SD 2SD2

SDC2

TSEL

I/O

I/O

+ I/OI/O

TSEL

SDC 3

SD3

SD 3+ SD 3SD3

SDC 3

ISEL

ATN

ATN+ ATNATN

ISEL

SDC 4

SD 4

SD 4

+ SD 4SD 4

SDC 4

SELC

GND

SEL+ SEL

SEL

GND

SDC 5

SD 5

SD 5

+ SD 5SD 5

SDC 5

BSYC

GND

BSY + BSY

BSY

GND

SDC 7

SD 7

SD 7

+ SD 7SD 7

SDC7

TSEL

REQC

REQ+ REQ

REQ

GND

SDCP

SDP

SD P

+ SD PSD P

SDCP

ISEL

ACKC

ACK+ ACK

ACK

GND

16506C-15


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13Am53C94/Am53C96

PIN DESCRIPTION

Host Interface Signals

DMA 150Data/DMA Bus(Input/Output, Active High, Internal Pull-up)

The configuration of this bus depends on the Bus Mode

10 (BUSMD 10) inputs. When the device is config-ured for a single bus operation, the host can access theinternal register set on the lower eight lines and the DMAaccesses can be made to the FIFO using entire bus.When using the Byte Mode via the BHE and A0 inputsthe data can be transferred on either the upper or lowerhalf of the DMA 150 bus.

DMAP 10Data/DMA Parity Bus(Input/Output, Active High, Internal Pull-up)

These lines are odd parity for the DMA 150 bus. DMAP1 is the parity for the upper half of the bus DMA 158 andDMAP 0 is the parity for the lower half of the bus

DMA 70.

ALE [A3]Address Latch Enable [Address 3](Input, Active High)

This is a dual function input. When the device is config-ured for the dual bus mode (two buses, multiplexed andbyte control), this input acts as ALE. As ALE, this inputlatches the address on the AD 70 bus on its Low goingedge. When the device is configured for all other busmodes, this input acts as A3. As A3, this input is the thirdbit of the address bus.

DMARD[A2]DMA Read [Address 2](Input, Active Low [Active High])

This is a dual function input. When the device is config-ured for the dual bus mode (two buses, multiplexed andbyte control), this input acts as DMARD. AsDMARD,this input is the read signal for the DMA 150 bus. Whenthe device is configured for all other bus modes, this in-put acts as A2. As A2, this input is the second bit of theaddress bus.

BHE [A1]

Bus High Enable [Address 1](Input, Active High)

This is a dual function input. When the device is config-ured for the dual bus mode (two buses, multiplexed andbyte control), this input acts as BHE. As BHE, this inputworks in conjunction with AS0 to indicate the lines onwhich data transfer will take place. When the device isconfigured for all other bus modes this input acts as A1.As A1, this input is the first bit of the address bus.

AS0 [A0]

Address Status [Address 0](Input, Active High)

This is a dual function input. When the device is config-ured for the dual bus mode (two buses, multiplexed andbyte control), this input acts as AS0. As AS0, this input

works in conjunction with BHE to indicate the lines onwhich data transfer will take place. When the device isconfigured for all other bus modes, this input acts as A0.As A0, this input is the zeroth bit of the address bus.

The following is the decoding for the BHE and AS0inputs:

BHE AS0 Bus Used

1 1 Upper Bus DMA 158, DMAP 1

1 0 Full Bus DMA 150, DMAP 10

0 1 Reserved

0 0 Lower Bus DMA 70, DMAP 0

DREQDMA Request(Output, Active High, Hi-Z)

This output signal to the DMA controller will be activeduring DMA read and write cycles. During a DMA readcycle it will be active as long as there is a word (or a bytein the byte mode) in the FIFO to be transferred to mem-ory. During a DMA write cycle it will be active as long asthere is an empty space for a word (or a byte in the bytemode) in the FIFO.

DACKDMA Acknowledge(Input, Active Low)

This input signal from the DMA controller will be activeduring DMA read and write cycles. TheDACKsignal isused to access the DMA FIFO only and should never beactive simultaneously with the CS signal, which ac-cesses the registers only.

AD 70Host Address Data Bus(Input/Output, Active High, Internal Pull-up)

This bus is used only in the dual bus mode. This bus al-lows the host processor to access the devices internalregisters while the DMA bus is transferring data. Whenusing multiplexed bus, these lines can be used for ad-dress and data. When using non multiplexed bus theselines can be used for the data only.


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14 Am53C94/Am53C96

DMAWR

DMA Write(Input, Active Low)

This signal writes the data on the DMA 150 bus into theinternal FIFO whenDACKis also active. When in thesingle bus mode this signal must be tied to the WRsignal.

RD

Read(Input Active Low)

This signal reads the internal device registers andplaces their contents on the data bus, when eitherCSsignal orDACKsignal is active.

WR

Write(Input Active Low)

This signal writes the internal device registers with thevalue present on the data bus, when theCSsignal is

also active.

CS

Chip Select(Input Active Low)

This signal enables the read and write of the device reg-isters.CSenables access to any register (including theFIFO) while theDACKenables access only to the FIFO.CSandDACKshould never be active simultaneously inthe single bus mode, they may however be active simul-taneously in the dual bus mode provided theCSsignal isnot enabling access to the FIFO.

INT

Interrupt(Output, Active Low, Open Drain)

This signal is a non maskable interrupt flag to the hostprocessor. This signal is latched on the output on thehigh going edge of the clock. This flag may be cleared byreading the Interrupt Status Register (ISTAT) or by per-forming a device reset (hard or soft). This flag is notcleared by a SCSI reset.

DFMODE

Differential Mode(Input, Active Low)

This input is available only on the Am53C96. This inputconfigures the SCSI bus to either single ended or differ-ential mode. When this input is active, the device oper-ates in the differential SCSI mode. The SCSI data isavailable on theSD70 lines and the high active trans-ceiver enables on theSDC70 outputs. When this inputis inactive, the device operates in the single ended SCSImode. The SCSI input data is available onSD70 linesand the output data is available onSDC 70 lines. In thesingle ended SCSI mode, theSD70 and theSDC70buses can be tied together externally.

BUSMD 10Bus Mode(Input, Active High)

These inputs configure the device for single bus or dualbus operation and the DMA width.

BUSMD1 BUSMD0 Bus Configuration

1 1 Two buses: 8-bit Host Busand 16-bit DMA BusRegister Address on A 30and Data on AD Bus

1 0 Two buses: Multiplexedand byte controlRegister Address on AD 30and Data on AD Bus

0 1 Single bus: 8-bit Host Busand 16-bit DMA BusRegister Address on A 30and Data on DMA Bus

0 0 Single bus: 8-bit Host Busand 8-bit DMA BusRegister Address on A 30and Data on DMA Bus

CLKClock(Input)

Clock input used to generate all the internal device tim-ings. The maximum frequency of this input is 25 MHz.and a minimum of 10 MHz to maintain the SCSI bustimings.

RESETReset(Input, Active High)

This input when active resets the device. The RESET in-put must be active for at least two CLK periods after thevoltage on the power inputs have reached Vccminimum.

SCSI Interface Signals

SD70SCSI Data(Input/Output, Active Low, Schmitt Trigger)

When the device is configured in the Single Ended SCSIMode (DFMODEinactive) these pins are defined as in-puts for the SCSI data bus. When the device is config-ured in the Differential SCSI Mode (DFMODE active)these pins are defined as bidirectional SCSI data bus.


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15Am53C94/Am53C96

SDP

SCSI Data Parity(Input/Output, Active Low, Schmitt Trigger)

When the device is configured in the Single Ended SCSIMode (DFMODEinactive) this pin is defined as the inputfor the SCSI data parity. When the device is configuredin the Differential SCSI Mode (DFMODEactive) this pinis defined as bidirectional SCSI data parity.

SDC 70SCSI Data Control(Output, Active Low, Open Drain)

When the device is configured in the Single Ended SCSIMode (DFMODEinactive) these pins are defined as out-puts for the SCSI data bus. When the device is config-ured in the Differential SCSI Mode (DFMODEactive)these pins are defined as direction controls for the exter-nal differential transceivers. In this mode, a signal highstate corresponds to an output to the SCSI bus and alow state corresponds to an input from the SCSI bus.

SDCPSCSI Data Control Parity(Output, Active Low, Open Drain)

When the device is configured in the Single Ended SCSIMode (DFMODEinactive) this pin is defined as an out-put for the SCSI data parity. When the device is config-ured in the Differential SCSI Mode (DFMODEactive)this pin is defined as the direction control for the externaldifferential transceiver. In this mode, a signal high statecorresponds to an output to the SCSI bus and a lowstate corresponds to an input from the SCSI bus.

MSG

Message(Input/Output, Active Low, Schmitt Trigger)

This is a bidirectional signal with 48 mA output driver. Itis an output in the target mode and a Schmitt trigger in-put in the initiator mode.

C/D

Command/Data(Input/Output, Schmitt Trigger)


I/OInput/Output(Input/Output, Schmitt Trigger)


ATN

Attention(Input/Output, Active Low, Schmitt Trigger)

This signal is a 48 mA output in the initiator mode and aSchmitt trigger input in the target mode. This signal willbe asserted when the initiator detects a parity error or itcan be asserted via certain initiator commands.

BSY

Busy(Input, Active Low, Schmitt Trigger)

This is a SCSI input signal with a Schmitt trigger.

SEL

Select(Input, Active Low, Schmitt Trigger)


RST

Reset

(Input, Active Low, Schmitt Trigger)This is a SCSI input signal with a Schmitt trigger.

REQ

Request(Input, Active Low, Schmitt Trigger)


ACK

Acknowledge(Input, Active Low, Schmitt Trigger)


BSYC

Busy Control(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. When the deviceis configured in the Single Ended SCSI Mode (DFMODEinactive) this pin is defined as a BSY output for the SCSIbus. When the device is configured in the DifferentialSCSI Mode (DFMODEactive) this pin is defined as thedirection control for the external differential transceiver.In this mode, a signal high state corresponds to an out-put to the SCSI bus and a low state corresponds to aninput from the SCSI bus.


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16 Am53C94/Am53C96

SELC

Select Control(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. When the deviceis configured in the Single Ended SCSI Mode (DFMODEinactive) this pin is defined as aSELoutput for the SCSIbus. When the device is configured in the DifferentialSCSI Mode (DFMODEactive) this pin is defined as thedirection control for the external differential transceiver.In this mode, a signal high state corresponds to an out-put to the SCSI bus and a low state corresponds to aninput from the SCSI bus.

RSTC

Reset Control(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. The Reset SCSIcommand will cause the device to driveRSTCactive for25 ms40 ms, which will depend on the CLK frequencyand the conversion factor. When the device is config-ured in the Single Ended SCSI Mode (DFMODEinac-

tive) this pin is defined as a RST output for the SCSI bus.When the device is configured in the Differential SCSIMode (DFMODEactive) this pin is defined as the direc-tion control for the external differential transceiver. Inthis mode, a signal high state corresponds to an outputto the SCSI bus and a low state corresponds to an inputfrom the SCSI bus.

REQC

Request Control(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is ac-tivated only in the target mode.

ACKC

Acknowledge Control(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is ac-tivated only in the initiator mode.

ISELInitiator Select(Output, Active High)

This signal is available on the Am53C96 only. This sig-nal is active whenever the device is in the initiator mode.In the differential mode this signal is used to enable theinitiator signals ACKC and ATNand the device alsodrives these signals.

TSELTarget Select(Output, Active High)

This signal is available on the Am53C96 only. This sig-nal is active whenever the device is in the target mode.In the differential mode this signal is used to enable thetarget signalsREQC,MSG,C/DandI/Oand the devicealso drives these signals.

FUNCTIONAL DESCRIPTION

Register Map

Address(Hex.) Operation Register

00 Read Current Transfer CountRegister LSB

00 Write Start Transfer Count RegisterLSB

01 Read Current Transfer CountRegister MSB

01 Write Start Transfer Count RegisterMSB

02 Read/Write FIFO Register

03 Read/Write Command Register

04 Read Status Register

04 Write SCSI Destination ID Register05 Read Interrupt Status Register

05 Write SCSI Timeout Register

Address(Hex.) Operation Register

06 Read Internal State Register

06 Write Synchronous Transfer PeriodRegister

07 Read Current FIFO/Internal StateRegister

07 Write Synchronous Offset Register

08 Read/Write Control Register 1

09 Write Clock Factor Register

0A Write Forced Test Mode Register

0B Read/Write Control Register 2

0C Read/Write Control Register 3

0F Write Data Alignment Register

Note:

Not all registers in this device are both readable and writable. Some read only registers share the same address with write onlyregisters. The registers can be accessed by asserting theCSsignal and then asserting eitherRD orWRsignal depending on theoperation to be performed. Only the FIFO Register can be accessed by asserting eitherCSorDACKin conjunction withRDandWRsignals orDMARDandDMAWRsignals. The register address inputs are ignored whenDACKis used but must be validwhenCSis used.


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17Am53C94/Am53C96

Current Transfer Count Register(00H01H) Read Only

Current Transfer Count RegisterCTCREG

Address: 00H01HType: Read

15 14 13 12 11 10 9 8

CRVL15 CRVL14 CRVL13 CRVL12 CRVL11 CRVL10 CRVL9 CRVL8

x x x x x x x x

7 6 5 4 3 2 1 0

CRVL7 CRVL6 CRVL5 CRVL4 CRVL3 CRVL2 CRVL1 CRVL0

x x x x x x x x

16506C-16

CTCREG Bits 15:0 CRVL 15:0 CurrentValue 15:0

This is a two-byte register. It counts down to keep trackof the number of DMA transfers. Reading this registerswill return the current value of the counter. The counterwill decrement by one for every byte transferred and twofor every word transferred over the SCSI bus. The trans-action is complete when the count reaches zero. Theseregisters are automatically loaded with the values in theStart Transfer Count Register every time a DMA com-mand is issued.

In the target mode, this counter is decremented by theactive edge ofDACKduring the Data-In phase and byREQCduring the Data-Out phase.

In the initiator mode, the counter is decremented by the

active edge ofDACKduring the Synchronous Data-Inphase or byACKC during the Asynchronous Data-Inphase and byDACKduring the Data-Out phase.

Start Transfer Count Register (00H01H)Write Only

Start Transfer Count RegisterSTCREG

Address: 00H01HType: Write

15 14 13 12 11 10 9 8

STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8

x x x x x x x x

7 6 5 4 3 2 1 0

STVL7 STVL6 STVL5 STVL4 STVL3 STVL2 STVL1 STVL0

x x x x x x x x

16506C-017

STCREG Bits 15:0 STVL 15:0 Start Value 15:0

This is a two-byte register. It contains the number ofbytes to be transferred during a DMA operation. Thevalue of this register is set to the number of bytes to betransferred prior to a DMA transfer command. This reg-ister retains its programmed value until it is overwrittenand is not affected by hardware or software reset.Therefore, it is not necessary to reprogram the count for

subsequent DMA transfers of the same size. Writing azero to this register sets a maximum transfer count of65536 bytes. The value in this register is undefined atpower-up.

FIFO Register (02H) Read/Write

FIFO RegisterFFREG

Address: 02HType: Read/Write

7 6 5 4 3 2 1 0

FF7 FF6 FF5 FF4 FF3 FF2 FF1 FF0

0 0 0 0 0 0 0 0

16506C-18

FFREG Bits 7:0 FF 7:0 FIFO 7:0

The bottom of the 16x9 FIFO is mapped into the FIFORegister address. By reading and writing this registerthe bottom of the FIFO can be read or written. This is theonly register that can also be accessed byDACKalongwithDMARDorDMAWR. This register is reset to zeroby hardware or software reset and also at the start of aselection or reselection sequence.

Command Register (03H) Read/Write

Command RegisterCMDREG


7 6 5 4 3 2 1 0

DMA CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

x x x x x x x x

Command 6:0

Direct Memory

Access

16506C-019

Commands to the device are issued by writing to thisregister. This register is two deep which allows for com-mand queuing. The second command can be issued be-fore the first one is completed. The Reset command andthe Stop DMA command are not queued and are exe-cuted immediately. Reading this register will return thecommand currently being executed (or the last com-mand executed if there are no pending commands).


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18 Am53C94/Am53C96

CMDREG Bit 7 DMA Direct Memory Access

The DMA bit when set notifies the device that the com-mand is a DMA instruction, when reset it is a non-DMAinstruction. For DMA instructions the Current TransferCount Register (CTCREG) will be loaded with the con-tents of the Start Transfer Count Register (STCREG).The data is then transferred and the CTCREG is decre-mented for each byte until it reaches zero.

CMDREG Bits 6:0 CMD 6:0 Command 6:0

These command bits decode the commands that thedevice needs to perform. There are a total of 29commands grouped into four categories. The groupsare Initiator Commands, Target Commands, Selection/Reselection Commands and General Purpose Com-mands.

Initiator Commands

CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 Command

0 0 1 0 0 0 0 Information Transfer

0 0 1 0 0 0 1 Initiator Command Complete Steps

0 0 1 0 0 1 0 Message Accepted

0 0 1 1 0 0 0 Transfer Pad Bytes

0 0 1 1 0 1 0 Set ATN

0 0 1 1 0 1 1 Reset ATN

Target Commands


0 1 0 0 0 0 0 Send Message

0 1 0 0 0 0 1 Send Status

0 1 0 0 0 1 0 Send Data

0 1 0 0 0 1 1 Disconnect Steps

0 1 0 0 1 0 0 Terminate Steps

0 1 0 0 1 0 1 Target Command Complete Steps

0 1 0 0 1 1 1 Disconnect

0 1 0 1 0 0 0 Receive Message Steps

0 1 0 1 0 0 1 Receive Command

0 1 0 1 0 1 0 Receive Data0 1 0 1 0 1 1 Receive Command Steps

0 0 0 0 1 0 0 DMA Stop

Idle Commands


1 0 0 0 0 0 0 Reselect Steps

1 0 0 0 0 0 1 Select without ATN Steps

1 0 0 0 0 1 0 Select with ATN Steps

1 0 0 0 0 1 1 Select with ATN and Stop Steps

1 0 0 0 1 0 0 Enable Selection/Reselection

1 0 0 0 1 0 1 Disable Selection/Reselection

1 0 0 0 1 1 0 Select with ATN3 Steps

General Commands


0 0 0 0 0 0 0 No Operation

0 0 0 0 0 0 1 Clear FIFO

0 0 0 0 0 1 0 Reset Device

0 0 0 0 0 1 1 Reset SCSI Bus


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19Am53C94/Am53C96

Status Register (04H) Read

Status RegisterSTATREG

Address: 04HType: Read

7 6 5 4 3 2 1 0

INT IOE PE CTZ GCV MSG C/D I/O

0 0 0 0 0 x x x

Illegal Operation Error

Parity Error

Count to Zero

Group Code Valid

Message

Command/Data

Input/Output

Interrupt

16506C-20

This read only register contains flags to indicate thestatus and phase of the SCSI transactions. It indicateswhether an interrupt or error condition exists. It shouldbe read every time the host is interrupted to determinewhich device is asserting an interrupt. The data islatched until the Interrupt Status Register is read. Thephase bits will be latched only if latching is enabled in theControl Register 2, otherwise, it will indicate the currentSCSI phase. If command stacking is used, two inter-rupts might occur. Reading this register will clear thestatus information for the first interrupt and update theStatus Register for the second interrupt.

STATREG Bit 7 INT Interrupt

The INT bit is set when the device asserts the interruptoutput. This bit will be cleared by a hardware or software

reset. Reading the Interrupt Status Register will deas-sert the interrupt output and also clear this bit.

STATREG Bit 6 IOE Illegal Operation Error

The IOE bit is set when an illegal operation is attempted.This condition will not cause an interrupt, it will be de-tected by reading the status register while servicing an-other interrupt. The following conditions will cause theIOE bit to be set:

DMA and SCSI transfer directions are opposite.

FIFO overflows.

In initiator mode an unexpected phase changedetected during synchronous data transfer.

Command Register overwritten.

This bit will be cleared by reading the Interrupt StatusRegister or by a hard or soft reset.

STATREG Bit 5 PE Parity Error

The PE bit is set if the parity checking option is enabledin Control Register 1 and the device detects a parity er-ror on incoming SCSI data, command, status or mes-

sage bytes. Detection of a parity error condition will notcause an interrupt but will be reported with other inter-rupt causing conditions. When a parity error is detectedin the information phase of the initiator modeATNis as-serted on the SCSI bus.

This bit will be cleared by reading the Interrupt StatusRegister or by a hard or soft reset.

STATREG Bit 4 CTZ Count To Zero

The CTZ bit is set when the Current Transfer CountRegister (CTCREG) has counted down to zero. This bitwill be reset when the CTCREG is written.

Reading the Interrupt Status Register will not affect thisbit. This bit will however be cleared by a hard or soft re-set.

Note:

A non-DMA NOP will not reset the CTZ bit since it doesnot load the CTCREG but a DMA NOP will reset this bitsince it loads the CTCREG.

STATREG Bit 3 GCV Group Code Valid

The GCV bit is set if the group code field in the Com-mand Descriptor Block (CDB) is one that is defined bythe ANSI Committee in their document X3.131 1986. Ifthe SCSI-2 Feature Enable (S2FE) bit in the ControlRegister 2 (CNTLREG2) is set, Group 2 commands willbe treated as ten byte commands and the GCV bit will beset. If S2FE is reset then Group 2 commands will betreated as reserved commands. Group 3 and 4 com-

mand will always be considered as reserved com-mands. The device will treat all reserved commands assix byte commands. Group 6 commands will always betreated as vendor unique six byte commands and Group7 commands will always be treated as vendor uniqueten byte commands.

The GCV bit is cleared by reading the Interrupt StatusRegister (INSTREG) or by a hard or soft reset.


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20 Am53C94/Am53C96

STATREG Bit 2 MSG Message

STATREG Bit 1 C/D Command/Data

STATREG Bit 0 I/O Input/Output

Bit2 Bit1 Bit0MSG C/D I/O SCSI Phase

1 1 1 Message In

1 1 0 Message Out

1 0 1 Reserved

1 0 0 Reserved

0 1 1 Status

0 1 0 Command

0 0 1 Data_In

0 0 0 Data_Out

The MSG, C/D and I/O bits together can be referred toas the SCSI Phase bits. They indicate the phase of theSCSI bus. These bits may be latched or unlatched de-pending on the option selected in Control Register 2(CNTLREG2) by the Latch SCSI Phase (LSP) bit.

In the latched mode the SCSI phase bits are latched atthe end of a command and the latch is opened when theInterrupt Status Register (INSTREG) is read. In the un-

latched mode, they indicate the phase of the SCSI buswhen this register is read.

SCSI Destination ID Register (04H) Write

RES RES RES RES RES

0 0 0 0 0

SCSI Destination ID RegisterSDIDREG

Address: 04HType: Write

7 6 5 4 3 2 1 0

DID2 DID1 DID0

x x x

Reserved

Reserved

Reserved

Reserved

SCSI Destination ID 2:0

Reserved16506C-21

SDIDREG Bits 7:3 RES Reserved

SDIDREG Bits 2:0 DID 2:0 Destination ID 2:0

The DID 2:0 bits are the encoded SCSI ID of the deviceon the SCSI bus which needs to be selected orreselected.

DID2 DID1 DID0 SCSI ID

1 1 1 7

1 1 0 6

1 0 1 5

1 0 0 4

0 1 1 3

0 1 0 2

0 0 1 1

0 0 0 0

At power-up the state of these bits is undefined. The DID 2:0bits are not affected by reset.


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21Am53C94/Am53C96

Interrupt Status Register (05H) Read

SRST ICMD DIS SR SO

0 0 0 0 0

Interrupt Status RegisterINSTREG

Address: 05hType: READ

7 6 5 4 3 2 1 0

RESEL SELA SEL

0 0 0

Invalid Command

Disconnected

Service Request

Successful Operation

Selected with Attention

SCSI Reset16506C-22

Selected

Reselected

The Interrupt Status Register (INSTREG) will indicatethe reason for the interrupt. This register is used with the

Status Register (STATREG) and Internal Status Regis-ter (ISREG) to determine the reason for the interrupt.Reading the INSTREG will clear all three registers.

INSTREG Bit 7 SRST SCSI Reset

The SRST bit will be set if a SCSI Reset is detected andSCSI reset reporting is enabled via the DISR (bit 6) ofthe CNTLREG1.

INSTREG Bit 6 ICMD Invalid Command

The ICMD bit will be set if the device detects an illegalcommand code. This bit is also set if a command codefrom a different mode is detected than the mode the de-vice is currently in.

INSTREG Bit 5 DIS Disconnected

The DIS bit can be set in the target or the initiator modewhen the device disconnects from the SCSI bus. In thetarget mode this bit will be set if a terminate or a com-mand complete sequence causes the device to discon-nect from the SCSI bus. In the Initiator mode this bit willbe set if the target disconnects or a selection or reselec-tion timeout occurs.

INSTREG Bit 4 SR Service Request

The SR bit can be set in the target or the initiator modewhen another device on the SCSI bus has a service re-

quest. In the target mode this bit will be set when the in-itiator asserts theATNsignal. In the Initiator mode this

bit is set whenever the target requests an informationtransfer phase.

INSTREG Bit 3 SO Successful Operation

The SO bit can be set in the target or the initiator modewhen an operation is successfully complete. In thetarget mode this bit will be set when any target modecommand is completed. In the initiator mode this bit isset after a target has been successfully selected, after acommand is successfully completed and after an infor-mation transfer command when the target requests amessage in phase.

INSTREG Bit 2 RESEL Reselected

The RESEL bit is set at the end of the reselection phaseindicating that the device has been reselected as an in-itiator.

INSTREG Bit 1 SELA Selected with Attention

The SELA bit is set at the end of the selection phase indi-cating that the device has been selected and that theATNsignal was active during the selection.

INSTREG Bit 0 SEL Selected

The SEL bit is set at the end of the selection phase indi-cating that the device has been selected and that theATNsignal was inactive during the selection.


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22 Am53C94/Am53C96

SCSI Timeout Register (05H) Write

SCSI Timeout RegisterSTIMREG


7 6 5 4 3 2 1 0

STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 STIM1 STIM0

x x x x x x x x

16506C-23

This register determines how long the initiator (target)will wait for a target to respond to a selection (reselec-tion) before timing out. It should be set to yield 250 ms tocomply with ANSI standards for SCSI.

STIMREG Bits 7:0 STIM 7:0 SCSI Timer 7:0

The value loaded in STIM 7:0 can be calculated from thefollowing formula:

STIM 7:0 =

[(SCSI Time Out) (Clock Frequency) / (8192 (ClockFactor))]

Example:

SCSI Time Out (in seconds): 250 ms. (Recommendedby the ANSI Standard) = 250 x 103s.

Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz.

Clock Factor: CLKF 2:0 from Clock Conversion Regis-ter (09H) = 5

STIM 7:0 = (250 x 103)X (20 x 106) / (8192 (5)) = 122decimal

Internal State Register (06H) Read

Internal State Register

ISREG

Address: 06H

Type: Read

7 6 5 4 3 2 1 0

RES RES RES RES SOF IS2 IS1 IS0

x x x x 0 0 0 0

Reserved

Reserved

Reserved

Synchronous Offset Flag

Internal State 2:0

Reserved

16506C-24

The Internal State Register (ISREG) tracks the progressof a sequence-type command. It is updated after eachsuccessful completion of an intermediate operation. Ifan error occurs, the host can read this register to deter-mined at where the command failed and take the neces-sary procedure for recovery. Reading the InterruptStatus Register will clear this register.

ISREG Bits 7:4 RES Reserved

ISREG Bit 3 SOF Synchronous Offset Flag

The SOF is reset when the Synchronous Offset Register(SOFREG) has reached its maximum value.

Note:

The SOF bit is active Low.

ISREG Bits 2:0 IS 2:0 Internal State 2:0

The IS 2:0 bits along with the Interrupt Status Register(INSTREG) indicates the status of the successfullycompleted intermediate operation. Refer to the StatusDecode section for more details.


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23Am53C94/Am53C96

Initiator Select without ATN Steps

Internal State Interrupt StatusRegister (06H) Register (05H) Explanation

Bits 2:0 (Hex) Bits 7:0 (Hex)

0 20 Arbitration steps completed or disconnected or selection timeout

4 18 Selection with ATN steps fully executed

3 18 Sequence halted during command transfer due to premature phase change(target)

2 18 Arbitration and selection completed; sequence halted because target failed toassert command phase

Initiator Select with ATN Steps



4 18 Selection with ATN steps fully executed

3 18 Sequence halted during command transfer due to premature phase change;some CDB bytes may not have been sent; check FIFO flags

2 18 Message out completed; sent one message byte with ATN true, then releasedATN; sequence halted because target failed to assert command phase aftermessage byte was sent

0 18 Arbitration and selection completed; sequence halted because target did not

assert message out phase; ATN still driven by HPSC

Initiator Select with ATN3 Steps




4 18 Selection with ATN3 steps fully executed

3 18 Sequence halted during command transfer due to premature phase change;some CDB bytes may not have been sent; check FIFO flags

2 18 One, two, or three message bytes sent; sequence halted because target failedto assert command phase after third message byte, or prematurely releasedmessage out phase; ATN released only if third message byte was sent

0 18 Arbitration and selection completed; sequence halted because target failed to

assert message out phase; ATN still driven by HPSC

Initiator Select with ATN and Stop Steps




0 18 Arbitration and selection completed; sequence halted because target failed toassert message out phase; ATN still asserted by HPSC

1 18 Message out completed; one message byte sent; ATN on


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24 Am53C94/Am53C96

Target Selected without ATN Steps



2 11 Selected; received entire CDB; check group code valid bit; initiator asserted ATNin command phase

1 11 Sequence halted in command phase due to parity error; some CDB bytes maynot have been received; check FIFO flags; initiator asserted ATN in command

phase2 01 Selected; received entire CDB; check group code valid bit

1 01 Sequence halted in command phase because of parity error; some CDB bytesmay not have been received; check FIFO flags

0 01 Selected; loaded bus ID into FIFO; nullbyte message loaded into FIFO

Target Select with ATN Steps, SCSI2 Bit NOT SET



2 12 Selection complete; received one message byte and entire CDB; initiator as-serted ATN during command phase

1 12 Halted in command phase; parity error and ATN true

0 12 Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause ATN remained true after first message byte2 02 Selection completed; received one message byte and the entire CDB

1 02 Sequence halted in command phase because of parity error; some CDB bytesnot received; check group code valid bit and FIFO flags

0 02 Selected with ATN; stored bus ID and one message byte; sequence halted be-cause of parity error or invalid ID message

Target Select with ATN Steps, SCSI2 Bit SET



5 12 Halted in command phase; parity error and ATN true

4 12 ATN remained true after third message byte

0 02 Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause of parity error or invalid ID message6 02 Selection completed; received three message bytes and the entire CDB

5 02 Received three message bytes then halted in command phase because of parityerror; some CDB bytes not received; check group code valid bit and FIFO flags

402Parity error during second or third message byte

Target Receive Command Steps



2 18 Received entire CDB; initiator asserted ATN

1 18 Sequence halted during command transfer due to parity error; ATN asserted byinitiator

2 08 Received entire CDB

1 08 Sequence halted during command transfer due to parity error; check FIFO flags

Target Disconnect Steps



2 28 Disconnect steps fully executed; disconnected; bus is free

1 18 Two message bytes sent; sequence halted because initiator asserted ATN

0 18 One message byte sent; sequence halted because initiator asserted ATN


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25Am53C94/Am53C96

Target Terminate Steps



2 28 Terminate steps fully executed; disconnected; bus is free

1 18 Status and message bytes sent; sequence halted because initiator assertedATN

0 18 Status byte sent; sequence halted because initiator asserted ATN

Target Command Complete Steps



1 18 Status and message bytes sent; sequence halted because initiator set ATN

0 18 Status byte sent; sequence halted because initiator set ATN

2 08 Command complete steps fully executed


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26 Am53C94/Am53C96

Synchronous Transfer Period Register (06H) Write

6

Synchronous Transfer Period RegisterSTPREG


7 5 4 3 2 1 0

RES RES RES STP4 STP3 STP2 STP1 STP0

x x x 0 0 1 0 1

Reserved

Reserved

Synchronous Transfer Period 4:0

Reserved

16506C-25

The Synchronous Transfer Period Register (STPREG)contains a 5-bit value indicating the number of clock cy-cles each byte will take to be transferred over the SCSI

bus in synchronous mode. The minimum value allowedis 5. The STPREG defaults to five after a hard or softreset.

STPREG Bits 7:5 RES Reserved

STPREG Bits 4:0 STP 4:0 SynchronousTransfer Period 4:0

The STP 4:0 bits are programmed to specify the syn-chronous transfer period or the number of clock cyclesfor each byte transfer in the synchronous mode. Theminimum value for STP 4:0 is five. Missing table entriesfollow the binary code.

Clocks/STP4 STP3 STP2 STP1 STP0 Byte

0 0 1 0 0 5

0 0 1 0 1 5

0 0 1 1 0 6

0 0 1 1 1 7

1 1 1 1 1 31

0 0 0 0 0 32

0 0 0 0 1 33

0 0 0 1 0 34

0 0 0 1 1 35


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27Am53C94/Am53C96

Current FIFO/Internal State Register (07H) Read

Current FIFO/Internal State RegisterCFISREG

Address: 07HType: Read

7 6 5 4 3 2 1 0

IS2 IS1 IS0 CF4 CF3 CF2 CF1 CF0

0 0 0 0 0 0 0 0

Internal State 2:0

Current FIFO 4:0

16506C-26

This register has two fields, the Current FIFO field andthe Internal State field.

CFISREG Bits 7:5 IS 2:0 Internal State 2:0

The Internal State Register (ISREG) tracks the progressof a sequence-type command.

The IS 2:0 bits are duplicated from the IS 2:0 field in theInternal State Register (ISREG) in the normal mode. Ifthe device is in the test mode, IS 0 is set to indicate thatthe offset value is non zero. A non zero value indicates

that synchronous data transfer can continue. A zerovalue indicates that the synchronous offset count has

been reached and no more data can be transferred untilan acknowledge is received.

CFISREG Bits 4:0 CF 4:0 Current FIFO 4:0

The CF 4:0 bits are the binary coded value of the num-ber of bytes in the FIFO. These bits should not be readwhen the device is transferring data since this countmay not be stable.

Synchronous Offset Register (07H) Write

Synchronous Offset RegisterSOFREG


7 6 5 4 3 2 1 0

SO3 SO2 SO1 SO0RES RES RES RES

x x x x 0 0 0 0

Reserved

Reserved

Reserved

Synchronous Offset 3:0

Reserved16506C-27

The Synchronous Offset Register (SOFREG) containsa 4-bit count of the number of bytes that can be sent to(or received from) the SCSI bus without an ACK (orREQ). Bytes exceeding the threshold will be sent onebyte at a time (asynchronously). That is, each byte willrequire anACK/REQhandshake. To set up an asyn-chronous transfer, the SOFREG is set to zero. TheSOFREG is set to zero after a hard or soft reset.

SOFREG Bits 7:4 RES Reserved

SOFREG Bits 3:0 SO 3:0 Synchronous Offset3:0

The SO 4:0 bits are the binary coded value of the num-ber of bytes that can be sent to (or received from) theSCSI bus without anACK(orREQ) signal.


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28 Am53C94/Am53C96

Control Register One (08H) Read/Write

Control Register OneCNTLREG1


7 6 5 4 3 2 1 0

ETM DISR PTE PERE STE CID2 CID1 CID0

0 0 0 0 0 x x x

Disable Interrupt on SCSI Reset

Parity Test Enable

Parity Error Reporting Enable

Self Test Enable

Chip ID 2:0

Extended Timing Mode

16506C-28

The Control Register 1 (CNTLREG1) sets up the device

with various operating parameters.

CNTLREG1 Bit 7 ETM Extended Timing Mode

The ETM bit is set if an extra clock period is required be-tween the data being driven on the bus and theREQorACKbeing asserted. This is some times necessary inhigh capacitive loading environments. The ETM bit is re-set to zero by a hard or soft reset.

CNTLREG1 Bit 6 DISR Disable Interrupt onSCSI Reset

The DISR bit masks the reporting of the SCSI reset.When the DISR bit is set and a SCSI reset is asserted,the device will disconnect from the SCSI bus and remainidle without interrupting the host processor. When theDISR bit is reset and a SCSI reset is asserted the devicewill respond by interrupting the host processor. TheDISR bit is reset to zero by a hard or soft reset.

CNTLREG1 Bit 5 PTE Parity Test Enable

The PTE bit is for test use only. When the PTE bit is setthe parity on the output (SCSI or host processor) bus isforced to the value of the MSB (bit 7) of the output datafrom the internal FIFO. This allows parity errors to becreated to test the hardware and software. The PTE bitis reset to zero by a hard or soft reset.

CNTLREG1 Bit 4 PERE Parity Error Report-

ing EnableThe PERE bit enables the checking and reporting of par-ity errors on incoming SCSI bytes during the informationtransfer phase. When the PERE bit set and a bad parityis detected, the PE bit in the STATREG is will be set butan interrupt will not be generated. In the initiator modetheATNsignal will also be asserted on the SCSI bus.When the PERE bit is reset and a bad parity occurs it isnot detected and no action is taken.

CNTLREG1 Bit 3 STE Self Test Enable

The STE bit is for test use only. When the STE bit is setthe device is placed in a test mode which enables thedevice to access the test register at address 0AH. To re-set this bit and to resume normal operation the devicemust be issued a hard or soft reset.

CNTLREG1 Bit 2:0 CID 2:0 Chip ID 2:0

The Chip ID 2:0 bits specify the binary coded value ofthe device ID on the SCSI bus. The device will arbitratewith this ID and will respond to selection or reselection tothis ID. At power-up the state of these bit are undefined.These bits are not affected by hard or soft reset.


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29Am53C94/Am53C96

Clock Factor Register (09H) Write

3

Clock Factor RegisterCLKFREG


7 6 5 4 2 1 0

RES RES RES RES RES CLKF2 CLKF1 CLKF0

x x x x x 0 1 0

Reserved

Reserved

Reserved

Reserved

Clock Factor 2:0

Reserved16506C-29

The Clock Factor Register (CLKFREG) must be set toindicate the input frequency range of the device. Thisvalue is crucial for controlling various timings to meet the

SCSI specification. The selector can be calculated byrounding off the quotient of (Input Clock Frequency inMHz)/(5 MHz). The device has a frequency range of 10to 25 MHz.

CLKFREG Bits 7:3 RES Reserved

CLKFREG Bits 2:0 CLKF 2:0 Clock Factor 2:0

The CLKF 2:0 bits specify the binary coded value of theclock factor. The CLKF 2:0 bits will default to a value of 2by a hard or soft reset.

Input ClockCLKF2 CLKF1 CLKF0 Frequency in MHz

0 1 0 10

0 1 1 10.01 to 15

1 0 0 15.01 to 20

1 0 1 20.01 to 25

Forced Test Mode Register (0AH) Write

3

Forced Test Mode RegisterFTMREG

Address: 0AHType: Write

7 6 5 4 2 1 0

RES RES RES RES RES FHI FIM FTM

x x x x x 0 0 0

Reserved

Reserved

Reserved

Reserved

Forced High Impedance Mode

Forced Initiator Mode

Forced Target Mode

Reserved

16506C-30

The Forced Test Mode Register (FTMREG) is for testuse only. The STE bit in the CNTLREG1 must be set forthe FTMREG to operate.

FTMREG Bits 7:3 RES Reserved

FTMREG Bit 2 FHI Forced High ImpedanceMode

The FHI bit when set places all the output and bidirec-tional pins into a high impedance state.


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30 Am53C94/Am53C96

FTMREG Bit 1 FIM Forced Initiator Mode

The FIM bit when set forces the device into the initiatormode. The device will then execute all initiator com-mands irrespective of the SCSI bus status.

FTMREG Bit 0 FTM Forced Target Mode

The FTM bit when set forces the device into the targetmode. The device will then execute all target commandsirrespective of the SCSI bus status.

Control Register Two (0BH) Read/Write

Control Register Two

CNTLREG2

Address: 0BH

Type: Read/Write7 6 5 4 3 2 1 0

DAE LSP SBO TSDR S2FE ACDPE PGRP PGDP

0 0 0 0 0 0 0 0

Latch SCSI Phase

Select Byte Order

TriState DMA Request

SCSI2 Features Enable

Abort on Command/Data Parity Error

Pass Through/Generate Register Parity

Pass Through/Generate Data Parity

Data Alignment Enable 16506C-31

The Control Register 2 (CNTLREG2) sets up the devicewith various operating parameters.

CNTLREG2 Bit 7 DAE Data Alignment Enable

The DAE bit is used in the initiator Synchronous Data-Inphase only. When the DAE bit is set one byte is reservedat the end of the FIFO when the phase changes to theSynchronous Data-In phase. The contents of this bytewill become the lower byte of the DMA word (16-bit)transfer to the memory, the upper byte being the firstbyte of the first word received from the SCSI bus.

Note:

If an interrupt is received for a misaligned boundary on aphase change to synchronous data the following recov-ery procedure may be followed. The host processorshould copy the byte at the start address in the hostmemory to the Data Alignment Register 0FH (DALREG)and then issue an information transfer command. Thefirst word the device will write to the memory (via DMA)will consists of the lower byte from the DALREG and theupper byte from the first byte received from the SCSIbus.

The DAE bit must be set before the phase changes tothe Synchronous Data-In. The DAE bit is reset to zero bya hard or soft reset or by writing the DALREG when in-

terrupted in the Synchronous Data-In phase.

CNTLREG2 Bit 6 LSP Latch SCSI Phase

The LSP bit is used to enable or disable the latching ofthe SCSI phase bits (MSG, C/D and I/O) in the StatusRegister (STATREG) 04H.

When the LSP bit is set the phase bits STSTREG Bits2:0 are latched at the end of each command. This simpli-fies software for stacked commands. When the LSP bitis reset the phase bits STATREG Bits 2:0 reflect the

actual state of the SCSI phase lines at any instant oftime. The LSP bit is reset by a hard or soft reset.

CNTLREG2 Bit 5 SBO Select Byte Order

The SBO bit is used only when the BUSMD 1:0 = 10 toenable or disable the byte control on the DMA interface.When SBO is set and the BUSMD 1:0 = 10, the byte con-trol inputs BHE and AS0 control the byte positions.When SBO is reset the byte control inputs BHE and AS0are ignored.

CNTLREG2 Bit 4 TSDR Tri-State DMA

RequestThe TSDR bit when set sends the DREQ output signal tohigh impedance state and the device ignores all activityon the DMA request (DREQ) input. This is useful forwiring-OR several devices that share a common DMArequest line. When the TSDR bit is reset the DREQoutput is driven to TTL levels.

CNTLREG2 Bit 3 S2FE SCSI2 FeaturesEnable

The S2FE bit allows the device to recognize two SCSI-2features. The two features are extended message fea-ture and the Group 2 command recognition.

Extended Message Feature: When the S2FE bit is setand the device is selected with attention, the device willmonitor theATNsignal at the end of the first messagebyte. If theATNsignal is active, the device will requesttwo more message bytes before switching to the com-mand phase. If theATNsignal is inactive the device willswitch to the command phase. When the S2FE bit is re-set the device as a target will request a single messagebyte. As an initiator, the device will abort the selectionsequence if the target does not switch to the commandphase after receiving a single message byte.


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Group 2 Command Recognition: When the S2FE bit isset the group 2 commands are recognized as 10 bytecommands. The GCV (Group Code Valid) bit in theSTATREG (04H) is set. When the S2FE bit is reset, thedevice will interpret the group 2 commands as reservedcommands and will request 6 byte commands. TheGCV bit in the STATREG will not be set in this case.

CNTLREG2 Bit 2 ACDPE Abort on Command/Data Parity Error

The ACDPE bit when set allows the device to abort acommand or data transfer when a parity error is de-tected. When the ACDPE bit is reset parity error is ig-nored.

CNTLREG2 Bit 1 PGRP Pass Through/Gener-ate Register Parity

The PGRP bit when set causes the data along with theparity from the host to pass through to the FIFO underthe control of theCS and theWR signals. When the

PGRP bit is reset, the device generates the parity on thedata from the host before writing it to the FIFO.

When the device is placing the data on the SCSI bus, itwill check for an outgoing parity error if either the PGRPbit is set or the PGDP (Pass Through/Generate DataParity) bit is set.

CNTLREG2 Bit 0 PGDP Pass Through/Gener-

ate Data Parity

The PGDP bit when set causes the data along with theparity from the host to pass through to the FIFO underthe control of theDACKand theWRsignals. When thePGDP bit is reset, the device generates the parity on thedata from the host before writing it to the FIFO.

When the device is placing the data on the SCSI bus, itwill check for an outgoing parity error if either the PGDPbit is set or the PGRP (Pass Through/Generate RegisterParity) bit is set.

4

Control Register ThreeCNTLREG3

Address: 0CHType: Read/Write

7 6 5 3 2 1 0

RES RES RES RES RES LBTM MDM BS8

0 0 0 0 0 0 0 0

ReservedReserved

Reserved

Reserved

Last Byte Transfer Mode

Modify DMA Mode

Burst Size 8

Reserved

16506C-32

Control Register Three (0CH) Read/Write

CNTLREG3 Bits 7:3 RES Reserved

CNTLREG3 Bit 2 LBTM Last Byte TransferMode

The LBTM bit specifies how the last byte in an odd bytetransfer is handled during 16-bit DMA transfers. Thismode is not used if byte control is selected via BUSMD1:0 inputs and BSO (Byte Select Order) bit in theCNTLREG2. This mode has no affect during 8-bit DMA

transfers and on transfers on the SCSI bus.When the LBTM bit is set the DREQ signal will not beasserted for the last byte, instead the host will read orwrite the last byte from or to the FIFO. When the LBTMbit is reset the DREQ signal will be asserted for the lastbyte and the following 16-bit DMA transfer will containthe last byte on the lower bus. If the transfer is a DMAread the upper bus will be all ones.

The LBTM bit is reset by hard or soft reset.

CNTLREG3 Bit 1 MDM Modify DMA Mode

The MDM bit is used to modify the timing of theDACKsignal with respect to theDMARDandDMAWRsignals.The MDM bit is used in conjunction with the Burst Size 8(BS8) bit in the CNTLREG3. Both bits have to be set forproper operation.

When the MDM bit is set and the device is in a DMA reador write mode the DACK signal will remain asserted

while the data is strobed by theDMARDorDMAWRsig-nals. In the DMA read mode when BUSMD 1:0 = 11 theDACKsignal will toggle for every DMA read.

When the MDM bit is reset and the device is in a DMAread or write mode theDACKsignal will toggle everytime the data is strobed by the DMARD or DMAWRsignals.


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CNTLREG3 Bit 0 BS8 Burst Size 8

The BS8 bit is used to modify the timing of the DREQsignal with respect to theDMARDandDMAWRsignals.The BS8 bit is used in conjunction with the Modify DMAMode (MDM) bit in the CNTLREG3. Both bits have to beset for proper operation.

When the BS8 bit is set the device delays the assertion

of the DREQ signal until 8 bytes or 4 words transfer ispossible.

When the BS8 bit is set and the device is in a DMA writemode the DREQ signal will be asserted only when 8 bytelocations are available for writing. In the DMA readmode the DREQ signal will go active under the followingcircumstances:

At the end of a transfer,

In the target mode, when the transfer is completeor

when theATNsignal is active

In the initiator mode, when the Current Transfer Register

is decremented to zeroor

after any phase change

In the middle of a transfer

In the initiator mode, when the last 8 bytes of the FIFO are full during Synchronous Data-In transfer when the

Event Transfer Count Register is greater than7 and the last 8 bytes of the FIFO are full.

When the BS8 bit is reset and the device is in a DMAread or write mode the DREQ signal will toggle every

time the data is strobed by the DMARD or DMAWRsignals.

Using Bit 0 (BS8) and Bit 1 (MDM) of ControlRegister 3, one can enable the different combinationmodes shown in the table below.

Maximum

(MDM) (BS8) Function SynchronousBit 1 Bit 0 Offset

0 0 Normal DMA Mode 15

0 1 Burst Size 8 Mode 7

1 0 Reserved

1 1 Modified DMA Mode 15

Data Alignment Register (0FH) Write

16506C-33

The Data Alignment Register (DALREG) is used if thefirst byte of a 16-bit DMA transfer from the SCSI bus tothe host processor is misaligned. Prior to issuing an in-formation transfer command, the host processor mustset the Data Alignment Enable (DAE) bit in theCNTLREG2.

DALREG Bits 7:0 DA 7:0 Data Alignment 7:0


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COMMANDSThe device commands can be broadly divided into twocategories, DMA commands and non-DMA commands.DMA commands are those which cause data movementbetween the host memory and the SCSI bus while non-

DMA commands are those that cause data movementbetween the device FIFO and the SCSI bus. The MSB ofthe command byte differentiate the DMA from the non-DMA commands.

Summary of Commands

Non-DMA DMAMode Mode

Initiator Commands

Information Transfer 10 90

Initiator Command Complete Steps 11 91

Message Accepted 12

Transfer Pad Bytes 18 98

SetATN 1A

ResetATN 1B

Target Commands

Send Message 20 A0

Send Status 21 A1

Send Data 22 A2

Disconnect Steps 23 A3

Terminate Steps 24 A4

Target Command Complete Steps 25 A5

Disconnect 27 A7

Receive Message 28 A8

Receive Command Steps 29 A9

Receive Data 2A AA

Receive Command Steps 2B AB

Target Abort DMA 04 84

Non-DMA DMAMode Mode

Idle State Commands

Reselect Steps 40 C0

Select withoutATNSteps 41 C1

Select withATNSteps 42 C2

Select withATNand Stop Steps 43 C3

Enable Selection/Reselection 44 C4

Disable Selection/Reselection 45 C5

Select WithATN3 46 C6

General Commands

No Operation 00 80

Clear FIFO 01 81

Reset Device 02 82

Reset SCSI bus 03 83

Command Code(Hex.) Command Code(Hex.)

Command Command


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COMMAND DESCRIPTION

Initiator Commands

Initiator commands are executed by the device when itis in the initiator mode. If the device is not in the initiatormode and an initiator command is received the devicewill ignore the command, generate an illegal commandinterrupt and clear the Command Register (CMDREG)

03H.

Information Transfer Command(Command Code 10H/90H)

The Information Transfer command is used to transferinformation bytes over the SCSI bus. This commandmay be issued during any SCSI Information Transferphase. Information transfer for synchronous data mustuse the DMA mode.

The device will continue to transfer information until it isterminated by any one of the following conditions:

The target changes the SCSI bus phase before theexpected number of bytes are transferred. The

device clears the Command Register (CMDREG)03H, and generates a service interrupt when thetarget assertsREQ.

Transfer is successfully complete. If the phase isMessage Out, the device deasserts ATN beforeasserting ACK for the last byte of the message.When the target assertsREQ, a service interrupt isgenerated.

In the Message In phase when the device receivesthe last byte. The device keeps the ACK signalasserted and generates a Successful Operationinterrupt.

During synchronous data transfers the target may sendup to the maximum synchronous threshold number ofREQpulses to the initiator. If it is the Synchronous Data-In phase then the target sends the data and theREQpulses. These bytes are stored by the initiator in theFIFO as they are received.

Information Transfer Command when issued during thefollowing SCSI phases and terminating in synchronousdata phases, is handled as described below:

Message In/Status Phase When a phase changeto Synchronous Data-In or Synchronous Data-Out isdetected by the device, the Command Register(CMDREG) 03H is cleared and the DMA interface is

disabled to disallow any transfer of data phase bytes.If the phase change is to Synchronous Data-In andbad parity is detected on the data bytes coming in, itis not reported since the Status Register(STATREG) 04H will report the status of thecommand just completed. The parity error flag andtheATNsignal will be asserted when the TransferInformation command begins execution.

Message Out/Command Phase When a phasechange to Synchronous Data-In or SynchronousData-Out is detected by the device, the CommandRegister (CMDREG) 03H is cleared and the DMAinterface is disabled to allow any transfer of dataphase bytes. If the phase change is to SynchronousData-In and bad parity is detected on the data bytescoming in, it is not reported since the Status Register(STATREG) 04H will report the status of thecommand just completed. The parity error flag andthe ATN signal will be asserted when the TransferInformation command begins execution. The FIFORegister29 (FFREG) 02H will be latched and willremain in that condition until the next commandbegins execution. The value in the FFREG indicatesthe number of bytes in the FIFO when the phasechanged to Synchronous Data-In. These bytes arecleared from the FIFO, which now contains only theincoming data bytes.

In the Synchronous Data-Out phase, the thresholdcounter is incremented asREQpulses are received.The transfer is completed when the FIFO is emptyand the Current Transfer Count Register (CTCREG)00H01H is zero. The threshold counter will not bezero.

In the Synchronous Data-In phase, the CurrentTransfer Count Register (CTCREG) is decre-mented as bytes are read from the FIFO rather thanbeing decremented when the bytes are being writtento the FIFO. The transfer is completed when CurrentTransfer Count Register (CTCREG) is zero but theFIFO may not be empty.

Initiator Command Complete Steps(Command Code 11H/91H)

The Initiator Command Complete Steps command isnormally issued when the SCSI bus is in the Status Inphase. One Status byte followed by one Message byteis transferred if this command completes normally. Afterreceiving the message byte the device will keep theACKsignal asserted to allow the initiator to examine themessage and assert theATNsignal if it is unacceptable.The command terminates early if the target does notswitch to the Message In phase or if the target discon-nects from the SCSI bus.

Message Accepted Command(Command Code 12H)

The Message Accepted Command is used to releasetheACKsignal. This command is normally used to com-plete a Message In handshake. Upon execution of thiscommand the device generates a service request inter-rupt afterREQis asserted by the target.


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After the device has received the last byte of message, itkeeps theACKsignal asserted. This allows the deviceto either accept or reject the message. To accept themessage, Message Accepted Command is issued. Toreject the message theATNsignal must be asserted(with the help of the SetATNCommand) before issuingthe Message Accepted Command. In either case theMessage Accepted Command has to be issued to re-

lease theACK

signal.Transfer Pad Bytes Command(Command Code 18H/98H)

The Transfer Pad Bytes Command is used to recoverfrom an error condition. This command is similar to theInformation Transfer Command, only the informationbytes consists of null data. It is used when the target ex-pects more data bytes than the initiator has to send. It isalso used when the initiator receives more informationthan it expected from the target.

When sending data to the SCSI bus, the FIFO is loadedwith null bytes and these bytes are sent out to the SCSIbus. DMA has to be enabled when pad bytes are trans-

ferred to the SCSI bus. No actual DMA requests aremade but the device uses the Current Transfer CountRegister (CTCREG) 00H01H to terminate thetransfer.

When receiving data from the SCSI bus, the device willreceive the pad bytes and place them on the top of theFIFO and unload them from the bottom of the FIFO.

The command terminates under the same condition asthe Information Transfer Command, only the devicedoes not keep theACKsignal asserted during the lastbyte of the Message In phase. If this command termi-nates prematurely, due to a disconnect or a phasechange, before the CTCREG decrements to zero, theFIFO may contain residual pad bytes.

SetATNCommand (Command Code 1AH)

The SetATNCommand is used to drive theATNsignalactive on the SCSI bus. An interrupt is not generated atthe end of this command. TheATNsignal is deassertedbefore asserting theACKsignal during the last byte ofthe Message Out phase.

Note:

TheATNsignal is asserted by the device without thiscommand in the following cases:

If any select withATNcommand is issued and thearbitration is won.

An initiator needs the targets attention to send amessage. TheATNsignal is asserted before deas-serting theACKsignal.

ResetATNCommand (Command Code 1BH)

The ResetATNCommand is used to deassert theATNsignal on the SCSI bus. An interrupt is not generated atthe end of this command. This command is used onlywhen interfacing with devices that do not support theCommon Command Set (CCS). These older devices donot deassert theirATNsignal automatically on the lastbyte of the Message Out phase. This device does deas-

sert itsATNsignal automatically on the last byte of theMessage Out phase.

Target Commands

Target commands are executed by the device when it isin the target mode. If the device is not in the target modeand a target command is received the device will ignorethe command, generate an illegal command interruptand clear the Command Register (CMDREG) 03H.

A SCSI bus reset during any target command will causethe device to abort the command sequence , flag a SCSIbus reset interrupt (if the interrupt is enabled) and dis-connect from the SCSI bus.

Normal or successful completion of a target commandwill cause a Successful Operation interrupt to beflagged. If theATN signal is asserted during a targetcommand sequence the Service Request bit is assertedin the Interrupt Status Register (INSTREG) 05H. If theATNsignal is asserted when the device is in an idle statea Service Request interrupt will be generated, the Suc-

cessful Operation bit in the INSTREG will be reset andthe CMDREG cleared.

Send Message Command(Command Code 20H/A0H)

The Send Message Command is used by the target toinform the initiator to receive a message. The SCSI busphase lines are set to the Message In Phase and mes-sage bytes are transferred from the device FIFO to thebuffer memory.

Send Status Command(Command Code 21H/A1H)

The Send Status Command is used by the target to in-

form the initiator to receive status information. The SCSIbus phase lines are set to the Status Phase and statusbytes are transferred from the target device to the initia-tor device.

Send Data Command (Command Code 22H/A2H)

The Send Data Command is used by the target to informthe initiator to receive data bytes. The SCSI bus phaselines are set to the Data-In Phase and data bytes aretransferred from the target device to the initiator device.

Disconnect Steps Command(Command Code 23H/A3H)

The Disconnect Steps Command is used by the target todisconnect from the SCSI bus. This command consistsof two steps. The first step consists of sending two bytesof the Save Data Pointers commands by the target in theMessage In Phase. In the second step the target discon-nects from the SCSI bus. Successful Operation and Dis-connected bits are set in the Interrupt Status Register(INSTREG) 05H upon command completion. IfATNsig-nal is asserted by the initiator then Successful Operationand Service Request bits are set in the INSTREG, theCMDREG is cleared and Disconnect Steps Commandterminates without disconnecting.


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Terminate Steps Command(Command Code 24H/A4H)

The Terminate Steps Command is used by the target todisconnect from the SCSI bus. This command consistsof three steps. The first step consists of sending onestatus byte by the target in the Status Phase. The sec-ond step consists of sending one message byte by thetarget in the Message In Phase. As the third step the tar-

get disconnects from the SCSI bus. Successful Opera-tion and Disconnected bits are set in the Interrupt StatusRegister (INSTREG) 05H upon command completion. IfATNsignal is asserted by the initiator then SuccessfulOperation and Service Request bits are set in the IN-STREG, the CMDREG is cleared and Terminate StepsCommand terminates without disconnecting.

Target Command Complete Steps Command(Command Code 25H/A5H)

The Target Command Complete Steps Command isused by the target to inform the initiator of a linked com-mand completion. This command consists of two steps.The first step consists of sending one status byte by the

target in the Status Phase. The second step consists ofsending one message byte by the target in the MessageIn Phase. The Successful Operation bit is set in the In-terrupt Status Register (INSTREG) 05H upon commandcompletion. IfATNsignal is asserted by the initiator thenSuccessful Operation and Service Request bits are setin the INSTREG, the CMDREG is cleared and TargetCommand Complete Steps Command terminatesprematurely.

Disconnect Command(Command Code 27H/A7H)

The Disconnect Command is used by the target to dis-connect from the SCSI bus. All SCSI bus signals except

RSTCare released and the device returns to the Dis-connected state. TheRSTCsignal is driven active forabout 25 micro seconds (depending on clock frequencyand clock factor). Interrupt is not generated to the micro-processor.

Receive Message Steps Command(Command Code 28H A8H)

The Receive Message Steps Command is used by thetarget to request message bytes from the initiator. Dur-ing this command the target receives the messagebytes from the initiator while the SCSI bus is in the Mes-sage Out Phase. The Successful Operation bit is set inthe Interrupt Status Register (INSTREG) 05H uponcommand completion. IfATNsignal is asserted by theinitiator then Successful Operation and Service Re-quest bits are set in the INSTREG, the CMDREG iscleared. If a parity error is detected, the device ignoresthe received message bytes until ATN signal is as-serted, the Successful Operation bit is set in the IN-STREG, and the CMDREG is cleared.

Receive Commands Command(Command Code 29H/A9H)

The Receive Commands Command is used by the tar-get to request the initiator for command bytes. During

this command the target receives the command bytesfrom the initiator while the SCSI bus is in the CommandPhase. The Successful Operation bit is set in the Inter-rupt Status Register (INSTREG) 05H upon commandcompletion. IfATNsignal is asserted by the initiator thenSuccessful Operation and Service Request bits are setin the INSTREG, the CMDREG is cleared and the com-mand terminates prematurely. If a parity error is de-

tected, the device continues to receive command bytesuntil the transfer is complete if the Abort on Command/Data Parity Error (ACDPE) bit in the Control Register(CNTLREG2) 0BH is reset. If the ACDPE bit is set, thecommand is terminated immediately. The Parity Error(PE) bit in the Status Register (STATREG) 04H is setand CMDREG is cleared.

Receive Data Command(Command Code 2AH/AAH)

The Receive Data Command is used by the target to re-quest the initiator for data bytes. During this commandthe target receives the data bytes from the initiator whilethe SCSI bus is in the Data-Out Phase. The Successful

Operation bit is set in the Interrupt Status Register (IN-STREG) 05H upon command completion. IfATNsignalis asserted by the initiator then Successful Operationand Service Request bits are set in the INSTREG, theCMDREG is cleared and the command terminates pre-maturely. If a parity error is detected, the device contin-ues to receive data bytes until the transfer is complete ifthe Abort on Command/Data Parity Error (ACDPE) bit inthe Control Register (CNTLREG2) 0BH is reset. If theACDPE bit is set, the command is terminated immedi-ately. The Parity Error (PE) bit in the Status Register(STATREG) 04H is set and CMDREG is cleared.

Receive Command Steps Command

(Command Code 2BH/ABH)The Receive Command Steps Command is used by thetarget to request the initiator for command informationbytes. During this command the target receives thecommand information bytes from the initiator while theSCSI bus is in the Command Phase.

The target device determines the command byte lengthfrom the first command byte. If an unknown length is re-ceived, the Start Transfer Count Register (STCREG)00H01H is loaded with 5 and the Group Code Valid(GCV) bit in the Status Register (STATREG) 04H is re-set. If a valid length is received, the STCREG is loadedwith the appropriate value and the GCV bit in theSTATREG is set. IfATNsignal is asserted by the initia-tor then the Service Request bit is set in the INSTREG,and the CMDREG is cleared If a parity error is detected,the command is terminated prematurely and theCMDREG is cleared.

DMA Stop Command (Command Code 04H/84H)

The DMA Stop Command is used by the target to allowthe microprocessor to discontinue data transfers due toa lack of activity on the DMA channel. This command isexecuted from the top of the command queue. If there isa queued command waiting execution, it will be over-written and the Illegal Operation Error (IOE) bit in the


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Status Register (STATREG) 04H will be set. This com-mand is cleared from the command queue once it isdecoded.

Caution must be exercised when using this command.

The DMA Stop Command can be used only during aDMA Target Send Data Command or DMA Target Re-ceive Data Command execution. In both cases the DMA

controller has to be in the idle state.

During a DMA Target Send Data Command the FIFOhas to be empty or the Current FIFO (CF 4:0) bits in theCurrent FIFO/Internal State Register (CFISREG) 07Hare zero.

During a DMA Synchronous Target Receive Data Com-mand the Current Transfer Count Register (CTCREG)0001H is zero, which is indicated by t

scsi controller

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differential scsi

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data bus high current

common scsi sequences

bitscsi data interface