sachverzeichnis - link.springer.com978-3-662-06747-5/1.pdf · 198 prozessor 8085 ... 421...

Sachverzeichnis

13-Segment-Kennlinie .............................. 309 decoder ................................................ 264 I-Bit-Folge ............................................... 308 decodierung 1T-1C-Zelle .............................................. 249 unvollständige ................................. 264 2T -2C-Zelle .............................................. 252 vollständige .................................... 264 3-State Buffer ............................................. 88 Adresse .............................. 335, 338-343, 403 3-State-Ausgang ......................................... 59 Adressierung ............................................. 237 7400 ...................................................... 56, 57 direkte .................................................. 391 8051 .......................................................... 344 indirekte ............................................... 391 8-Bit-D-Latch ........................................... l71 Immediate ............................................ 390 8-Bit-D-Register ....................................... 175 indizierte .............................................. 391

Register- .............................................. 390 A51 .......................................................... .417 unmittelbare ......................................... 390 Abhängigkeit AdressierungsaTt ....................................... 348

Adressen- ............................................. 512 Controller 8051 .................................... 390 Freigabe-.............................................. 511 Adress-Mode- .................................................. 512 leitungen .............................................. 220 Negations- ........................................... 509 puffer ........................... 335, 339, 342, 343 ODER-................................................. 509 ADU ......................................... 271,273,275 Setz-und Rücksetz- .............................. 5 10 Advanced Steuer- ................................................. 511 LS-TTL .................................................. 56 UND- ................................................... 508 Schottky-TTL ........................................ 56 Verbindungs- ....................................... 5 10 AHG ................................. 275,277, 281, 283

Abhängigkeitsnotation .............................. 507 Akkumulator.. ........................................... 337 Absolute ALE .................................. 338, 342, 345, 386

Segmente ............................................. 419 Algorithmische Verfahren .......................... 37 Fehler ................................................... 286 Alternate Output Function ........................ 356

Abtast- ALU ......................................... 331,337,346 halteglied ..................... 275,277, 280, 281 Analog-Digital-Umsetzer ......... 271,292, 445 phase ............................................. 278-282 Analoge theorem ................................ 275, 276, 308 Eingabekanäle ...................................... 446 unsicherheil ......................................... 281 Grösse .................................................... 20

Abtastung ......................................... 272, 275 Analogsignal... .................................. 275, 309 ACC ......................................................... 352 Anschlüsse Accumulator ............................................. 353 Controller 8051 .................................... 385 Active ................................................ 237-239 Prozessor 8085 ..................................... 337 ADC ......................................................... 271 Anstiegszeit .............................................. 280 ADD ......................................................... 424 Antifuse-Link ............................................. 81 Addierer. ................................................... 156 Antivalenz-Verknüpfung ............................ 28

4-Bit-Ripple-Carry-Addierer ....... 158, 159 An wenderspezifische Bausteine ................. 71 8-Bit-Addierer ..................................... 159 Aperture Halbaddierer ........................................ 156 Jitter ..................................... 281, 282, 284 n-Bit-Ripple-Carry-Addierer ............... 160 Time ............................................ 281,284 Volladdierer ......................................... 157 Uncertainty Time ................................. 281

Additionsbefehle ...................................... 397 -fehler .................................................. 308 Adress- -zeit.. .................................... 281, 282, 283

bus ....................................... 332,334,338 Application Specific 1Cs ....................... 50, 71

522 13 Sachverzeichnis

Aquisition time ......................................... 318 für Verzweigungsoperationen ............. 393 Äquivalenz von Zuständen ....................... 203 Befehls-Arbeitstabelle ............................................. 18 ausführung ................................... 339, 387 Arbitration ................................................ 242 entschlüssler ................. 335-337, 339, 341 Arithmetic Iiste

Logic Unit ........................................... 331 Controller 8051 .............................. 513 -Logik-Einheit ..................................... 346 register ................... 335-337, 339, 340, 343

ASCII-Zeichen ......................................... 365 satz ASIC .................................................... 50,51 Controller 8051 .............................. 391 Assembler ................................................ 414 speicher-Erweiterung .......................... 347

- Testprogramme ......................... 428, 436 zyklen ........................... 340, 342, 387, 388 - Anweisungen .................................... 422 Beschreibungsfeld ............................ 503, 506 - Funktion ............................................ 440 Betriebsdaten von FRAMs ....................... 252 - Steueranweisungen ........................... 422 Betriebsspannungsabhängigkeit ............... 317 - Steuervariable ................................... 422 Bibliotheksdateien .................................... 423

Assoziative Gesetze ................................... 29 Binäre Variable .......................................... 15 Assoziativ-Speicher ................................. 219 Binden relokativer Objektmodule ............ 425 Astabiler Multivibrator ............................. 161 Bistabile Kippstufe ................................... 165 Auffrischen .............................................. 228 Bitadressierbar ......................................... 352 Auflösung ................................................ 319 Bit-Auflösungswert .......................................... 95 gewicht.. .............................................. 311 Ausführungszeit ............................... 443, 441 operationen .......................................... 346 Ausgabe ............................ 337, 338, 340, 342 operationsbefehle ................................ 402

kombinatorisch ............................ 207,208 Übergang ............................................... 10 Register- ...................................... 207, 208 Blank & Convert ...................................... 322 von Zustandsvariablen ......................... 209 Blockbeschreibungsfeld ................... 503, 505 -datei ................................................... 143 Blockschaltbild -funktion .............................................. 198 Controller 8051 ........................... 344, 345 -vektor ................................................. 198 Prozessor 8085 .................................... 336

Ausgangs- Timer/Counter 8051 ..................... 361-363 lastfaktor ............................................... 53 Boolesche Algebra ................................. 2, 28 treiber .................................................. 356 Boolescher Prozessor ............................... 346 variablen ................................................ 19 Booth-Algorithmus .................................... 10

Auswahlstrukturblock .............................. 412 Borrow ......................................................... 5 Auto Refresh ............................................ 238 Bottom Up-Entwurf ................................. 410 Automat Boundary Scan ........................................... 88

Mealy- ................................................. 198 BSEG ....................................................... 420 Moore- ................................................ 198 Bündel-Refresh ........................................ 228

Automatentheorie ..................................... 197 Burst.. ....................................................... 238 Autoprecharge .......................................... 238 Length ................................................. 239 Auxiliary Carry Hag ................................ 353 Refresh ................................................ 228 Axiome ...................................................... 28 Terminate ............................................ 238

-ausgabe .............................................. 239 B-Register ................................................ 353 Bus ................................................... 340,341 Band-Gap-Dioden .................................... 305 Bussystem ................................................ 332 Baudrate ........................................... 367,370 Busy ......................................................... 322

im Mode 0 ........................................... 375 im Mode 2 ........................................... 376 C - Testprogramme .................................. 436 im Mode 1 und 3 ................................. 375 C/-,T ........................................................ 360

Baumdiagramm ........................................ 411 Cachezeile ................................................ 230 Bausteinfamilie .................................... 50, 56 Carry ............................................................ 5 Befehle ..................................................... 339 Hag ..................................................... 353

für arithmetische Operationen ..... 393, 397 CAS ................................................. 226, 238 für Bitoperationen ............................... 393 before •RAS Refresh .......................... 228 für Dekrement- und Inkrementoper.399 Latency ........................................ 238, 239 für logische Operationen ............. 393, 400 für Transferoperationen ....................... 392

-Zykluszeit .......................................... 229 CBR-Refresh ............................................ 228

13 Sachverzeichnis 523

CLB ............................................................ 84 Speicher ........................................ 348, 349 Clock to Output Time ......................... 80, 172 Speicher-Erweiterung ........................... 351 Clocksignal. .............................................. 23 8 Übertragung .......................................... 363 CMOS-Technik .......................................... 67 DAU ......................................... 273, 275, 309 Code ................................................. l47, 337 DDR SDRAM .......................................... 235

ASCII- ......................................... 147, 148 De Morgansche Gesetze ............................. 29 BCD ........................................................ 2 Debugger .......................................... 414, 423 BCD unipolar .... , ......................... 286, 287 Dedicated binär unipolar ...................................... 286 Input ...................................................... 75 bipolar ................................................. 286 Output.. .................................................. 75 kompakter ............................................ 438 DELETE ................................................... 424 mit Absolutwert und Vorzeichen ......... 288 Delta-Modulator ....................................... 306 numerischer ......................................... 148 Demultiplexer ........................................... l55 offset binary ................................. 286, 287 1-zu-4-Demultiplexer .......................... 155 relokativer ............................................ 420 Depolarisation .......................................... 251 straight binary ...................................... 286 Deselect .................................................... 237 Two's Complement ............................. 286 Dezimalzähler ........................................... 189 unipolarer ............................................ 286 D-Flipflop ................................................... 77 Wortcode ............................................. 148 Dielektrikum ............................................. 247

Dualcode ......................................... 148 Differentielle Nichtlinearität.. ................... 317 Gray-Code .............................. 148, 149 Differenzierer ........................................... 210

Ziffern- ................................................ 149 Digital-Analog-Umsetzung ....................... 309 3-Exzess- ........................................ 150 Digitale 8-4-2-l- .......................................... 149 Größe ..................................................... 21 Aiken-............................................. 150 Halbleiterspeicher ................................ 219 BCD-Gray- ..................................... 150 Differenzierer ...................................... 210

Zweierkomplement-............................. 286 Digitales Filter .......................................... 307 Code- Digitalisierung .......................... 275, 276, 286

Segment ............................................... 418 Digitally Locked Loop .............................. 237 Umsetzer ...................................... l5l, 152 DIN 40146 ................................................ 273

Codierschaltungen .................................... 147 DIN 66000 .................................................. 15 Codierung ......................................... 272, 275 Diodenbrücke ........................................... 282 Column ..................................................... 237 Direkte Adressierung ................................ 348

Addr. Strohe ........................................ 238 Direktumsetzer ......................................... 292 Complementary MOS ................................. 67 Disjunktion ................................................. 26 Complex Programmahle Logic Device. 50, 79 Disjunktive Concurrent Refresh ................................... 228 Minimalform .......................................... 35 Contigurahle Logic Block .......................... 84 Normalform ........................................... 33 Convert Pulse Mode ................................. 323 Diskretisierung ......................................... 272 Counter-Betrieb ........................................ 359 Distributed Refresh ................................... 228 CPLD ................................................... 50, 79 Distributive Gesetze ................................... 29 CPU .......................................... 331,335,341 Division von Dualzahlen ............................ 11 CREATE .................................................. 424 Divisions- und Mu1tiplikationsbefehle ...... 399 CSEG ....................................................... 419 Divisionsbefehle ....................................... 346 CTS .......................................................... 365 D-Latch ............................................ 170, 171

DLL .......................................................... 237 Data Pointer .............................................. 345 Doppel-Integrations-Verfahren ......... 304, 305

Ready ................................................... 322 Double Data Rate SDRAM ...................... 235 retention ............................................... 251 Double-length Lines ................................... 87 -Segment. ............................................. 418 DPH .......................................................... 352

Daten- DPHIDPL ................................................. 345 ausgänge .............................. 220, 322, 326 DPL .......................................................... 352 bus ....................................................... 332 DQS .......................................................... 236 eingang ................................................ 220 DQS-Generator ......................................... 237 haltung ................................................. 251 DRAM ................................ 51,224,226,252 pointer ................................................. 354 DRAM-Controller .................................... 227 selektor ................................................ 153 Droop Current .................................. 281, 284


Droop Rate ....................................... 281, 284 ENOB ...................................................... 319 DSEG ....................................................... 419 Entlade-DSR ......................................................... 365 dauer .................................................... 304 DTR ......................................................... 365 zeitkonstante ........................................ 281 Dual Slope-Verfahren ...................... 302, 304 Entwicklung Duale der Modularchitektur ........................... 411

Addition .................................................. 5 der Systemarchitektur .......................... 410 Subtraktion .............................................. 5 Entwurf komplexer Speichersysteme ....... 264

Dual-Port-RAM ....................................... 241 Entwurfsphase .......................................... 407 Dualsystem ................................................... 2 EPROM ........................................... 257,269 Dynamische Fehler ................................... 318 Löschvorgang, ..................................... 260 Dynamisches RAM ............................. : .... 224 Erasable PROM ....................................... 257

Erweitertes FJA-Interface ............................................ 331 Parallelverfahren .................. 295, 296, 324 EA .................................................... 345,386 Zählverfahren .............................. 295,301 EAROM ................................................... 258 ESDRAM ................................................. 234 ECL ............................................................ 69 ETX/ACK-Procedur ................................. 365 Editor ............................................... 414, 416 Exklusiv-ODER .............. , .......................... 28 EDO-DRAM ............................................ 230 Extended-Data-Output-DRAM ................ 230 EDRAM ................................................... 230 Externaufrufe ........................................... 421 EEPROM ......................................... 258, 269 Externe Effective Number Of Bits ....................... 319 Interrupt 0-Freigabe ............................. 379 Effektive Auflösung ......................... 318,319 Interrupt 0-Priorität ............................. 379 Effizienz ................................................... 406 lnterrupt 1-Freigabe ............................. 379 Ein-/ Ausgabe- Interrupt I-Priorität ............................. 379

block ..................................................... 86 Interrupts ............................................. 3 77 einheit. ................................................. 331 werk .................................................... 331 Fan-In ......................................................... 53

Einadress-Maschinen ............................... 339 Fan-Out ...................................................... 53 Einbindung ............................................... 438 Fast-Page-Mode-DRAM .......................... 229 Einer-Komplement ....................................... 6 Fatigue ..................................................... 251 Eingabe Feedthrough ..................................... 281,284

asynchron ............................................ 207 Fehler synchron .............................................. 207 absolute ............................................... 315 -datei ................................................... 141 dynamische ......................................... 318 -vektor ................................................. 197 realer AD- und DA-Umsetzer .............. 313

Bingangs- relative ................................. 286, 309, 316 fehlerstrom .................................. 280, 281 statische ............................................... 314 Iastfaktor ............................................... 53 systematische ...................................... 314 variablen ................................................ 19 -strom .................................................. 281

Einschwingzeit ......................................... 318 Feldeffekttransistoren ................................. 65 Einsprungadresse ..................................... 439 IGFET ................................................... 65 Einstufige Logik ......................................... 30 NIGFET ................................................ 65 Ein-Transistor-Speicherzelle .................... 224 FeRAM .................................................... 247 Einzelbitrechner ....................................... 346 Ferroelektrischer Einzustandsgesteuertes Flipflop ............... 169 Speicher ............................................... 247 Elektrisch löschbare, programmierbare ROMs Effekt ................................................. 247

............................................................ 258 Kondensator ............................... 248, 249 Elementarblock ........................................ 503 Festwertspeicher ...................................... 255 Ernitter Coupled Logic ............................... 69 FET ............................................................ 65 Empfangsbetrieb ............... 369, 371, 372, 373 FFT .................................................. 318,319 Emulations- und Testadapter .................... 414 Field Programmahle Gate Array .......... 50, 81 Emulator .................................................. 427 FIFO-Speicher .......................................... 245 Endlicher Automat ................................... 197 Filterung ........................................... 276, 310 Enhanced Finite State Machine ................................ 197

DRAM ................................................ 230 First-In/First -Out -Speicher ....................... 245 SDRAM .............................................. 234 Flag 0 ....................................................... 353


Flanken- Haltekapazität... ........................ 279,280, 281 gesteuert .............................................. 171 Halte--Steuerung ............................................ 377 phase .................................... 278, 280, 281

Flash zeit ....................................................... 172 Memory ............................................... 261 Hardware--Speicher. ..................................... 261, 269 beschreibungssprache ............................ 91 -Umsetzer .................................... 288, 295 sicherungen ............................................ 78

Flipflop ............................................. 165, 341 Verbindung ............................................ 81 D- .......................................................... 77 Harmonische Verzerrungen ...................... 318 D, flankengesteuert .............................. 173 Harvard-Architektur ......................... 333, 346 D, zustandsgesteuert ............................ 170 Hazards ..................................................... 206 einflankengesteuert .............................. 171 Hexadezimalsystem .................................. 2, 4 JK, flankengesteuert ............................ 175 Hidden Refresh ......................................... 228 RS, flankengesteuert ............................ 172 Hilfsmessgröße ......................................... 302 RS, NAND, zustandsgesteuert ............. l69 Histogramm .............................. 318,320,321 RS, ungetaktet ..................................... 166 Hochpass .................................................. 308 RS, zustandsgesteuert .......................... 169 Hold Time ................................................ 172 T, flankengesteuert .............................. 179 Hornerschema ......................................... l, 13

Floating Gate ............................................ 258 H-Pegel... .............................................. l6,62 Floating-Gate-Technologie ....................... 259 Hybridtechnik.. ................................. 282, 290 FLOTOX -Speichertransistor .................... 259 Hystereseschleife .............................. 250, 251 Flussdiagramme ....................................... 411 Folge einfacher Strukturblöcke ................. 412 110- ............................................................. 75 Folgezustandsvektor ................................. 197 Ports ............................................. 344,355 FPGA ................................................... 50, 81 Zelle ....................................................... 83 FPM-DRAM ............................................. 229 IC ............................................................... 49 FRAM .............................................. 247,252 Idle Mode ................................. 239,383,444 FRAM-Speicherzelle ........................ 249, 251 Bit ........................................................ 384 Frequenzgang ................................... 280, 310 Idle-Zustand ............................................. 239

Inverser ........................................ 276,310 IE ..................................................... 352, 379 Frequenzteiler .................................... l75,178 IEEE-Boundary-Standard ........................... 88 FSM .......................................................... I97 IGFET ........................................................ 65 Pulleustom IC ................................. 51, 71, 72 Implementierungsphase .................... 407, 414 Funktionen ............................................... 198 Imprint.. .................................................... 251 Funktions- Impuls-

block ...................................................... l8 former .................................................. 162 generator ................................................ 84 verzögerungszeit .................................... 55 Parameter ............................................. 438 Include-Datei ............................................ 438

Fuse-Link ................................................... 82 Indirekte V erfahren .................................. 302 Inherent .................................................... 390

Gain Error. ................................................ 3 16 INL ........................................................... 316 Gate .......................................................... 360 Input GateArray ...................................... 51, 71,72 Output Read ......................................... 340 Gatterdurchlaufzeit ............................. 55, 163 Output Write ........................................ 340 General Controls ....................................... 422 /Output.. ................................................. 75 Generelle Interrupt-Freigabe .................... 379 /Output Block ........................................ 86 Gespeicherte Ladung ................................ 224 INT0 ................................................. 355,377 Glitchfläche .............................. 318,320,321 INTl ................................................. 355,377 Global Net .................................................. 88 Integrale Nichtlinearität ............................ 316 Granularität ................................................ 51 Integrated Circuit.. ...................................... 49 Grenzfrequenz .................. 181,275, 276, 282 Integration ................................................ 303 Grund- Integrations-

verknüpfungen ....................................... 25 dichte ................................................... 329 welle .................................................... 320 zeitkonstante ........................................ 305

Integratorschaltung ................................... 303 Half-Flash-Umsetzer ................................ 298 Interpolatortiefpass ........................... 275, 310 Haltedauer ........................................ 277, 280 Interrupt.. ................... 325, 335, 337, 342, 376


Interrupt Lese-1 Edge ................................................. 361 verstärker .............................. 225, 229, 280 Enab1e Register ........................... 354, 378 vorgang ............................................... 251 Priority ................................................ 345 zeiger ................................................... 245

Register .......................................... 353 zugriff des 8051 .................................. 388 -quelle ................................................. 377 zyklus .................................................. 223 Type 1 Control .................................... 361 BEDO-RAM, Burst Mode .............. 232 -Antwortzeiten .................................... 381 DRAM ........................................... 227 -Service-Routine ................................. 376 EOO Page Mode ............................ 231 -Steuerung ........................................... 344 ESDRAM, Burst Mode .................. 234 -Vektor ........................................ 376,377 FPM-DRAM, Fast Page Mode ....... 229 -verarbeitung ....................................... 380 SDRAM, Burst Mode ..................... 234

Intersegmentaufrufe ................................. 421 Library-Manager .......................... : ........... 414 Intrasegmentaufrufe ................................. 421 Life-Cycle-Modell ................................... 407 10/-.M ...................................................... 338 LIF0 ........................................................ 245 lOB ............................................................ 86 Lineare Ionenimplantation .................................... 330 AD-Umsetzung ................................... 309 1P ............................................. 345, 352, 379 Quantisierung ...................................... 286 ISEG ........................................................ 420 Verzerrung .................................. 276, 310

Linker-Locator ......................................... 414 Karnaugh-Veitch-Diagramm ...................... 38 LIST ......................................................... 424 Kaskaden- Logik

struktur ................................. 293, 294, 300 -block .................................................... 80 umsetzer .............................................. 292 -Pegel .............................................. 15, 63

Kaskadierung ........................................... 189 -Polarität ................................................ 19 Kennlinie .......................................... 314,315 -stufen ................................................... 30

ideale ........................................... 314, 316 -vereinbarung ........................................ 17 Ketten- -zelle ...................................................... 83

leitemetzwerk .............................. 311,312 -Zustand ................................................ 16 schaltung ............................................. 312 Logische Variablen .................................... 22

Kippstufe Lokalisiervorgang .................................... 426 bistabil. ................................................ 165 Longlines ................................................... 87 monostabil ........................................... 164 Low-Power-Schottky-TIL ......................... 56

Koerzitivspannung ................................... 248 L-Pegel.. ............................................... 16,61 Kombinatorische Schaltung ..................... 147 LSB .......................................................... 316 Kommando ........................................ 237-239 LSI ............................................................. 51

Lffi51 .................................................. 424 Kommutative Gesetze ................................ 29 Makro-Komparator ....................... 289, 293,302, 307 assembler ............................................. 417 Komplexität einiger Mikroprozessoren .... 328 zelle ....................................................... 77 Konfigurationsmode ................................... 89 Map-Speicher ........................................... 427 Konfigurierbarer Logikblock ..................... 84 Maschinenzyklus ............... 335, 339-343, 387 Konjunktion ............................................... 26 Maskenprogrammiertes ROM .................. 255 Konjunktive Minimalform ......................... 35 Master Konvertierung .................................... 3, 4, 13 -mode .................................................... 89 Korrektheit ............................................... 406 Parallel Mode ........................................ 89 Kürzungsregeln .......................................... 30 Serial Mode ........................................... 89 KV-Diagramm ........................................... 38 Maxterm ..................................................... 33

Mealy-Automat ........................................ 198 Ladungs- Medium Scale Integration .......................... 51

vergleich .............................................. 225 Mehrflanken-Umsetz-Verfahren .............. 306 verschiebung ....................................... 247 Memory

Large Scale Integration .............................. 51 Read .................................................... 340 Lastfaktor ................................................... 53 Write ................................................... 340 Laufzeiten ................................................ 438 Mess-Leistungsverbrauch .................................. 329 größe ................................................... 271 Leiternetzwerk ................................. 312,321 schritt ........................... 289, 290, 295, 299


zeit ....................................................... 302 differentielle ........................................ 317 zyklus .................................. 293, 302, 303 integrale ............................................... 316

Microcontroller-Applikationen ................. 446 NIGFET ...................................................... 65 Mikrocomputer ......................................... 328 Nitrid-MOS-Technologie ......................... 259

-Design-Zyklus .................................... 409 N-Kanai-Enhancement-Transistor ............ 249 Mikrocontroller ........................................ 343 NMOS-Technik .......................................... 66

kundenspezifisch ................................. 343 No Operation ............................................ 237 Standard- ............................................. 343 Nonlinearity .............................................. 316

Mikroprozessor. .................. 51, 327,334, 339 NOP .......................................................... 237 -Baugruppe .......................................... 338 NOR ........................................................... 22 -Interface ..................................... 321,323 -FLASH ............................... 252,261,269

Minimale logische Gleichung ..................... 35 Normale ............................ 288,291, 295, 297 Minimieren ................................................. 35 Normalenzahl ............................ 291, 296-298 Minimierungsverfahren .............................. 37 Normalform ................................................ 33 Minterm ...................................................... 33 NOR-Technik ............................................. 32 MirrorBit-Cell .......................................... 264 NOVRAMs ............................................... 260 Missing Code ................................... 317, 321 N-stufige Logik .......................................... 31 MLC ......................................................... 264 Nulldurchgang .......................................... 306 Mode ......................................... 323-325, 360 Nyquistgrenze ........................................... 319

Register Set... ....................................... 237 Modulare Programmentwicklung ............. 405 Oberwellen ............................................... 320 Momentanwert ......................................... 303 Objektcode ............................................... 436 Mono- Objektorientierte Programmierung .......... .408

flop ...................................................... 164 ODER ......................................................... 22 stabile Kippstufe .................................. 164 -Feld ...................................................... 74

Monoton ................................................... 308 OE ............................................................ 346 Monotonicity ............................................ 317 Offener Kollektorausgang .......................... 60 Monotonität .............................................. 317 Offsetfehl er. .............................................. 315 Moore ....................................................... 329 Oktalsystem .................................................. 2

-Automa\. ............................................. 198 Opcode fetch ............................................ 342 MOSFET .................................................... 64 Open-Most Significant Bit ................................. 291 Drain .................................................... 356 MOS-Technik ............................................. 64 Kollektor ................................................ 59 MRAM ..................................................... 252 Operanden- ............................................... 387 MSI ............................................................ 51 bereich ................................................. 346 Multicontroller-System ............................. 447 teil... ............................................. 331, 337 Multi-Level-Cell ....................................... 264 Operations- ............................................... 331 Multiplexbetrieb ............................... 308, 323 bereich ................................................. 346 Multiplexer ....................................... 153, 274 code ..................................................... 387

4-zu-1-Multiplexer. .............................. 153 verstärker ............................. 278, 303, 311 Multiplexverfahren ................................... 335 Oszillator Multiplikation ..................................... 346, 10 digitaler. ............................................... 161 Multivibrator ............................................ 162 quarzgesteuerter ................................... 164

Overflow Flag ........................................... 353 NAND- ....................................................... 22 Oversampling

Flash .................................... 252, 261, 269 -Technik .............................................. 308 Technik .................................................. 32 -Umsetzer ............................................ 306

Negation ..................................................... 23 Negationskreis ............................................ 17 Page .......................................................... 237 Negative Logikvereinbarung ...................... 17 PAL ............................................................ 73 Neumannscher Universalrechenautomat... 331 Parallel Neumann-Struktur .................................... 331 -Serien-Wandler.. ................................. 194 Nichtflüchtig ............................................ 24 7 -verfahren ............................................ 288 Nichtflüchtige RAMs ............................... 260 Parameter .......................................... 439, 441 Nichtlineare A/D-Umsetzung ................... 309 -übergabe ............................................. 439

Paritätsbit. ................................................. 364 Nichtlinearitä\... ........................ 314, 316,317 Partity Flag ............................................... 3 53


PCH/ PCL ................................................ 345 Programmierbare PCON ............................................... 352, 384 Logik ..................................................... 73 Pegel- Makrozelle ............................................ 76

bereich ................................................... 16 Verbindung ........................................... 86 tabelle .................................................... 24 Programmierbares ROM .......................... 257 Zustände ................................................ 61 Programmspeicher ............ 339-341, 343, 347

Peripheral Mode ......................................... 89 PROM .............................................. 257, 269 Perovskit-Kristalle ................................... 248 Prototyp .................................................... 439 Phase ........................................................ 387 Prototyping ............................................... 408 PIM ............................................................ 80 Prozessorstatuswort .................................. 348 Pipeline- PSEN ................................ 345, 346, 348, 386

ND-Umsetzer ...................... 294, 299, 300 Pseudo-Architektur .......................................... 299 tetrade .......................................... 149,213 Prinzip ......................................... 295, 301 Zufallszahlengenerator ......................... 195 Struktur ............................................... 299 PSW .......................................... 348, 352, 353 Verfahren ............................................ 294 PuB-

Planungsphase .......................................... 406 Down-Widerstand ................................. 61 Plateleitung .............................................. 249 Up ....................................................... 356 PLD ................................................ 50, 71, 73 Up-Hardware ....................................... 358 PMOS-Technik .......................................... 66 Up-Widerstand ...................................... 62 Polarisation .............................................. 247 PZT .......................................................... 248 Polarisations-

richtung ............................................... 248 Quantisierung ............................ 272, 275, 309 zustände .............................................. 247 lineare .......................................... 309, 314

Polaritätsindikator ...................................... 18 nichtlineare .......................................... 309 Polyadisches Zahlensystem .......................... 1 Quantisierungs-Port ........................................................... 354 fehler .................................... 272, 286, 309 Portabilität ................................................ 406 fehlerleistung ....................................... 309 Portanschlüsse .......................................... 355 gerade .................................................. 284 Positive Logikvereinbarung ....................... 17 intervall ................................ 272, 284, 314 Power Down ............................................ 237 intervallbreite .............................. 277, 284

Bit ....................................................... 384 kennlinie ...................................... 284, 285 Mode .................................... 383,384,444 stufenzahl ............................................ 277

Power Quasistatisches dynamisches RAM .......... 240 On ....................................................... 239 Quellcodierer ............................................ 274 On Reset.. ............................................ 382 Supply Rejection ................................. 317 R-2R-Leiternetzwerk ........................ 312,313 Supply Sensitivity ............................... 317 Races ........................................................ 206

Precharge .................................. 225, 235, 237 RAM ................................................ 220, 396 -signal. ................................................. 251 -Port .................................................... 244

Primäranweisungen .................................. 422 RAS ................................................. 226, 238 Primary Controls ...................................... 422 only Refresh ........................................ 228 Prioritätsstruktur der 8051-Interrupts ....... 379 to CAS Delay ...................................... 237 Problemanalyse ........................................ 406 Rauschsignale .......................................... 304 Produktterm ............................................... 73 RB8 .......................................................... 367

-Allocator .............................................. 80 RD ............................................. 338, 346, 355 Program RDY/BSY- Prozedur .............................. 365

Counter ................................................ 335 Read ................................................. 237,238 Status Word ......................................... 353 Latch ................................................... 356

Programmablaufpläne .............................. 411 Pin ....................................................... 356 Programmahle -Modify-Write ..................................... 358

Array Logic ........................................... 73 READY .................................................... 341 Interconnect.. ......................................... 86 Receive Interrupt Flag .............................. 367 Interconnect Matrix ............................... 80 Rechenregeln der Schaltalgebra ................. 28 Logic Device ................................... 50,73 Rechenwerk ............................................. 331

Redundante Terme ..................................... 38 Reduzierter Stromverbrauch .................... 383


Referenz- geschwindigkeit ................................... 329 ladung .................................................. 225 netz ...................................................... l48 spannung ...................... 292,301,303,312 symbole ................................................. 26 speicherzellen ...................................... 225 variablen .............................................. 161

Refresh ..................................................... 228 werk ............................................. l61, 197 -zyklus ................................. 224, 228, 241 asynchron ....................................... 204

Register .................................... 335, 337, 339 synchron ......................................... 206 Bank Selector Bit... .............................. 353 synchron, Analyse ........................... 209 -aus gang ................................................ 75 synchron, Entwurf .......................... 210 -bank .................................................... 350 zeit ......................................................... 54 -bereich ................................................ 346 Schieberegister ......................................... 191 -feld ..................................................... 335 4 Bit... .................................................. l92

Relative Fehler ......................... 280, 286, 309 8 Bit.. ................................................... l93 Relokative Segmente ................................ 418 rückgekoppelt ...................................... 195 Remanent ................................................. 247 -betrieb ................................................ 368

-Iadung ................................................. 248 Schleifenstrukturblock .............................. 412 REN .......................................................... 367 Schmitt-Trigger ........................................ 163 Repräsentations- Schottky-TTL ....................................... 56, 57

größe ............................................ 271,272 Schreib-werte .................................................... 285 /Lesespeieher ....................................... 220

Reset.. ....................................................... 356 vorgang ........................................ 222, 249 -Logik .................................................. 206 zeiger ................................................... 245

Residuum ................................. 292,299, 300 zugriff des 8051 ................................... 389 Restfehler ................................................. 280 zyklus .................................. 223,227, 338 Restoring-Methode ..................................... ll SCON ....................................... 345, 352, 367 RETI. ........................................................ 380 Scratch Pad ............................................... 350 RI ............................................................. 367 SDRAM .................................................... 232 Ring Segmentierung .......................................... 418

der Dualzahlen ..................................... 8, 9 Sekundäranweisungen .............................. 422 -zähler .................................................. 195 Selektive Haltepunktsteuerung ................ .427

5 Bit. ............................................... l95 Self Refresh ...................................... 228, 238 ROM ................................................ 255, 332 Semaphoren .............................................. 242 Row .......................................................... 237 Semicustom IC ........................................... 51

Active .................................................. 239 Sendebetrieb ............................. 368, 370, 372 Addr. Strobe ........................................ 238 Sense Cache ................................................... 234 Amplifier ..................................... 225, 229

RS-232C ........................................... 363,364 -Verstärker. .......................... 237, 250, 251 RS-422 ..................................................... 364 Sequentielle RS-423 ..................................................... 364 Logik ................................................... l98 RS-Latch .................................................. 166 Schaltung ..................................... l61, 198 RSTNPD ......................................... 345, 386 Serial RTS .......................................................... 365 Control Register ................................... 354 Rückgabe .................................................. 439 Data Buffer .......................................... 354 Rückkopplungscodierer ............................ 292 Serielle Rücksetzbedingung, JK-FF ....................... l78 Datenübertragung ................................ 194 RXD .......................... 355, 365, 370, 371, 373 Ein-/ Ausgabe ....................................... 344

Schnittstelle ......................................... 366 S&H ......................................... 278, 298, 299 Serieller Port-lnterrupt. ............................. 378

Amplifier ............................................. 283 Serielles Interface des 8051 Sägezahnverfahren ........................... 302, 303 ModeO ................................................ 368 Sample&Hold-Glieder .............................. 279 Mode 1 ................................................ 370 SAR .................................................. 292, 295 Mode2 ................................................ 372 Sättigungsladung ...................................... 248 Mode 3 ................................................ 375 SBT .......................................................... 248 Serielle Port-lntermpt-SBUF ......................... 345, 352, 354, 370, 372 Freigabe ............................................... 379 Schalt- Priorität. ............................................... 379

algebra ................................................... 22 Serien-Parallel-Wandler ........................... 194


Settling time ..................................... 280, 318 SRAM ......................................... 81, 221,252 Setup time .......................................... 80, 172 -Caches ................................................ 234 Setz- -Verbindungszelle ................................. 84

bedingung,JK-FF ................................ 178 SSI ............................................................. 51 zeit. ........................................... 79, 80, 172 Stack

SFR ........................... 344, 349,351,352,355 Pointer ......................................... 335,355 SG ............................................................ 365 -Segment ............................................. 418 Shannon ................................................... 276 Standard-Shannonsches Gesetz ................................. 29 IC .......................................................... 51 SID ........................................................... 338 TTL ....................................................... 56 Sigma-Delta-Umsetzer ............................. 306 zellen ..................................................... 71 Signal- Stapel-

leistung ................................. 309, 310, 314 speicher ............................................... 335 proben ................................................. 277 zeiger ................................................... 335 Rauschabstand ..................................... 309 Start Conversion ....................................... 322 verarbeitung ................................ 274, 275 Statisches RAM ....................................... 221

Signal To Noise Ratio .............................. 319 STC .......................................................... 322 Signalbeschreibungsfeld .......................... 504 Std_logic .................................................... 95

externes ............................................... 506 Std_ulogic .................................................. 94 internes ................................................ 507 Step-Sensing-Approach ............................ 250

Signal- Steuer-konflikt .................................................. 95 block ................................................... 503 name ...................................................... 20 bus ............................................... 332,334 prozessoren .......................................... 328 logik .................................................... 346

Simulation ................................................ 137 werk .................................................... 331 SINAD ..................................................... 319 Stimuli ..................................................... 141 Single- Störspannungs-

length Lines ........................................... 87 abstand .................................................. 53 Step-Betrieb ........................................ 3 81 dynamischer ..................................... 54

Slave Serial Mode ...................................... 90 statischer .......................................... 53 SM0 ......................................................... 367 Unterdrückung ..................................... 305 SM1 ......................................................... 367 Strobesignal ............................................. 236 SM2 ......................................................... 367 Stromschalter ................................... 312, 321 Small Scale Integration .............................. 51 Struktograrnm .......................................... 411 SNR .......................................... 309, 314, 319 Strukturierung SOD ......................................................... 338 im Großen ..... , ..................................... 410 Software- imKleinen ........................................... 411

Engineering ................................. 328, 405 Stufenkennlinie ........................................ 314 Interrupts ............................................. 378 Subranging Quantisierer ........................... 299 Struktur Controller 8051 ..................... 390 Subtrahierer .............................................. 293

Sonderformen von A/D-Umsetzem .......... 302 Subtraktionsbefehle .................................. 398 Spaltenleitung .......................................... 226 Successive Spannungsteilerkette ........................ 289, 312 Approximation .................................... 292 Special Function Register .. 344, 349, 351, 352 Approximation Register ...................... 292 Speicher ............................ 219, 338-341, 343 Summation gewichteter Ströme ............... 311

-adresse ............................................... 219 Summationspunkt ............................ 278, 312 -bänke .................................................. 237 Switched capacitor circuits ....................... 295 -bausteine, Übersicht. .......................... 268 Symbolische Adressierung ....................... 420 -einheit ........................................ 344, 346 Synchrones DRAM .................................. 232 -erweiterung Synchronisierschaltung ............................ 210

8051 ............................................... 447 Systematische Fehler. ............................... 272 80515 ............................................. 445

-prinzip ................................................ 248 T&H ......................................................... 279 -werk ................................................... 331 T &H Amplifier ........................................ 283

Spezifikationsphase .................................. 407 TO ............................................................ 355 Sprung- und Verzweigungsbefehle .......... 403 Tl ............................................................ 355

Takt-Ausgangszeit ................................... 172


TB8 .......................................................... 367 Schottky- ......................................... 56, 57 TCON ....................................... 345,352, 360 Standard- ............................................... 56 Temperatur-Koeffizient. ................... 315, 316 TXD ................................. 355, 365, 370, 373 Testbench ................................................. 139

mit Ein- und Ausgabedatei .......... 141, 469 Übergabe .................................................. 438 mit Testvektoren .......................... 138, 467 Übergangs-

Test- bedingung phase .................................................... 407 D-FF, flankengesteuert ................... 173 vektoren ............................................... 138 D-FF, zustandsgesteuert .................. 170

Tetrade ..................................................... 149 JK-FF, flankengesteuert .......... l76, 179 Textdateien ............................................... 141 RS-FF, flankengesteuert ................. 172 TH0 .......................................................... 352 RS-FF, zustandsgesteuert ................ l69 THOffLO .................................................. 345 RS-Latch ......................................... 167 TH1 .......................................................... 352 funktion ............................................... 198 TH1m1 .................................................. 345 werte .................................................... 285 THALT ..................................................... 342 Über-THD ......................................................... 320 schwingzeit .................................. 280, 318 THOLD .................................................... 342 sprechen ............................................... 281 Three-State-Ausgang .................................. 59 tragungsrate ......................................... 364 TI ............................................................. 367 ULSI ........................................................... 51 Tiefpass .................................... 307, 309, 310 Ultra Large Scale Integration ...................... 51

-charakter ..................................... 276,310 Umsetz-Timer ................................................ 344, 359 dauer .................................... 277,278, 325

0 Overflow ........................................... 360 rate ....................................................... 301 0- und Timer 1-Interrupts .................... 378 verfahren .............................................. 295 0-Interrupt-Freigabe ............................. 379 zyklus .................................. 322, 324, 325 0-Interrupt-Priorität ............................. 379 Umsetzerstufe ........................................... 297 1 Overflow ........................................... 360 UND ........................................................... 22 1 Run Control ...................................... 360 UND-Feld ................................................... 74 1-Interrupt-Freigabe ............................. 379 Universal-ADU ........................................ 322 1-Interrupt-Priorität ............................. 379 Universeller PAL ........................................ 78 /Counter ............................................... 354 User definable Plag ................................... 353

Control Register ............................. 354 UV -löschbares, programmierbares ROM . 257 Timer-

Betrieb ................................................. 359 V.24 .................................................. 363, 364 ModeO ................................................ 361 vco ......................................................... 302 Mode 1 ................................................ 362 Vektoren ................................................... 197 Mode2 ................................................ 362 Venn-Diagramm ......................................... 38 Mode3 ................................................ 362 Verbindungsmatrix ..................................... 80

Ti-W-Fuse .................................................. 78 Vergleich .......................................... 291, 295 TL0 ........................................................... 352 CPLD-FPGA ......................................... 90 TL1 ........................................................... 352 Vergleichsschritt. ...................................... 289 TMOD ...................................... 345,352, 360 Verknüpfungs-Top Down-Entwurf ................................. .410 symbole ................................................. 23 Torzeit ...................................................... 302 zeichen ................................................... 22 Total Harmonie Distortion ........................ 320 Verstärkungsfehler ........................... 315, 316 Trace-Speicher ......................................... 427 Verteilungsdichte .............................. 320, 321 Track&Hold-Glieder ........................ 279, 282 Very Large Scale Integration ...................... 51 Tracking-Netzteile .................................... 318 Verzögerungszeit. ..................... 280,294, 301 Transferbefehle ......................................... 395 VHDL. ........................................................ 91 Transistor-Transistor-Logik ........................ 56 Aggregate ............................................ 132 Transmit Interrupt Flag ............................. 367 Alias-Deklaration ................................ 114 TRAP ....................................................... 338 Arbeitsbibliothek ................................. 118 TTL ...................................................... 53, 56 Architecture ........................................... 98

Advanced LS ......................................... 56 Assertion-Anweisung .......................... 113 Advanced-Schottky- .............................. 56 Association Low Power Schottky- ............................ 56 named ............................................. 132


positional ........................................ 132 Library ................................................ 118 Attribute .............................................. 134 Literals ................................................ 127 Auflösungsfunktionen ......................... 115 Modus Behavioral Description .......................... 98 Buffer ............................................... 94 Beispiel In .................................................... 94

Funktion ......................................... 112 Inout ................................................. 94 Packagei-Body ............................... 116 Out ................................................... 94 Prozedur ......................................... 111 Nebenläufige Strukturbeschreibung ..................... 109 Anweisung ....................................... 98 Verhaltensbeschreibung ................. 106 Signalzuweisung .............................. 99

Bezeichner ........................................... 124 Next- und Exit-Anweisung .................. 106 Bibliothek ............................................ 118 Objektklassen ...................................... 125 Block-Anweisung ................................ 119 Dateien ........................................... 125 Block-Konfiguration ........................... 122 Konstanten ..................................... 126 Case-When-Anweisung ....................... 105 Signale ........................................... 126 Component .......................................... l07 Variablen ........................................ 126 Concurrent Statement.. .......................... 98 Operanden ........................................... 135 Datenobjekte ................................. 93, 125 Operatoren ................................... 135, 136 Datentypen .................................... 94, 127 addierende ...................................... 135

Arrays ............................................. 130 logische .......................................... 135 Aufzähl- ......................................... 129 multiplizierende .............................. 135 bit,bit_ vector .................................... 94 Schiebe- und Rotations- ................. 135 Fließkomma- .................................. 129 Vergleichs- ..................................... 135 Integer- ........................................... 128 vermischte ...................................... 135 physikalische .................................. 129 Vorzeichen- .................................... 135 Records .......................................... 130 Overloading ......................................... ll4 skalare ............................................ 128 Package ............................................... ll5 std_logic,std_logic_ vector ................ 94 Package-Body ..................................... 116 zusammengesetzte .......................... 130 Parameter

Entity ..................................................... 93 aktuelle ........................................... 108 Entity-Deklaration ................................. 93 formale ........................................... 108

mit Entity-Anweisungen ................... 97 lokale .............................................. 108 mit Parameterübergabe ..................... 97 Port ........................................................ 93 ohne Parameterübergabe .................. 96

For-Loop-Anweisung .......................... 106 Port Map ............................................. 110 Primäreinh~it ....................................... 118

Function .............................................. 111 Procedure ............................................ llO Funktion .............................................. 111 Prozedur .............................................. 110 Generate-Anweisung ........................... 118 Prozess ................................................ 103 Größen ................................................ 127 sensitive Signale ............................. 103

Bit-String- ...................................... 128 sensitivity _Iist ................................ 103 Character-....................................... 128 Wait-Anweisung ............................ 103 Integer- ........................................... 127 Prozess-Anweisung ............................. 103 numerische ..................................... 127 Report-Anweisung .............................. 113 physikalische .................................. 127 Reservierte Wörter .............................. 125 Real- ............................................... 127 Resolution Functions ........................... 115 String- ............................................ 128 Schlüsselwörter .. .. .. .. .. . . . . .. . .. .. .. .. .. .. . . .. . . 125

Grundbegriffe ...................................... 124 Sekundäreinheit.. .. . . . . . .. .. . . .. .. ... . . . . .. . . . . .. 118 Guarded Signal Assignment ................ 119 Selected Names ................................... 132 ldentifier ........ ,· ..................................... 124 Sequentielle If-Then-Else-Anweisung ..................... 105 Variablenzu~eisung ....................... 105 Indexed Names .................................... 131 Anweisung ..................................... 104 Kommentare ........................................ 125 Signalzuweisung ............................ 104 Komponenten ...................................... 107 Sliced Names ...................................... 132

-Deklaration ................................... 108 Structural Description ......................... 107 -lnstantiierung ................................ 108 Strukturbeschreibung .......................... 107 -Konfiguration ................................ 120 Subprogram ......................................... 110

Konfiguration ...................................... 119 Subtypes .............................................. 133


Überladen ............................................ 114 XTAL1 ..................................................... 386 Unterprogramm ................................... 110 XTAL2 ..................................................... 386 Use-Anweisung ................................... 115 Vektor .................................................... 94 Zähler ....................................................... 180 Verhaltensbeschreibung ......................... 98, asynchron ............................................ 180 When-Else-Anweisung ........................ lOO dual ................................................. l80 While-Loop-Anweisung ...................... 106 kaskadiert ....................................... 182 With-Select-When-Anweisung ............ I 00 modulo 6 ......................................... 183

ViaLink -Element ........................................ 81 modulo m ........................................ l82 Video-RAM .............................................. 243 dual, 4-Bit-vorwärts ............................. l85 Vierer-Burst. ............................................. 239 synchron .............................................. 184 VLSI. .......................................................... 51 synchron, dual... .............................. 184 Vollduplex ................................................ 366 modulo 10 ....................................... 189 Von-Neumann-Architektur ....................... 346 modulo m ........................................ l89 Vorrangregeln ............................................. 23 vorwärts, dual ...................................... 181 VRAM ...................................................... 243 Zählverfahren ........................... 295,301, 302

Zeilenspeicher .......................................... 234 Wäge- Zeit-

codierer. ....................................... 292, 300 diskretisierung ..................................... 276 verfahren ...................... 290,291, 293, 298 konstanten ............................................ 280

Wahrheitstabelle ......................................... 18 multiplex .............................................. 348 Warte- Zeitliche Struktur ...................................... 387

zustände ............................................... 324 Zentraleinheit ............ 331, 335, 339, 344, 346 zyklen .......................................... 325, 326 Zero Error ................................................. 315

Wartungsfreundlichkeit ............................ 406 Zuordnungssystem ...................................... 16 Watchdog ................................................. 446 Zustand .............................................. 340-343 WE ........................................................... 238 Zustands-Wert- diagramm .............. 199,200, 240, 340-342

diskretisierung ............................. 272, 276 folgetabeHe .................................. 199, 201 kontinuierlich ............................... 271, 272 gesteuert .............................................. 169

Wettlauf .................................................... 207 gesteuertes Flipflop .............................. l69 Wide Edge Decoder .................................... 86 reduzierung .......................................... 203 Wired-Verknüpfung ................................... 61 vektor. .................................................. l97 Wortleitung .............................................. 249 diagramm ..................... 240,340, 341, 342 WR ........................................... 338, 346, 355 steuerung ............................................. 378 Write ......................................................... 237 Zuverlässigkeit ......................................... 406

Enable .................................................. 238 Zweierkomplement ....................................... 6 WR-RD Mode .......................................... 325 -code ............................................ 286, 287

Zweistufige Logik ...................................... 31 XON/XOFF-Prozedur .............................. 365 XSEG ....................................................... 420

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