routing for manufacturability and...

10
Routing for Manufacturability and Reliability Huang-Yu Chen 1 , Yao-Wen Chang 1,2 1 Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan 2 Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan E-mails: [email protected]; [email protected] Abstract— As IC process geometries scale down to the nanome- ter territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability. I. I NTRODUCTION As the process geometries scale down to the nanometer territory, the IC industry faces severe challenges in manufacturability and reliability. Among these challenges, optical proximity correction (OPC), chemical-mechanical polishing (CMP), and double-patterning technology (DPT) are current major issues for manufacturability, and antenna effect avoidance and double-via insertion are often adopted for reliability. Those issues are often tackled at the post-layout stage. Nevertheless, with the fast-growing design complexity, it is desirable to handle these issues earlier at the routing stage to provide higher flexibility for the optimization. Consequently, we shall focus our discussions on routing for these challenges. II. ROUTING FOR MANUFACTURABILITY For manufacturability, OPC and CMP are two most important concerns for modern chip designs. The former adds or subtracts feature patterns to a mask to enhance the layout resolution and thus the printability of the mask patterns on the wafer, while the latter improves layout uniformity and chip planarization to achieve higher manufacturing yield. A. OPC-Aware Routing We shall first briefly introduce the manufacturing process. The process uses an optical lithography system and goes through many cycles of processing, each of which consists of two major steps: exposure followed by etching. Figure 1 illustrates a basic optical lithography system. In the exposure step, it transfers the patterns on a mask to the light-sensitive positive or negative photoresist coated on the top of the wafer, which is performed by an intense ultraviolet light emitted from the light source via the apertures of the mask. Exposed by the light, the positive photoresist becomes soluble to the photoresist developer, while the negative photoresist becomes insoluble. This chemical change allows some of the photoresist to be removed by a special solution. In the etching step, a chemical agent removes the uppermost layer of the wafer in the areas that are not protected by photoresist to form the designed patterns on the wafer. With the continuous shrinking of the minimum feature size, IC foundries have to use an optical lithography system with a larger wavelength of light to print a feature pattern with a much smaller size on a wafer, which is called the sub-wavelength lithography gap (see Figure 2). For the modern process technology, for example, we might need to print a 45nm feature pattern by using the light of Projection lens Light source Mask Wafer Projection lens Photoresist Fig. 1. A typical optical lithography system. 193nm wavelength. The sub-wavelength lithography gap might lead to unwanted large shape distortions for the printed patterns on the wafer. Physically, when a light with the wavelength λ passes through an aperture of the size d, the wavefronts of the light behave differently according to the relation between λ and d. When λ is much smaller than the aperture size d on the mask, the wavefronts of the light remain straight, as illustrated in Figure 3(a). However, when λ is close to or larger than d, the light behaves like waves (instead of particles) and diffraction occurs (see Figure 3(b)), making the pattern on the wafer not exactly the same as that on the mask. As a result, intensive use of costly resolution enhancement techniques (RETs) to improve the layout accuracy becomes inevitable. Many RETs are adopted at the post-layout stage to enhance the printability and thus the yield. The increasing design complexity, however, leaves very limited space for post-layout optimization. Therefore, it is desirable to consider the manufacturability earlier in the design flow, such as RET-aware routing. Among the RETs, optical proximity correction (OPC) is most popular in industry. OPC is the process of modifying the layout patterns on the mask (drawn by the designers) to compensate for the non-ideal properties of the lithography process and thus to enhance the layout printability. Figure 4 illustrates an example of OPC enhancement. Without OPC, the printed patterns on the wafer would be distorted from the designed pattern on the mask due to the sub-wavelength lithography. In contrast, if the patterns on the mask are enhanced by OPC, the printed patterns on the wafer could well match the original designed patterns. However, OPC might incur a large number of extra pattern features, implying larger memory requirements and longer time to record and process these features, and thus higher mask-making costs, such as mask synthesis, writing, and inspection verification. If a router can consider the optical effects, the number of pattern features on the

Upload: vanhanh

Post on 02-Sep-2018

231 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

Routing for Manufacturability and Reliability

Huang-Yu Chen1, Yao-Wen Chang1,2

1Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan2Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan E-mails: [email protected]; [email protected]

Abstract— As IC process geometries scale down to the nanome-ter territory, industry faces severe challenges of manufacturinglimitations. To guarantee high yield and reliability, routingfor manufacturability and reliability has played a pivotal rolein resolution and thus yield enhancement for the imperfectmanufacturing process. In this article, we introduce majorrouting challenges arising from nanometer process, survey keyexisting techniques for handling the challenges, and provide somefuture research directions in routing for manufacturability andreliability.

I. I NTRODUCTION

As the process geometries scale down to the nanometer territory,the IC industry faces severe challenges in manufacturability andreliability. Among these challenges,optical proximity correction(OPC),chemical-mechanical polishing(CMP), anddouble-patterningtechnology(DPT) are current major issues for manufacturability, andantenna effectavoidance anddouble-via insertionare often adoptedfor reliability. Those issues are often tackled at the post-layout stage.Nevertheless, with the fast-growing design complexity, it is desirableto handle these issues earlier at the routing stage to provide higherflexibility for the optimization. Consequently, we shall focus ourdiscussions on routing for these challenges.

II. ROUTING FORMANUFACTURABILITY

For manufacturability, OPC and CMP are two most importantconcerns for modern chip designs. The former adds or subtractsfeature patterns to a mask to enhance the layout resolution and thusthe printability of the mask patterns on the wafer, while the latterimproves layout uniformity and chip planarization to achieve highermanufacturing yield.

A. OPC-Aware RoutingWe shall first briefly introduce the manufacturing process. The

process uses an optical lithography system and goes through manycycles of processing, each of which consists of two major steps:exposurefollowed by etching.

Figure 1 illustrates a basic optical lithography system. In theexposure step, it transfers the patterns on a mask to the light-sensitivepositive or negative photoresist coated on the top of the wafer, whichis performed by an intense ultraviolet light emitted from the lightsource via the apertures of the mask. Exposed by the light, the positivephotoresist becomes soluble to the photoresist developer, while thenegative photoresist becomes insoluble. This chemical change allowssome of the photoresist to be removed by a special solution. In theetching step, a chemical agent removes the uppermost layer of thewafer in the areas that are not protected by photoresist to form thedesigned patterns on the wafer.

With the continuous shrinking of the minimum feature size, ICfoundries have to use an optical lithography system with a largerwavelength of light to print a feature pattern with a much smallersize on a wafer, which is called thesub-wavelength lithography gap(see Figure 2). For the modern process technology, for example, wemight need to print a 45nm feature pattern by using the light of

Projection lens

Light source

Mask

Wafer

Projection lens

Photoresist

Fig. 1. A typical optical lithography system.

193nm wavelength. The sub-wavelength lithography gap might leadto unwanted large shape distortions for the printed patterns on thewafer. Physically, when a light with the wavelengthλ passes throughan aperture of the sized, the wavefronts of the light behave differentlyaccording to the relation betweenλ andd. Whenλ is much smallerthan the aperture sized on the mask, the wavefronts of the lightremain straight, as illustrated in Figure 3(a). However, whenλ isclose to or larger thand, the light behaves like waves (instead ofparticles) and diffraction occurs (see Figure 3(b)), making the patternon the wafer not exactly the same as that on the mask. As a result,intensive use of costlyresolution enhancement techniques(RETs) toimprove the layout accuracy becomes inevitable.

Many RETs are adopted at the post-layout stage to enhance theprintability and thus the yield. The increasing design complexity,however, leaves very limited space for post-layout optimization.Therefore, it is desirable to consider the manufacturability earlierin the design flow, such as RET-aware routing.

Among the RETs,optical proximity correction(OPC) is mostpopular in industry. OPC is the process of modifying the layoutpatterns on the mask (drawn by the designers) to compensate forthe non-ideal properties of the lithography process and thus toenhance the layout printability. Figure 4 illustrates an example ofOPC enhancement. Without OPC, the printed patterns on the waferwould be distorted from the designed pattern on the mask due to thesub-wavelength lithography. In contrast, if the patterns on the maskare enhanced by OPC, the printed patterns on the wafer could wellmatch the original designed patterns.

However, OPC might incur a large number of extra patternfeatures, implying larger memory requirements and longer time torecord and process these features, and thus higher mask-making costs,such as mask synthesis, writing, and inspection verification. If a routercan consider the optical effects, the number of pattern features on the

Page 2: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

Fig. 2. The sub-wavelength lithography gap: the printed feature size issmaller than the wavelength of the light shining through the mask.

Wafer

Mask

Photoresist

Wafer

Mask

Photoresist

(a) (b)

d

< d > d

d

Fig. 3. When a light with the wavelengthλ passes through an aperture of thesized, the wavefronts of the light behave differently according to the relationbetweenλ andd. (a) Whenλ is much smaller thand, the wavefronts remainstraight. (b) Whenλ is much larger thand, diffracted wavefronts might occur.

final mask can greatly be reduced.Chen and Chang proposed arule-basedOPC-aware multilevel

router to reduce the requirements for OPC-pattern feature [1]. Theyhandled the pattern distortions based on the three major types:cornerrounding, line-end shortening, andline-width shrinking, as illustratedin Figures 5(a)–(c). For each type of distortions, the pattern featuresrequired for compensation are identified based on some geometryrules; for example,serifs are added at corners to make the anglessharper,hammerheadsare added at line ends to compensate forline-end shortenings, andline biasingsare added along line sidesto compensate for line-width shrinking (see Figure 6).

The number of pattern features required for OPC is then modeledas a cost for routing a connection. For example, as shown inFigure 6(a), four serifs are required to add at the four corners toincrease the fidelity of images for a line. Also, when the length of aline increases, the ends of the line become shortened, as illustrated inFigure 6(b); therefore, two hammerheads are required to add at theline ends for a long line. Besides, a wider line is easier to be affectedby neighboring lines than a narrower one, making the sides of a lineshrink more seriously. Therefore, as shown in Figure 6(c), some linebiasings in the line sides are required to be added for a wide line.

Patterns

on the mask

Printed patterns

on the wafer

OPC-enhanced patterns

on the mask

(a)

(b)

Printed patterns

on the wafer

Fig. 4. The effects of OPC: (a) without OPC, the printed patterns on thewafer incur large distortions from the patterns on the mask, and (b) with OPCenhancement, the printed patterns could well match the original patterns.

(a) (b) (c)

Fig. 5. Three major types of pattern distortions (the dashed lines representthe ideal pattern shapes): (a) corner rounding, (b) line-end shortening, and (c)line-width shrinking.

(a) (b) (c)

Fig. 6. Three major OPC compensation pattern features: (a) serif, (b)hammerhead, and (c) line biasing.

Therefore, the total number of additional features for a line can bemodeled as a function of the length and width of the line. With thisfunction, we can incorporate the OPC cost into the original routabilityand wirelength costs for a router to obtain a rule-based OPC-awarerouting methodology.

Chen, Liao, and Chang recently considered the OPC effects duringrouting to alleviate the cost of post-layout OPC operations [2]. Theydeveloped an analytical formula for the intensity computation bycurve fitting simulated intensity data, i.e.,model-based OPC(whichinvolves complicated simulations of various process effects), and

Page 3: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

a post-layout OPC modeling based on aquasi-inverse lithographytechnique, and then incorporated the OPC costs into an OPC-friendlyrouter.

As illustrated in Figure 7, the function of a wafer pattern can becomputed by the convolution of the function of a mask pattern and thekernel function that models the light wave. Therefore, the function ofthe mask pattern can be computed by the convolution of the functionof the wafer pattern and the inverse kernel function.

Kernel function

Mask pattern

Wafer pattern

+

Fig. 7. Relationship among the light wave, a mask pattern, and awaferpattern.

During the post-layout OPC process, an OPC tool is used to addpatterns to modify the original layout. The modified layout may notbe unique and is typically hard to predict. With the relationshipamong the kernel function, the mask pattern, and the wafer patternin mind, however, we can predict the required free spaces for post-layout OPC patterns. Chen, Liao, and Chang proposed a quasi-inverselithography technique to predict the required free spaces for OPCprocessing.

Figure 8 illustrates this technique for OPC demand calculation.First, they use the fitted intensity formula to obtain the originalintensity map for a layout. Second, the insufficient intensity mapis computed by subtracting the values in the target intensity mapfrom the corresponding ones in the original intensity map. Third, theinsufficient amplitude map is computed by the square root of theinsufficient intensity. Note that insufficient amplitude makes somedesign shapes not able to be printed clearly in the final layout. Sothe insufficient amplitude map can quantify this insufficient amplitudefor a layout to be printed clearly. Fourth, given the light source andparameters, we can obtain its kernel function and then its inversekernel function. The kernel function models the impact of a point onthe mask on other points on the wafer; therefore, the quasi-inversekernel function models the effect of the points on a wafer on one pointin the mask. In other words, the quasi-inverse kernel function capturesthe amplitude interaction and is used to propagate the amplitudedemand from the routed patterns. Fifth, the OPC demand map iscomputed by the convolution of the quasi-inverse kernel functionand the insufficient amplitude map. The OPC demand map modelsthe OPC cost for an OPC-aware routing. A point with a larger OPCdemand implies a higher probability for adding an OPC pattern atthe point by a post-layout OPC tool. Therefore, we shall reservethose points with larger OPC demands in the routing stage for post-layout OPC processing to prevent from a time-consuming layoutmodification process. Finally, the OPC demand cost is incorporatedinto an OPC-friendly router to find a desired path with the minimumOPC cost.

Huang and Wong, Wuet al., and Mitra et al. also addressedOPC-aware routing [3]–[5]. All of these works (and the work [1])focused on OPC-aware routing based on the interference between netsduring routing and did not consider the potential post-layout OPCchange. Choet al. proposed a correct-by-construction OPC-awarerouter [6]. Based on statistical characterization, they presented a post-OPC lithography cost metric by considering the interference amongweak grids filled with lithography-critical shapes such as corners,

Inverse-like kernel function

Kernel function

OPC demand map

Insufficient

intensity map

Original

intensity map

Insufficient

amplitude map

Fig. 8. Illustration of the quasi-inverse lithography technique for OPCdemand calculation.

vias, and line ends. This cost metric is then used to guide detailedrouting to find desired paths.

B. CMP-Aware RoutingIn the modern metallization process, copper (Cu) has replaced

the traditional aluminum (Al) due to its better properties, such ashigher current-carrying capability, lower resistance, and lower cost.However, the process of copper is significantly different from thatfor traditional aluminum. The modern copper metallization processapplies thedual-Damascene process[7], which consists ofelectro-plating (ECP) followed bychemical-mechanical polishing(CMP).The ECP deposits the copper on the trenches, while the CMP removesthe copper that overfills the trenches, as shown in Figures 9(a)-(c).

Figure 10 shows a schematic diagram of the CMP process. Abra-sive and corrosive chemicalslurry that can dissolve the wafer layeris deposited on the surface of a polishing pad. Then, the polishingpad and wafer are pressed together by a dynamic, rotating polishinghead. Combined with both the chemical reaction and the mechanicalforce, the CMP process can remove materials on the surface of waferand tends to make the wafer planar.

Slurry

Polishing pad

Polishing head

Wafer

Fig. 10. Schematic diagram of the CMP polisher.

However, because of the difference in the hardness between copperand dielectric materials, the CMP planarizing process might generatetopography irregularities, which might incur significant yield loss ofcopper interconnects. The studies of the CMP process have indicatedthat the post-CMP dielectric thickness is highly correlated to thelayout pattern density, because during the polishing step, the dielectricremoval rates are varied with the pattern density. A non-uniformfeature density distribution on each layer might cause CMP to overpolish or under polish, as illustrated in Figure 11.

These post-CMP thickness variations need to be carefully con-trolled, since the variation in one metal layer could be progressivelytransferred to subsequent layers during manufacturing, and finally theaccumulative variation could be significant on the upper metal layer,which is often called themulti-layer accumulative effect[8].

Page 4: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

(a) (b) (c)

Fig. 9. Damascene process: (a) Open trenches, (b) Electroplating (ECP) deposits Cu on the trenches, and (c) Chemical-mechanical polishing (CMP) removesCu that overfills the trenches.

Oxide

polishing pad slurry

oxidemetal

oxide

(a) (b)

Fig. 11. Layout-dependent thickness variations: (a) Pre-CMP layout and (b)Post-CMP thickness variation.

In order to improve the CMP quality, modern foundries oftenimpose recommended layout density rules (or even density gradientrules) on each layer and filldummy featuresinto layouts to reducethe variations on each layer. However, these filled dummy featuresmight incur unwanted effects at 65nm and successive technologynodes [9]. For example, they may induce high coupling capacitancesto nearby interconnects and thus incur crosstalk problems. Moreover,dummy fills also significantly increase the data volume of mask,lengthening the time of mask-making processes and thus the maskcost. Especially, these filled features would significantly increase theinput data in the following time-consuming RETs, such as the OPCprocess.

Wire density greatly affects dummy feature filling. The layoutpattern (consisting of wires and dummy features) density strongly de-pends on the wire density distribution, as reported in [10]. Therefore,controlling wire density at the routing stage can alleviate the problemsinduced by aggressive dummy feature filling. Additionally, good wiredistribution can reduce the random particle short defects and alsobenefit the post-layout redundant-via insertion (see Section IV-B),which can translate into yield gain.

The density uniformity in different routing stages for CMP vari-ation control has been addressed in the literature [10]–[12]. Choet al. considered CMP variation during global routing [10]. Theyempirically showed that the number of inserted dummy featurescan be predicted by the wire density and observed that a pathwith higher pin density may not get much benefit from the wiredensity optimization since there is little room for improvement (it isdestined to have high wire density from the beginning). Therefore,they proposed aminimum pin-density global-routingalgorithm toreduce the maximum wire density.

Figure 12 illustrates the minimum pin-density global-routing al-gorithm. A net from the sourceS to the targetT to be routed isshown in Figure 12(a) with a pin distribution. If only the L-shaped(1-bend) routing paths are allowed, there are two possible paths,aandb, with the same wirelength but different pin densities. Since theexistence of a pin implies at least one connection to other pins, apath with higher pin density likeb would tend to have higher wiredensity eventually as shown in Figure 12(b), resulting in higher finalwire densities. Therefore, a path with the minimum pin density (likepatha) leads to better wire density distribution.

(a) (b)

S

T

S

T

Fig. 12. Minimum pin-density global routing [10]: (a) There are two possible1-bend pathsa and b from the sourceS to the targetT and (b) The pathawith smaller pin density is better than the pathb.

C. DPT-Aware RoutingDue to the persistent technical problems on the 157-nm optical

lithography and the immaturity and infrastructure challenges of thenext-generation 13.5-nm EUV (extreme ultraviolet) and e-beam litho-graphy, it is expected to continue using the illumination wavelengthof 193 nm for 45-, 32-, and 22-nm technology nodes in the nearfuture.

Double-patterning lithography(DPT) has received more attentionand interest recently [13], [14], since it can increase the half-pitchresolution by up to two times using current infrastructures, therebyextending the 193-nm immersion lithography beyond the 32-nm nodeand potentially down to the 16-nm node. Currently, DPT mainlytargets on the critical patterns or advanced devices such as NANDflash memory, but it is expected to apply on most designs in thenearest future.

Although there are different approaches of DPT [15], the under-lying principle is based onpitch relaxation, which splits a densemask into two less-dense masks and then sequentially prints (exposesfollowed by etches) each mask on a target wafer. For example (seeFigure 13), a dense layout with 32-nm line width and 64-nm pitch canbe manufactured by two complementary masks with 32-nm line widthand more relaxed 128-nm pitch, which enlarges process windows andenhances the depth of focus (DOF) and exposure latitudes (EL) [16].

In DPT, a pair of two untouched patterns of the same layer wouldbecome aconflict if their distance is less than or equal to asplittingdistanceprovided by foundries, denoted byDs, which represents theminimum distance allowed in each DPT mask. If a pattern is splitinto different DPT masks, the dividing point between different maskson this pattern is called astitch.

Like the phase assignment problem in Alt-PSM (alternating phase-shift mask) [17], it seems a natural way to find a DPT layoutdecomposition solution through applying a 2-coloring algorithm ina conflict graph. However, as mentioned in [21], the DPT layoutdecomposition problem has higher complexity than Alt-PSM. One ofthe reasons is that inserting stitches in DPT can break the odd-lengthcycles in a conflict graph and thus resolves some hard-to-resolve

Page 5: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

dense mask less-dense mask #1 less-dense mask #2

+

64nm

32nm

128nm

32nm

128nm

32nm

Fig. 13. The pitch relaxation of DPT. A dense layout can be manufacturedby two complementary masks with more relaxed pitch.

conflicts.Figure 14 illustrates the terminologies. By setting the splitting

distanceDs as α, five possible-conflict patterns{p1,p2}, {p1,p3},{p2,p3}, {p3,p4}, {p4,p5} exist as in Figure 14(a). Without usingstitches, a popular layout decomposition method, such as the nat-ural split decomposition (NSD) mentioned in [18], would assign{p1,p2,p4} to DPT mask #1 and{p3,p5} to DPT mask #2, but wouldresult in a conflict betweenp1 andp2 as shown in Figure 14(b). Byinserting a stitch inp1 that assigns respectivep1a and p1b to DPTmasks #2 and #1, a better decomposition could be achieved withoutany conflicts as shown in Figure 14(c).

Notice that besides the conflict issues, it is also desirable to min-imize the stitches since stitches may induce printability degradationcaused by line-end shortening.

Existing approaches often focus on post-layout DPT decompo-sition [19], [20]; however, the increasing design complexity leavesvery limited space for post-layout optimization. It has been reportedthat considering DPT during routing can improve the quality oflayout significantly in terms of decomposability and the number ofstitches [19]. Therefore, it is desired to consider double-patterningearlier at the routing stages.

In [21], Cho, Ban, and Pan proposed the first DPT-aware detailedrouting algorithm. They first proposed a path-coloring algorithmwhich decomposes a given routing path while minimizing the numberof stitches. Then they developed a DPT-friendly detailed routingalgorithm which simultaneously finds a DPT-friendly routing pathand corresponding layout decomposition for each net. Experimentsshowed that the DPT-compatible layout generated by their DPT-aware routing outperforms the current industrial sequential approach(routing followed by DPT layout decomposition) for both quality andruntime.

III. ROUTING FORRELIABILITY

Manufacturing reliability and yield in VLSI designs are becominga crucial challenge as the feature sizes shrink into the nanometerscale. Both the antenna effect arising in the plasma process and thevia-open defect are important issues for achieving a higher reliabilityand yield.

IV. ROUTING FORRELIABILITY

Manufacturing reliability and yield in VLSI designs are becominga crucial challenge as the feature sizes shrink into the nanometerscale. Both the antenna effect arising in the plasma process and thevia-open defect are important issues for achieving a higher reliabilityand yield.

A. Antenna-Avoidance RoutingThe antenna effectis caused by the charges collected on the

floating interconnects which are connected to only a gate oxide.During the metallization, long floating interconnects act as temporarycapacitors and store charges gained from the energy provided byfabrication steps such as plasma etching and CMP. If the collected

charges exceed a threshold, theFowler-Nordheim(F-N) tunnelingcurrent will discharge through the thin oxide and cause gate damage.On the other hand, if the collected charges can be released beforeexceeding the threshold through a low impedance path, such asdiffusion, the gate damage can be avoided.

For example, considering the routing in Figure 15(a), the intercon-nects are manufactured in the order of poly, metal 1, and metal 2.After manufacturing metal 1 (see Figure 15(b)), the collected chargeson the right metal 1 pattern may cause damage to the connected gateoxide. The discharging path is constructed after manufacturing metal2 (see Figure 15(c)), and thus the charges can be released throughthe connected diffusion on the left side.

There are three kinds of solutions to reduce the antenna effect [22]:1) Jumper insertion: Break only signal wires with antenna

violation and route to the highest level by jumper insertion.This reduces the charge amount for violated nets duringmanufacturing.

2) Embedded protection diode: Add protection diodes on everyinput port for every standard cell. Since these diodes areembedded and fixed, they consume unnecessary area whenthere is no violation at the connecting wire.

3) Diode inserting after placement and routing: Fix those wireswith antenna violations that have enough room for “under-the-wire” diode insertion. During wafer manufacturing, all theinserted diodes are floating (or ground). One diode can be usedto protect all input ports that are connected to the same outputports. However, this approach works only if there is enoughroom for diode insertion.

Jumper insertion is a popular way to solve the antenna problem.To avoid/fix the antenna violation, it is required that the total effectiveconductor connecting to a gate be less than or equal to a threshold,Lmax. The threshold could be the wire length limit, the wire arealimit, the wire perimeter limit, the ratio of antenna strength (length,area, perimeter, etc) to the gate size, or any model of the strengthof antenna effect caused by conductors. As the example shown inFigure 18, we have a two-terminal net in whicha is the source nodeandb is the terminal node. In this case, the antenna charge weight ofb is the sum of the antenna charge weight of segments 4, 5, and 6,which may violateLmax. Note that once segment 3 is manufactured,a discharging path is established through segment 1 and the diffusionof the transistor a (see Figure 18(b)). If we add a jumper at the longsegment 5 (see Figure 19), the antenna charge weight ofb is just thesum of the length of segments 8, 9, and 10, which will not violateLmax. Thus, if we add jumpers appropriately, the antenna problemcan be easily solved.

a b

Metal 1

Metal 2

Metal 3

a

b

1 5

2 4

3 Metal 3

Metal 2

Metal 1

Poly6

(a)

(b)

Fig. 16. (a) A two-pin net and (b) The cross section view.

Page 6: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

(c)(a) (b)

p1

p2

p3p4

p5

p1

p2

p3p4

p5

p1a

p2

p3p4

p5

p1b

DPT

mask #1

DPT

mask #2

Original

mask Stitch Conflict

2

Fig. 14. Terminologies of DPT layout decomposition: (a) For a splitting distanceDs = α, five possible-conflict patterns{p1,p2}, {p1,p3}, {p2,p3},{p3,p4}, {p4,p5} exist in a given grid-based layout. (b) A layout decomposition assigning{p1,p2,p4} to mask #1 and{p3,p5} to mask #2 results in aconflict betweenp1 andp2. (c) After splitting p1 into p1a andp1b by a stitch, a better layout decomposition result incurs no conflict.

Metal 2

Metal 1

Poly LayerDiffusion

Gate

+ + + + + + + + + + + + + +

+ + + + + + + + + + + +

+ + + + + + +

+ + + ++ + +

Collected

Charges

Damage

the gate

+ + + + + + + + + + + + +

+ + + + + + + + + + + + + + + + + + +

+ + + + + + + + + + +

+ + + + + + + + + +

Discharge

through the

diffusion

Fig. 15. Illustration of the antenna effect: (a) A routing example, (b) Late stage of metal-1 pattern etching of (a), where the collected charges on the rightside of the metal-1 pattern may cause damage to the connected gate oxide, and (c) Late stage of metal-2 pattern etching of (a), where all the collected chargescan be released through the connected diffusion on the left side.

Antenna avoidance by jumper insertion has been extensively stud-ied in the literature (e.g., [23]–[26]). Ho, Chang, and Chen proposedmultilevel routing considering antenna effects by bottom-up jumperinsertion [23]. The work inserts jumpers only beside gate terminals,and its optimality of using the least jumpers to satisfy the antennarule holds only for this special condition of inserting jumpers rightbeside gate terminals. Wu, Hu, and Mahapatra extended the work [23]to handle the problem [24]. To fix the antenna violation of a gateterminal, the work first removes all subtrees around the node thatviolate the antenna rules. After all such subtrees are removed, if thesink still violates the antenna rule, the work will continually removethe heaviest branch from the sink until the antenna rules are satisfied.This approach still cannot guarantee optimal solutions under somespecial cases.

Su and Chang formulated the general jumper insertion for antennaavoidance (applicable at the routing stage) and/or fixing (applicableat the post-layout stage) as a tree-cutting problem on a routingtree and presented the first optimal algorithm for the general tree-cutting problem [26]. As usual, a net is modelled as a routing tree,where a node in the tree denotes a circuit terminal/junction (a gate,

diffusion, or a junction of interconnects) and an edge denotes theinterconnection between two circuit terminals or junctions. Since theinterconnection connecting to a diffusion terminal will not cause anyantenna violation, the algorithm focuses on those connecting to gateterminals.

Let L(u) denote the sum of edge weight (could be wirelength, wirearea, wire perimeter limit, the ratio of antenna strength, etc) betweenthe nodeu and all its neighbors. The problem of jumper insertionon a routing tree for antenna avoidance/fixing can be formulated asa tree-cutting problem as follows:

Jumper Insertion on a Routing Tree for Antenna AvoidanceProblem:Given a routing treeT = (V, E) and an upper boundLmax, find theminimum setC of cutting nodes,e 6= u for any c ∈ C andu ∈ V ,so thatL(u) ≤ Lmax, ∀u ∈ V .

As the routing-tree example shown in Figure 18(a),u1 andu2 aretwo sink nodes, the number beside each edge denotes the antennacharge weight, andLmax is assumed to be 10. For this case, threejumpers suffice to solve the antenna violations; see the jumpersc1,c2, andc3 shown in Figure 18(b).

Page 7: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

a b

a

b

1 5

2 4

3

10

Metal 1

Poly

6 8

7 Metal 3

Metal 2

9

(a)

(b)

Metal 1

Metal 2

Metal 3

Fig. 17. (a) A two-pin net with jumper insertion and (b) The cross sectionview.

(a)

(b)

Fig. 18. (a) A routing tree with two sink nodesu1 and u2 and (b) Threejumpersc1, c2, c3 are inserted to satisfy the antenna rule.

The algorithm performs in a bottom-up manner by dealing withleaf nodes first followed by sub-leaf nodes of the tree. Here, a leafnode is a node with no children, whereas a sub-leaf node is a nodefor which all its children are leaf nodes, and if any of its childrenis a gate terminal, the edges between it and its children all haveweightsLmax. Let p(u) denote the parent node of nodeu, andl(e)(or l(u, v)) be the antenna charge weight of the edgee = (u, v) inthe routing tree.

For a leaf nodeu, if l(u, p(u)) ≤ Lmax or u is not a gate terminal,then u satisfies the antenna rule and thus it does not need to insertany cutting nodes. However, ifl(u, p(u)) > Lmax and u is a gate,then l(u, c) = Lmax gives the best position for inserting the cuttingnodec, as illustrated in Figure 19. After adding jumperc, the edgee(u, c) is cut from the tree.

For a sub-leaf node up and its childrenui, ∀1 ≤ i ≤ k, lettotal len =

∑k

i=1l(ui, up). There are two cases:

Case 1:total len ≤ Lmax

If (total len + l(up, p(up)) > Lmax, the cutting nodec withl(c, up) + total len = Lmax gives the best position, as shown in

Lmax

Fig. 19. Optimal jumper insertion for a leaf node. The cutting nodec is theoptimal one among the nodes on edgee(u, p(u)).

Figure 20(a). After addingc, all up’s children from the original treeare cut from the tree.

Case 2:total len > Lmax

First sort l(up, ui)∀1 ≤ i ≤ k in non-decreasing order and find themaximum s such that

∑s

i=1l(up, ui) ≤ Lmax. Then add the cutting

nodescs+1, . . . , ck as shown in Figure 20(b).

u3�

up

u2u1 �, ukus+2,us+1us

cs+1, cs+2, �, ck

(b)

(a)

Fig. 20. (a) Optimal jumper insertion for a sub-leaf node and (b) Illustrationfor the case oftotal len > Lmax.

Page 8: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

B. Redundant-Via Aware RoutingIn the nanometer technology, via-open defects are one of important

failures. A via may fail due to various reasons such as random defects,electromigration, cut misalignment, and/or thermal stress inducedvoiding effects. The failure significantly reduces the manufacturingyield and chip performance. To improve via reliability and yield,redundant-via insertionis a highly recommended technique proposedby foundries. If a via fails, a redundant via can serve as a fault-tolerantsubstitute for the failing one. As shown in Figure 21, a redundant viacan be inserted adjacently to each via to form a double-via pair.Double vias typically lead to 10–100 smaller failure rates than singlevias.

metal 1

metal 2

via

redundant via

Fig. 21. Double-via insertion. Each via is paired with a redundant via toform a double-via pair.

Below give some terminologies about vias. For a via, a redundant-via candidate is its adjacent position where a redundant via canbe inserted. For the example shown in Figure 22, viav1 hasone redundant-via candidate on its left side, and viav3 has threecandidates around it. According to the number of redundant-viacandidates, vias can be classified asdead, alive, or critical vias. Ifa via has at least one redundant-via candidate, it is an alive via;otherwise it is called a dead via. Note that if an alive via has exactlyone redundant-via candidate, it is also called a critical via. As shownin Figure 22, both vias v1 andv3 are alive vias,v2 is a dead via,andv1 is also a critical via.

critical via

dead viaalive vias

metal 1

metal 2

via

redundant-via candidate

v1

v2

v3

Fig. 22. Illustration of redundant-via candidates, dead vias, alive vias,and critical vias. Viasv1, v2, and v3 have one, zero, three redundant-viacandidates, respectively. Bothv1 andv3 are alive vias,v2 is a dead via, andv1 is also called a critical via.

Traditionally, redundant-via insertion is performed at the post-layout stage, which can be formulated as amaximum independent set(MIS) problem [27] or0-1 integer linear programming(ILP) [28], ormaximum bipartite matching[29], [30]. However, it is reported thatif the router can minimize the number of dead and critical vias, thepost-layout double-via insertion rate can be significantly improved.The reason is that the dead vias cannot be paired with redundant vias,and critical vias may not be paired due to the competition with othervias. For a routing instance from the sourceS to the targetT shown inFigure 23(a), an inferior routing path as shown in Figure 23(b) wouldmake viav a dead via and cannot be paired with any redundant vias.

In contrast, for the better routing result as shown in Figure 23(c), viav still remains alive for double-via insertion. Therefore, it is desirableto consider the redundant-via insertion at the routing stage to facilitateand preserve more flexibility for the post-layout double via insertion,as pointed out by [31].

(a) (b) (c)

S

T

S

T

S

T

dead via alive via

v

Fig. 23. Redundant-via aware routing benefits the post-layout double-viainsertion: (a) A detailed-routing instance for a 2-pin connection from thesourceS to the targetT , (b) If an inferior routing path is selected, viavwould become a dead via and cannot be paired, and (c) For a better routingpath, viav would remain alive for double-via insertion.

Chen et al. developed a redundant-via aware detailed-routingalgorithm [30]. For each redundant-via candidateri of a via v, theredundant-via cost ofri, cost(ri), is set as

cost(ri) =1

DoFv

,

where DoFv stands for thedegree of freedomof v and equalsthe number of redundant-via candidates ofv. The redundant-viapenalty for a connection pathp is calculated as the summation ofthe redundant-via costs of these redundant-via candidates onp.

Figure 24 illustrates the routing algorithm. Figure 24(a) shows adetailed-routing instance connected from the sourceS to the targetT . The redundant-via costs of redundant-via candidates are shown inFigure 24(b). The router can find a better routing path by choosingone with smaller redundant-via penalty, as shown in Figure 24(c).Finally, the routing solution would be more redundant-via friendly asshown in Figure 24(d), which contains more alive vias and preservesmore redundant-via candidates to benefit the post-layout redundant-via insertion.

V. CONCLUSIONS

Routing is one of the most fundamental steps in the physical designflow and is typically a very complex optimization problem. In thisarticle, we have addressed routing for some important nanometereffects, including manufacturability and reliability. As the technologynodes keep shrinking, all these effects should be considered in theearlier design stages. Considering the trade-off between optimizationflexibility and layout-information availability, routing appears to bethe best stage to handle these effects. It would be necessary to developnew data structures, algorithms, frameworks, and/or methodology forthe next-generation routers to handle the severe challenges yet tocome.

REFERENCES

[1] T.-C. Chen and Y.-W. Chang, “Multilevel full-chip gridless routingwith applications to optical proximity correction,”IEEE Trans. onComputer-Aided Design, 26(6), pp. 1041–1053, June 2007.

[2] T.-C. Chen, G.-W. Liao, and Y.-W. Chang, “Predictive formulaefor OPC with applications to lithography-friendly routing,” Proc.ACM/IEEE Design Automation Conf., pp. 510–515, June 2008.

[3] L.-D. Huang and M. D. F. Wong, “Optical proximity correction (OPC)-friendly maze routing,”Proc. ACM/IEEE Design Automation Conf., pp.186–191, June 2004.

Page 9: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

(a) (b)

S

T

S

T

1/3

1/3

1/3

1/4

1/4

1/4

1/4

1/2

1/2

S

T

1/3

1/3

1/3

1/4

1/4

1/4

1/4

1/2

1/2

S

T

penalty = 5/6

penalty = 1/4

(c) (d)

Fig. 24. Redundant-via aware detailed routing: (a) A detailed-routing instanceconnected from the sourceS to the targetT , (b) The redundant-via costs ofredundant-via candidates, (c) The router can find a better routing path withsmaller redundant-via penalty, and (d) The routing solutionwould be moreredundant-via friendly by preserving more redundant-via candidates.

[4] Y.-R. Wu, M.-C. Tsai, and T.-C. Wang, “Maze routing with OPCconsideration,”Proc. ACM/IEEE Asia and South Pacific Design Au-tomation Conf., pp. 198–203, January 2005.

[5] J. Mitra, P. Yu, and D. Z. Pan, “RADAR: RET-aware detailedroutingusing fast lithography simulations,”Proc. ACM/IEEE Design Automa-tion Conf., pages 369–372, Anaheim, CA, June 2005.

[6] M. Cho, K. Yuan, Y. Ban, D. Z. Pan, “ELIAD: Efficient LithographyAware Detailed Router with Compact Printability Prediction,” Proc.ACM/IEEE Design Automation Conf., pages 504–509, Anaheim, CA,June 2008.

[7] J. Luo, Q. Su, C. Chiang, and J. Kawa, “A layout dependent full-chipcopper electroplating topography model,”Proc. IEEE/ACM Int. Conf.on Computer-Aided Design, pp. 133–140, November 2005.

[8] R. Tian, D. F. Wong, and R. Boone, “Model-based dummy featureplacement for oxide chemical-mechanical polishing manufacturability,”Proc. ACM/IEEE Design Automation Conf., pp. 667–670, June 2000.

[9] D. White and B. Moore, “An ’intelligent’ approach to dummy fill,” EETimes, January 3, 2005.

[10] M. Cho, D. Z. Pan, H. Xiang, and R. Puri, “Wire density driven globalrouting for CMP variation and timing,”Proc. IEEE/ACM Int. Conf. onComputer-Aided Design, pp. 487–492, November 2006.

[11] H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, “Novel wiredensity driven full-chip routing for CMP variation control,” Proc.IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 831–838, No-vember 2007.

[12] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E Chen, “Mul-tilevel full-chip routing with testability and yield enhancement,”IEEETrans. on Computer-Aided Design, 26(9), pp. 1625–1636, September2007.

[13] C. Hammerschmidt, “IMEC sees double patterning as next step towards32nm,” EE Times Europe, July 16, 2007.

[14] D. Lammers, “Self-aligned double patterning coming,”SemiconductorInternational, July 17, 2008.

[15] J. Park, S. Hsua, D. Van Den Broekea, J. F. Chena, M. Dusab,R. Sochab, J. Findersc, B. Vleemingc, A. van Oostenc, P. Nikolskyc,V. Wiauxd, E. Hendrickxd, J. Bekaertd, and G. Vandenberghed, “Ap-plication challenges with double patterning technology (DPT) beyond

45 nm,” inProc. of SPIE Conf. on Photomask Technology, pp. 634922-1–634922-12, 2006.

[16] W. Arnold, M. Dusa, and J. Finders, “Manufacturing challenges indouble patterning lithography,” inProc. of IEEE Int. Symp. on Semi-conductor Manufacturing, pp. 283–286, September 2006.

[17] A. B. Kahng, S. Vaya, and A. Zelikovsky, “New graph bipartizations fordouble-exposure, bright field alternating phase-shift masklayout,” inProc. of ACM/IEEE Asia and South Pacific Design Automation Conf.,pp. 133–138, January 2001.

[18] Y. Pan, H. Zhang, and Y. Chen, “A new OPC method for double pattern-ing technology,” inProc. of SPIE Conf. on Optical MicrolithographyXXI, pp. 692422-1–692422-10, 2008.

[19] A. B. Kahng, C.-H. Park, X. Xu, and H. Yao, “Layout Decompositionfor Double Patterning Lithography,” inProc. of IEEE/ACM Int. Conf.on Computer-Aided Design, pp. 465–472, November 2008.

[20] T.-B. Chiou, R. Socha, H. Chen, L. Chen, S. Hsu, P. Nikolsky,A. van Oosten, and A. C. Chen, “Development of layout split algo-rithms and printability evaluation for double patterning technology,” inProc. of SPIE Conf. on Optical Microlithography XXI, pp. 69243M-1–69243M-10, 2008.

[21] M. Cho, Y. Ban, and D. Z. Pan, “Double patterning technology friendlydetailed routing,” inProc. of IEEE/ACM Int. Conf. on Computer-AidedDesign, pp. 506–511, November 2008.

[22] P. H. Chen, S. Malkani, C.-M. Peng, and J. Lin, “Fixing antennaproblem by dynamic diode dropping and jumper insertion,”Proc. IEEEInt. Symp. on Quality Electronic Design, pp. 275–282, March 2000.

[23] T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing withantenna avoidance,”Proc. ACM Int. Symp. on Physical Design, pp.34–40, April 2004.

[24] D. Wu, J. Hu, and R. Mahapatra, “Coupling aware timing optimizationand antenna avoidance in layer assignment,”Proc. ACM. Int. Symp. onPhysical Design, pp. 20–27, April 2005.

[25] T.-Y. Ho, Y.-W. Chang, and S.-J. Chen,Full-Chip Nanometer RoutingTechniques, Springer, Dordrecht, The Netherlands, 2007.

[26] B.-Y. Su and Y.-W. Chang, and J. Hu, “An optimal jumper insertionalgorithm for antenna avoidance/fixing,”IEEE Trans. on Computer-Aided Design, 26(10), pp. 1818–1929, October 2007.

[27] K.-Y. Lee and T.-C. Wang, “Post-routing redundant via insertion foryield/reliability improvement,”Proc. ACM/IEEE Asia and South PacificDesign Automation Conf., pp. 303–308, January 2006.

[28] K.-Y. Lee, C.-K. Koh, T.-C. Wang, and K.-Y. Chao, “Optimal post-routing redundant via insertion,”Proc. ACM Int. Symp. on PhysicalDesign, pp. 111–117, April 2008.

[29] H. Yao, Y. Cai, X. Hong, and Q. Zhou, “Improved multilevel routingwith redundant via placement for yield and reliability,”Proc. ACMGreat Lakes Symp. on VLSI, pp. 143–146, April 2005.

[30] H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han,“Full-chip routing considering double-via insertion,”IEEE Trans. onComputer-Aided Design, 27(5), pp. 844–857, May 2008.

[31] G. Xu, L.-D. Huang, D. Z. Pan, and M. D. Wong, “Redundant-viaenhanced maze routing for yield improvement,”Proc. ACM/IEEE Asiaand South Pacific Design Automation Conf., pp. 1148–1151, January2005.

Page 10: Routing for Manufacturability and Reliabilitycc.ee.ntu.edu.tw/~ywchang/Courses/PD_Source/IEEE_DFM2009.pdf · Routing for Manufacturability and Reliability Huang-Yu Chen1, Yao-Wen

Huang-Yu Chen is working toward the Ph.D. de-gree in Graduate Institute of Electronics Engineeringat the National Taiwan University, Taipei, Taiwan.He received his B.S. in electrical engineering fromNational Tsing Hua University, Hsinchu, Taiwan, in2004. His research interests are in combinatorial op-timization with applications to the VLSI design au-tomation, manufacturability-driven large-scale rout-ing, and design for manufacturability/reliability. Hehas four papers published in the first-tier confer-ences (DAC’06, ICCAD’07, ICCAD’08, and ASP-

DAC’09), two papers in the topmost journal (TCAD’07, TCAD’09), and twobook chapters published since 2006.

He has received the Outstanding Research Award from National TaiwanUniversity in 2006 and the Best Paper Nomination from ICCAD-2007. Theacademic global router developed by his team, NTUgr, got the2nd placein 2008 ACM ISPD global routing contest among 11 teams from U.S.A.,Europe, and Asia. He also received a Best Paper Award at the 2008 VLSIDesign/CAD Symposium.

Yao-Wen Chang received the B.S. degree in Com-puter Science and Information Engineering fromNational Taiwan University in 1988, and the M.S.and Ph.D. degrees in Computer Science from theUniversity of Texas at Austin in 1993 and 1996, re-spectively. Currently, he is Professor of the GraduateInstitute of Electronics Engineering, the Graduate In-stitute of Electrical Engineering, and the Departmentof Electrical Engineering, National Taiwan Univer-sity, Taipei, Taiwan. His current research interest liesin electronic design automation, with an emphasis on

physical design for nanometer IC’s and design for manufacturability.Dr. Chang received four excellent teaching awards, a Best Paper Award at

the 2007 VLSI Design/CAD Symposium, an award at the 2006 ACM/IEEEISPD International Placement Contest, a Best Paper Award at ICCD-95, andnine Best Paper nominations from DAC-07, ISPD-07 (two papers), DAC-05,ASP-DAC-04, 2003 ACM Transactions on Design Automation of ElectronicSystems , ICCAD-02, ICCD-01 , and DAC-2K. Dr. Chang is an editor of theinternational Journal of Information Science and Engineering. He currentlyserves on the ACM SIGDA Physical Design Technical Committee and hasserved on the technical program committees of ACM/IEEE DAC, IEEE/ACMICCAD, ACM ISPD, IEEE/ACM ASP-DAC (topic chair), IEEE/ACM DATE,IEEE ICCD, ACM GLSVLSI, IEEE-TSA VLSI-DAT (topic chair), IEEESOCC (topic chair), IEEE FPT (program co-chair), IEEE IECON(topic chair),IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), and IEEETENCON. He is currently an independent board director of Genesys Logic,Inc., the Chair of the EDA Consortium of the Ministry of Education, Taiwan, amember of the Board Governors of the Taiwan IC Design Society, aReviewCommittee Member of the National Science Council and the Ministry ofEconomics Affairs, Taiwan.