rf-system-on-package (sop) for wireless...

RF-System-On-Package (SOP) for Wireless Communications

� Kyutae Lim, Stephane Pinel, Mekita Davis, Albert Sutono, Chang-Ho Lee, Deukhyoun Heo,Ade Obatoynbo, Joy Laskar, Emmanouil M. Tantzeris, Rao Tummala

Anew industrial revolution, often called the “thirdwave” or information technology (IT), is in the mak-ing. The products of this revolution will require en-

tirely different systems hardware technologies: those withmultifunctions, such as digital, analog, RF, and opticalcircuitries. RF and microwave design and packaging havebeen established as key technologies of this revolution. Thedemand for increasingly higher rates of data, voice, andvideo drives RF technology to ever higher frequencies wherebandwidth for channel capacity is easy to find. Such emerg-ing high-performance applications as personal communica-tion networks, wireless local-area networks (WLAN), andRF-optical networks have defined a trend toward more flexi-ble and reconfigurable systems. They impose very stringentspecifications never before reached in term of low noise,high linearity, low power consumption, small size andweight, and low cost.

The RF front-end module is the foundation of these systems,and its integration poses a great challenge. Microelectronicstechnology, since the invention of the transistor, has revolution-ized many aspects of electronic products. This integration andcost path has led the microelectronics industry to believe thatthis kind of progress can go on forever, leading to so-called “sys-tem-on-chip” (SOC) for all applications. But it is becoming clearthat the production of a complete solution for the new wirelesscommunication front-end is still a dream. When you considerthe characteristics of an RF front-end module

• high performance up to 100-GHz operating frequency• a large number of high-performance discrete passive

components• design flexibility• reconfigurable architecture• low power consumption• compactness• product customization• short time to market and low cost

the system-on-package approach (SOP) has emerged as themost effective to provide a realistic integration solution be-cause it is based on multilayer technology using low-cost andhigh-performance materials [1], [2]. Multilayer topologyhigh-density hybrid interconnect schemes, as well as variouscompact passive structures, including inductors, capacitors,and filters, can be directly integrated into the substrate. Thus,

a high-performance module can be implemented while si-multaneously achieving cost and size reduction.

This article illustrates the performance of the next-genera-tion SOP integrated module, including

• the features of the SOP concept for RF front-end moduleintegration

• development efforts on the embedded passive libraryand 3D modules for wireless applications

• high-performance, organic-based, multichip-module (MCM)technology.

What Is RF-SOP?In the future, wireless communication will require betterperformance, lower cost, and smaller RF front-end size. Tomeet critical specifications, it is common to use discrete pas-sive components, such as surface acoustic wave (SAW) fil-ters and packaged inductors. Although much effort has beendevoted to the realization of SOC in RF areas using Si basedtechnology, SOC is considered a solution for limited applica-tions, such as Bluetooth. The recent development of materi-als and processes in packaging makes it possible to bring theconcept of SOP into the RF world to meet the stringent needsof wireless communication. RF-SOP is “to provide a com-plete packaging solution for RF module by integrating em-bedded passives components and MMIC at the packagelevel” [3], [4].

To explain the concept, a general system configuration ofa wireless transceiver is shown in Figure 1. The module iscomposed of a monolithic microwave integrated circuit(MMIC) chipset [power amplifier (PA), low-noise amplifier(LNA), up-and-down mixer (MIX), and voltage-controlledoscillator (VCO)] and passive components (filter, antenna,and external high-Q discrete passive elements for blockswith stringent requirements, such as PA and VCO). TheRF-SOP approach includes

• the replacement of the discrete passives with embed-ded ones

• the addition of more functional blocks, such as an an-tenna, to the module

• the optimization of the performance of the MMICchipset by replacing on-chip passives with high-Qpassives embedded in the package.

Figure 2 is a roadmap for the RF-SOP approach. It is im-portant to note that choice of the on-chip or off-chip(on-package) passives is dependant on the frequency band,modulation scheme, available device, and packaging tech-nology. For example, the linearity and efficiency of PA willdetermine the choice of an on-chip/off-chip matching cir-cuit. In VCO, the need of a high-Q inductor on package is de-

88 March 2002IEEE magazine

K. Lim, S. Pinel, M. Davis, J. Laskar, E.M. Tantzeris, and R.Tummala are with Georgia Institute of Technology, Atlanta, Geor-gia. A. Sutono and C.-H. Lee are with RF Solutions, Atlanta, Geor-gia, USA. D. Heo is with National Semi Conductor, Inc., Norcross,Georgia. A. Obatoynbo is with HRL, Malibu, California, USA.

termined by the phase noise specification that is comingfrom a modulation scheme

The advantages of RF-SOP are• lower cost by using embedded passive instead of dis-

crete components• design flexibility for MMIC designers by using high-Q

passives embedded in the package• minimized loss and parasitic effects by reducing the

number of interconnections• reduced module size by adopting multilayer packaging• ease of realization of multifunctional RF modules in a

single package• better high-power handling capability than MMIC chip.However, there are still some of problems to be overcome,

such as• interference between each of the blocks in a package• too many degrees of freedom in multilayer packaging to

build a design library• size constraints, if an antenna is included in the package.

Embedded Passive DevelopmentsMulitlayer Inductor LibraryAn inductor library for the low-temperature co-fired ceramic(LTCC) packaging process was built based on the multilevelsignal line and ground plane concept in Figure 3 [5]. Figure 4shows three different inductor topologies in microstrip con-figuration that can be implemented in multilayer board tech-nology. The conventional planar spiral inductor is fabricatedon a single layer. Increasing inductance is obtained by increas-ing the number of turns laterally. As the area increases pro-portionally to the number of turns, RS, CS, and LS increasewhile RP decreases. Therefore, this topology is expected tohave both low Q and self-resonance frequency (SRF). The“offset” 3D style, shown in Figure 4(b), offsets the bottom turnso that the upper and lower turns do not overlap each other.While this design has a better SRF due to a slight reduction ofCC, by avoiding the winding overlap, it requires a longer lineand, therefore, larger area to get an equivalent inductance tothat obtained by the conventional 3D inductor. Figure 4(c)shows a helical configuration which is an evolution of theconventional 3D structure where only half of the turn is fabri-cated on each layer thereby increasing the gap between twooverlapping layers. This architecture occupies the same realestate as conventional 3D structures with reduced CC due toincreasing the gap between the inductor windings and, there-fore, improves the SRF.

An 8.2-nH inductor with 10-mil line width using the pla-nar spiral, offset 3D, and helical configurations has been de-signed, fabricated, and measured. The performance of thesethree inductors was assessed in terms of Q, SRF, and area.Figure 5 shows that all inductors have a nominal effective in-ductance of approximately 8.2 nH. We demonstrated that thenovel helical type has a three times better Q and twice higherSRF than the planar spiral design while occupying signifi-cantly less lateral area compared to the other two types (Fig-ure 6). The performance summary of the three 8.2-nHinductors (Table 1) indicates that the novel helical inductor is

not only superior in terms of Q and SRF, but also occupiesarea an order of magnitude smaller than that occupied by theplanar spiral inductor.

Mulitlayer CapacitorsConventional metal-insulator-metal (MIM) capacitors inmicrostrip configuration are incorporated for the capacitor li-brary [6]. A capacitance of 0.48fF/mil2 can be achieved usingstandard 3.6-mil-thick tapes. A 4.9-pF MIM, for example, canbe realized by 100 × 100 mil square electrodes neglecting thefringing fields. For large capacitors such as the RF ground ca-pacitors, however, the electrode size becomes impractical.

March 2002 89IEEE magazine

AntennaRF Front-End

Up-Mixer

VCODuplexer

LNA Filter

Down-Mixer

IF

MO

DE

M

Filter PA

Figure 1. RF transceiver architecture.

MMIC

Package

LNA

Mixer

VCO

PA

Antenna Filter

Balun

Driver AmpDuplexer

Switch

Power Combiner

High-Q L/C

Figure 2. RF-SOP road map.

h1

Gound Plane

(a) (b)

L L

h2

GroundPlane

Cs1

Cs2

Figure 3. An illustration of multilevel signal lines and groundplane inductors.

Therefore, there is a need for a new configuration to maintainthe compactness of the capacitor structures. The lateral elec-trode interdigitation method has been applied to implement acapacitor as well. While exhibiting less parasitics, this topol-ogy tends to require a bigger area, considering that the electricflux is generated laterally instead of vertically, such as in theMIM case, which allows more electrode coverage and, thus,occupies less area.

An alternative capacitor implementation to the MIM to-pology was proposed using the vertically interdigitated con-figuration (VIC). Figure 7(b) illustrates the concept of theVIC as compared to the conventional MIM structure shownin Figure 7(a). The MIM structure, consisting of a dielectriclayer sandwiched between two square plates of width s inFigure 7(a), neglecting the higher order excitation mode.

This capacitor can also be implemented by a par-allel combination of pairs of plates of smallersize. The VIC deploys these smaller plates withwidth s’ vertically. The plate size can be madesmaller as more plates are deployed on a largernumber of dielectric layers. The electric flux notonly flows vertically between the pair of the ca-pacitor electrodes, but also laterally between thevia interconnects to the electrode. Such a mecha-nism allows further shrinkage of the VIC plates.VIC topology occupies nearly an order of magni-tude less area than the MIM, while maintainingcomparable performance.

Mulitlayer FilterAn on-package integrated multilayer filter of-fers a more attractive implementation thanon-chip and discrete filters. An RF image-rejectfilter was implemented with six layers of LTCCin a stripline configuration, whose 3D view is il-lustrated in Figure 8. Layers 6 and 0 are the topand bottom metalizations which serve as the

top and bottom ground planes. The two shunt inductors, L1

and L2, were realized by the U-shaped strips fabricated onlayers 4 and 3, which are located two and three layers un-derneath the top ground plane, respectively. The end of thestrips are connected to both grounds through vias. There isno metalization between layer 4 and 6, therefore, the top in-ductor strip on layer 4 is 7.2 mil (two layers) away from thetop ground plane, while the bottom strip is 10.8 mil (threelayers) away from the bottom ground plane. The requiredmutual inductive coupling is achieved by overlapping theL1 and L2 strips, which are one layer (3.6 mil) apart. MIM ca-pacitors with electrodes on layers 4 and 3, laid out besidethe inductor strips, were utilized to implement CI and CO.The VIC topology was utilized to implement CS, which is re-alized by two series capacitors of capacitance 2 CS. Each of


(a) (b) (c)

Top View

S

Ground Plane

d

h

Cross-Sectional View

W

Figure 4. (a) Top and cross-sectional view of a planar spiral, (b) offset 3D,and (c) helical inductors.

0

5

10

15

20

0 0.5 1 1.5 2 2.5

Helical (3D)Offset-Turn (3D)Planar Spiral

Frequency, GHz

L, n

Hef

f

Figure 5. Measured effective inductance of the planar and 3Dinductors.

0

20

40

60

80

100

0 1 2 3 4 5

Q

Frequency, GHz

Helical (3D)Offset-Turn (3D)Planar Spiral

Figure 6. Measured Q of the planar and 3D inductors.

these capacitors is implemented in VICtopology as a parallel combination oftwo capacitors with a value of CS. Suchimplementation ensures the symmetryof the structure desirable for high fre-quency circuits. If CS were implementedin MIM topology, the entire structurewould not have been symmetrical. Thebottom plates of CI and CO are used asthe top plates of the VIC extended tolayer 2 through via connections. Thedumbbell-shaped trace is inserted onlayer 2 between layer 3 and 1 as the bot-tom plates of the VIC. The extended topplates of the VIC on layer 1 are used asthe top MIM electrodes for the shunt ca-pacitor CR with the bottom ground onlayer 0 as the bottom electrode. The fil-ter prototype is given in the photographin Figure 9. Figure 10 gives the mea-sured insertion loss of 3 dB at 2.4 GHzwith 40-dB rejection at 2 GHz.

Integrated AntennaOne of the major issues in developingRF-SOP is integrating an antenna with amodule efficiently. Fabricating an an-tenna directly on the package has the advantage of reducingfeeder loss and size of an entire module. However, for the fre-quency range from 1-6 GHz, which is being used for mostwireless mobile and data communication, it is difficult tobring an antenna into the transceiver module since the size ofthe antenna becomes large. Also, the interference between theantenna and other RF components in a highly compact mod-ule is another main hinderance of this approach.

In compact modules, a cavity-backed patch antenna(CBPA) has been successfully adopted to LTCC packaging(Figure 11) [7]. The antenna is designed to be connected withthe embedded RF blocks, such as filter or duplexer switches.The cavity structure is formed by surrounding multiple viasconnected to the ground plane. The radiator (patch) is madeon the top surface and is connected with the embedded filterthrough a via. The location of the via feed is designed to getimpedance matching with an embedded filter. A CBPA needsa smaller ground plane since most of energy is confined be-tween the edge of the patch and via wall. Obviously, thickersubstrate increases the bandwidth of the antenna, but thethickness should be determined moderately by consideringthe entire module structure.

The measured return loss of the CBPA designed for 5.8GHz is shown in Figure 12. For comparison, a microstrippatch antenna has been developed for the same frequency.The result shows that bandwidth of a CBPA is 20% largerthan the patch.

Multilayer BalunBaluns are required in a wide variety of microwave compo-nents, such as balanced mixers, push-pull amplifiers, multi-pliers, and phase shifters. They have become important RFcomponents for improving performance and reducing thecost of the RF module by being embedded inside the package.

Figure 13 shows the stripline type multilayer Balun de-signed for LTCC. Two shorted lines are placed next to an openline such that they couple energy from the open line as shown.Layers 0 and 4 represent the ground planes of the structure.


Table 1. Summary of the three different types of multilayer inductors.

Types# ofturns

D(mil)

Q maxSRF(GHz)

Leff(nH)

Area(mil mil)

a) Planar spiral 3 - 27 at 0.8 GHz 1.5 8.2 90 × 107

b) Modified 3D 2 7.2 46 at 1.1 GHz 2.3 8.2 74 × 75

c) Helical 2 3.6 88 at 1.3 GHz 3.2 8.2 42 × 37

Port 1

Port 1

Port 2

Port 2s

(a) Parallel Plate Capacitor (b) Vertically Interdigitated Capacitor

Via

s′

d

Figure 7. Three-dimensional views of MIM and VIC configurations.

Port 1

A

Layer 5

Layer 4

Layer 3

Layer 2

Layer 1

Layer 0

A

Port 2

Figure 8. A 3D layer-by-layer view of multilayer filter structure.

The half wavelength open line is on layer 2. A small portion ofthis line is on layer 3 to avoid overlapping traces and to achievethe spiral space saving configuration described previously.One of the quarter wavelength coupling sections is on layer 1and the other on layer 3. Each of these lines is shorted to theground planes (through vias) above and below it, respectively.

There is very good agreement between the measurementand simulation, as can be seen from the results (Figure 14).An insertion loss of 3.4 dB was measured, while a measuredbandwidth of 41% was calculated compared with 69% forthe simulation.

Integrated RF-SOP ModulesKu-Band Transmitter ModuleThe implementation of a compact transmitter module is thekey issue for higher data rates and broadband transmission,such as applications of satellite communication systems in theKu/Ka-band range. One obstacle for a compact transceivermodule is the large and heavy cavity filter that cannot be eas-ily integrated into the module.

A highly integrated LTCC based transmitter module usingGaAs metal-semiconductor field-effect transistor (MESFET)

MMICs for Ku-band satellite communication applications ispresented [8]. Figure 15 shows the 3D-configuration and pic-ture of the module. The upconverter MMIC integrated with aVCO exhibits a measured upconversion gain of 15 dB and anIIP3 of 15 dBm, while the power amplifier (PA) MMIC showsa measured gain of 31 dB and a 1-dB compression outputpower of 26 dBm at 14 GHz. Both MMICs were integrated ona compact LTCC module where an integrated front-end bandpass filter (BPF) with a measured insertion loss of 1.8 dB at14.5 GHz was integrated. The bandpass filter for the transmit-ter module was implemented in a coupled line filter topologyon a multilayer LTCC substrate. The two stripline groundplanes are physically connected by vias, and the actual inputand output of the filter are connected to the RF amplifier anddriver amplifier of the transmitter. Three segment folded edgecoupled strip-line filters, where the middle segment was de-ployed perpendicular to the first and third segments for com-pactness, have been designed to suppress the local oscillator(LO) signal at 13 GHz as well as the harmonics and spurioussignals. This is a balanced stripline topology where the cou-pled-line segments are sandwiched by two ground planes atan equal distance of 17.6 mil (four LTCC tape layers).


Figure 9. Photograph of the fabricated filter.

−50

−40

−30

−20

−10

0

1 1.5 2 2.5 3 3.5 4 4.5 5

MeasurementMoM Simulation

Frequency, GHz

S, d

B21

Figure 10. Measured and simulated magnitude of S11 and S21 forthe filter.

Ground Wall

Feeding PointRadiator

Feed Via

Ground Via Via To Duplexer/Filter

LTCC

Ground Plane

Figure 11. Configuration of CBPA.

−20

−15

−10

−5

0

5 5.5 6 6.5 7Frequency (GHz)

S11(db_sim)S11(db_meas)

S11

(dB

)

Figure 12. Measured and simulated return loss of the CBPA de-signed for 5.8 GHz.

The entire transmitter chain exhibits a total gain of 41 dBand output power of 26 dBm incorporating the wirebondloss from 14-15 GHz and image rejection of more than 30dBc at 12 GHz [Figure 16(a)]. Figure16(b) shows the overall system level di-agram of the entire transmitter chainbased on the measurement of eachtransmitter block. The compact mod-ule was made possible by embeddingthe filter, thereby saving more than40% of real estate compared to themodule if it were implemented on atypical alumina substrate.

3D-Integrated Modulefor C-BandThe integration of the antenna and theRF front end in a compact module isquite attractive and challenging. Sev-eral works on modules in which the an-tenna has been integrated have beenpresented for mm-wave wireless applications [9]. Thesetechniques are difficult to adopt in C-band due to the largerrelative size of the antenna at the frequency of interest. A 3Dintegrated transceiver module with an antenna for 5.8 GHzis presented here [10]. The structure of the integrated mod-ule is shown in Figure 17. Three different layers for the trans-ceiver, filter, and antenna, are vertically stacked andconnected through vertical vias. The antenna and filter aredirectly fabricated on the module using LTCC technology inorder to reduce size and interconnection losses.

The module has been designed for 20 LTCC layers. Beforedesigning each of the embedded passives, the layers are prop-erly assigned. The antenna, filter, and transceiver utilize 8, 10,and 2 layers, respectively. The total size of the module is 14 ×19 × 2 mm3, including all the RF functional blocks. Thegrounds are connected efficiently to suppress the unwantedparasitic modes. A photograph of the integrated module isshown in Figure 18.

To utilize the module space effectively, the type of passivecomponents should be chosen very carefully. A CBPA hasbeen designed for the module. A three-section coupledstripline filter has been designed to be embedded inside of theLTCC package. The input and output ports of the filter areconnected to the antenna and the duplexer switch throughvias. RF functional blocks, including PA, LNA, mixers, andVCO, are attached on the top of the LTCC board. The specifi-cations of the functional blocks have been determined andverified through system simulations based on IEEE 802.11a.To evaluate the performance of the module, each of the sec-tions in the module have been fabricated. The results of thisevaluation are shown in Figure 19.

Integrated Power Amplifier ModuleA two-stage 1.9-GHz power amplifier with second-harmonictuning circuits using silicon N-MOSFETs has been built utiliz-ing the LTCC package [11]. Figure 20 shows the schematic dia-

gram and photograph of the LTCC power amplifier. A single-ended two-stage common source amplifier is implementedwith an integrated reactive matching network using


Port 2Port 1

Port 3Layer 0

Layer 1

Layer 2

Layer 3

Layer 4

Figure 13. Photo and configuration of the stripline multilayer balun.

−25

−20

−15

−10

−5

0

3 4 5 6 7 8

dbS11_2_measdbS11_sim

−20

−15

−10

−5

0

3 4 5 6 7 8

dbS21_measdbS21_sim

S11

(dB

)S

11(d

B)

Frequency (GHz)

Frequency (GHz)

Figure 14. Measured and simulated results of the stripline balundesgined for 5.8 GHz.


4.4 mils

B=4 Layers (17.5 mils)

IF

Up-ConverterMMIC PA MMICRF

DCPA Output

Driver Input

Figure 15. Configuration and picture of compact Ku-band transceiver module.

−40

−30

−20

−10

0

10

20

30

11 12 13 14 15 16 17 18

Gai

n (d

B)

Frequency (GHz)

Overall System

w/o Filter

IF Amp Mixer RF Amp Filter Driver PA

25

20

15

10

5

0

−5

−10

−15

2 dB

P-1 dBP-1 dB

P-1 dB

P-1 dB

P-1 dB

10 dB

5 dB -3 dB

26 dB

5 dB

PowerLevel

−20

40

FilterReturn Loss

FilterInsertion Loss

(a)

(b)

Figure 16. Measured gain of the module (a) overall system gainand (b) gain variation at each level.

MMIC RF Blocks(PA, LNA, Mixer, VCO, Duplexer)

Embedded Filterfor Image Rejection

Cavity Backed Patch Antennawith Via Feed

Figure 17. 3D integrated module with CBPA and embedded filter.

Figure 18. Photograph of the integrated module.

multilayer LTCC passives. For high-efficiency operation, eachstage of the PA was class AB biased (20% of Imax), incorporatingsecond-harmonic tuning circuits in the input and output ofeach stage. The two N-MOSFET devices fabricated in a con-ventional 0.8-µm BiCMOS technology were wirebonded ontogold pads on the LTCC board. Half- and quarter-turninductors were used as matching components while afull-turn inductor was used for an RF choke. Parallel- plate

MIM capacitors were utilized as matching components for thefundamental signal since their values and sizes are relativelysmall. The RF ground capacitors were implemented in thecompact VIC topology since they require large capacitancevalue for 1.9-GHz applications. Second-harmonic tuning ele-ments were implemented through a series inductive- capaci-tance (LC) resonator at 3.8 GHz as part of the second-harmonic trap network to improve the efficiency.

Figure 21 shows the measuredgain, power-added efficiency (PAE)and output power of the fabricatedCMOS-LTCC PA at 1.9 GHz. Thepower amplifier exhibits 48% PAE,26-dBm output power, and 17-dBpower gain at 1.9 GHz with a 3.3-Vdrain supply voltage.

To investigate the advantage of in-tegrating passives on-package, suchas on LTCC, another 1.9-GHz poweramplifier was built with the same to-pology as that with fully integratedLTCC passives. The two-stage CMOSpower amplifier integrated theinterstage matching componentson-chip, while the input and outputmatching elements, as well as the RFchoke and ground inductors and ca-pacitors, were integrated on LTCCusing the library components. Figure22 shows the circuit schematic and aphotograph of the LTCC board hous-ing the module. The fully monolithicon-chip version of this power ampli-fier using the same CMOS technol-ogy and the same schematic has alsobeen designed, fabricated, and mea-sured. Table 2 outlines the measuredperformance comparison of the1.9-GHz power amplifier, employingthree different passive integration ap-


–60

–50

–40

–30

–20

–10

0

10

–3

–2

–1

0

1

2

3

4

–60 –50 –40 –30 –20 –10 0 10

IF P

ower

(dB

m)

RF Power (dBm)(a)

–30

–27

–24

–21

–18

–15

–2

–1

0

1

2

3

5 5.2 5.4 5.6 5.8 6

IF P

ower

(dB

m)

RF Frequency (Ghz)(b)

Gai

n (d

B)

Gai

n (d

B)

Figure 19. Measured gain of the receiver versus (a) input level and (b) frequency.

C2

L0 C0

L1Input

L3

C1

M1

L6

C3

L2

Vgg1−−

++

C4−

−

+

+

Vdd1

L4L5

C5

C6 L7

C7

C9

C8

L9

L8

Vgg2

C10 Vdd2

L10C12

L11

C11

M2 L13

L12

Output

N-MOSFET 2.5 mm VIC Capacitor N-MOSFET 5 mm

MIM Capacitor Second Harmonic Tuning Cicuit 3D Inductor

(a)

(b)

Figure 20. Schematic diagram (a) and die photo (b) of the 1.9-GHz power amplifier modulewith fully on-package passives.

proaches: fully LTCC integrated, on-chip interstage inte-grated, and fully on-chip integrated techniques. These resultsclearly demonstrate the advantages of implementingon-package components where superior Q performance canbe achieved.

Multilayer Organic PackageA multilayer packaging process using a organic material, de-veloped by the Georgia Institute of Technology’s PackagingResearch Center, offers potential as the next generation tech-nology of choice for SOP for RF-wireless, high-speed digital,and RF-optical applications [12]. This approach set up thetechnological platform with the ability to integrate on thesame substrate digital, RF, and optical systems.

The current SOP configuration is shown in Figure 23. It in-corporates low-cost materials and processes consisting of acore substrate (FR-4 for example) laminated with two thin or-ganic layers. The thickness of the core substrate is 40 mil,while the thickness of the laminate layers are 2.46 mil each.

The integral passive components fabricated within thewiring structure of the SOP module, which consists of a threemetal layer structure, including two layers of high-densitywiring metallization and two micro via levels. For thismultilayer interconnection structure, 10-18-µm coppermetallization and 100-µm diameter micro vias process areused. The minimum metal linewidth and spacing is 1 mil for the toptwo metal layers.

Multilayer InductorsHigh Qs at the frequency range of in-terest can be obtained by designingmultilayer inductors and HGPinductors using multilayer organictechnology. The CPW spiral inductor(Figure 24) avoids via losses, has re-duced dielectric losses, and increasedSRF. Also, the thick copper metali-zation in the packaging process makeit possible to get a very high-Q. Thisdecreases the shunt parasitic capaci-tance and reduces the eddy currentflowing in the ground plane, produc-ing negative mutual inductance ef-fect. As a result, higher Q and Leff canbe achieved. The CPW inductor dem-onstrates a Q of 182, an SRF of20GHz, and a Leff of 1.97 nH, as shownin Figure 23.

Embedded FiltersSeveral embedded filters were de-signed for the process. The bandpassfilter design for C band applicationsconsists of a square patch resonatorwith inset feed lines (Figure 25). Theinset gaps act as small capacitors and

cause the filter to have a pseudo-elliptic response with trans-mission zeros on either side of the passband. This structurealso has a tunable bandwidth. The length of the insets and thedistance between them are the main controlling factors, effec-tively setting the size of the mode-splitting perturbation in the


30

25

20

15

10

5

0

−5

60

50

40

30

20

10

0−20 −15 −10 −5 0 5 10 15

P (dBm)in

P(d

Bm

), G

ain

(dB

)ou

t

PAE

(%

)

Gain

PoutPAE

Figure 21. Measured (dot) and simulated (solid) gain, PAE, andoutput power of the PA at 1.9 GHz.

IN

VG1

VD1VG2

VD2

OUT

On-Chip(a)

(b)

511 mils

472

mils

Figure 22. Schematic diagram (a) and die photo (b) of the 1.9 GHz power amplifier modulewith on-chip interstage matching and on-package in/output matching.

field of the resonator. The length of the feed lines is determinedby the input and output matching requirements. The measure-ment results show a bandwidth of 1.5 GHz and a minimum in-sertion loss of 3 dB at the center frequency of 5.8 GHz.

Other AttributesIn addition to the filter and inductor, many passives are be-ing developed for the organic process. A lifted slot antennahas been successfully implemented in the package. Also,CPW-microstrip transition using vias shows that it can be

used up to 20 GHz.

ConclusionWe have presented the SOP conceptapplied for RF front-end module in-tegration. The development of anLTCC-based component for wire-less RF-SOP applications has beendescribed. Various types of multi-layer embedded passive compo-nents including inductor, capacitor,filter, antenna, and balun suitablefor the highly integrated modulehave been presented. Developmentefforts on a 3D integrated module,which includes wireless transceiv-ers and power amplifier moduleshave been demonstrated, and then anovel 3D integration concept has

been described. Multilayer organic pack-aging developed for SOP was also re-ported. Very high Q-factor inductors (upto 180) and embedded filters have beenpresented as examples of the high perfor-mances of multilayer organic packages.

References[1] R.R. Tummala, Fundamentals of Microsystems Pack-

aging. New York: McGraw-Hill, 2001.

[2] J. Laskar, “System on package and system on chiptrade-offs,” presented at the IEEE Workshop onCircuits and Systems for Wireless Communicationsand Networking, South Bend, IN, Aug. 2001.

[3] J. Laskar, A. Sutono, C.-H. Lee, M.F. Davis, A.Obatoyinbo, K. Lim, and M. Tentzeris, “Develop-ment of integrated 3D radio front-end sys-tem-onp-ackage (SOP),” in Proc. IEEE GaAs ICSymp., Baltimore, MD, Oct. 2001, pp. 215-218.

[4] G. Carchon, K. Vaesen, S. Brebels, W. De Raedt, E.Beyne, B. Nauwelaers, “Multilayer thin-filmMCM-D for the integration of high-performance RFand microwave circuits,” IEEE Trans. Comp. Packag.Technol, vol. 24, pp.510-519, Sept. 2001.

[5] A. Sutono, D. Heo, E. Chen, K. Lim, and J. Laskar,“High Q LTCC-based passive library for wirelesssystem-on-package (SOP) module development,”IEEE Trans. Microwave Theory Tech., vol. 49, pp.1715-1724, Oct. 2001.

[6] A. Sutono, J. Laskar, and W.R. Smih, “ Developmentof integrated three dimensional Bluetooth image


Board Size = 4 x4Via Diameter = 4 milsVia Pad >= 2xVia Dia.Min. Line Width = 1mil

″″

Metal 3A

Metal 2A

Metal 1A

Vialux: r = 3.5, Loss tan = 0.015, Thickness = 2.46 milsε

Vialux: r = 3.5, Loss Tan = 0.015, Thickness = 2.46 milsε

FR4: = 3.9, Loss tan = 0.015, Thickness 40 milsεr

Figure 23. 3D integrated module with CBPA and embedded filter.

−50

0

50

100

150

200

0

10

20

30

40

50

0 5 10 15

Q

Frequency, GHz

L eff

Figure 24. Photo of CPW inductor and measurement result of Q and inductance.

−40

−35

−30

−25

−20

−15

−10

−5

0

12 13 14 15 16 17 18

S11

, S21

, dB

Frequency, GHz

Figure 25. Photo of bandpass filter for 5.8 GHz and measurement results.

Table 2. Comparison of three different approaches ofthe power amplifier.

Passive integrationPout(dBm)

Gain(dB)

PAE(%)

Area(mil mil)

Fully on-package 26 17 48 900 × 500

On-chip interstage 23 15 32 511 × 472

Fully on-chip 19 10 20 105 × 84

reject filter,” in Proc. IEEE Int. Microwave Symp., Boston, MA, June 2000,vol. 1, pp. 339-342.

[7] K. Lim, A. Obatoyinbo, M.F. Davis, J. Laskar, and R. Tummala, “Develop-ment of planar antennas in multi-layer package for RF-system on-a-pack-age applications,” in Proc. IEEE EPEP Topical Meeting, Boston, MA, Oct.2001, pp. 101-104.

[8] C.-H. Lee, A. Sutono, S. Han, and J. Laskar, “A compact LTCC Ku-bandtransmitter module with integrated filter for satellite communication ap-plications,” in Proc. IEEE Int. Microwave Symp., vol. 2, 2001, pp. 945-948.

[9] Y. Hirachi, Y. Aoki, T. Yamamoto, J. Ishibashi, and A. Kato, “A cost-effec-tive RF-module for millimeter-wave systems,” in Proc. Asia-Pacific Micro-wave Conf., 1998, pp.53-56.

[10] K. Lim, A. Obatoyinbo, A. Sutono, S. Chakraborty, C-H.Lee, E. Gebara,A. Raghavan, and J. Laskar, “A highly integrated transceiver modulefor 5.8 GHz OFDM communication system using multi-layer packagingtechnology,” in Proc. IEEE Int. Microwave Symp., Phoenix, AZ, May 2001,vol. 3, pp. 1739-1742.

[11] D. Heo, A. Sutono, E. Chen, Y. Suh, and J. Laskar, “A 1.9-GHz DECTCMOS power amplifier with fully integrated multilayer LTCC passives,”IEEE Microwave Wireless Comp. Lett., vol. 11, pp. 249-251, June 2001.

[12] M.F. Davis, A. Sutono, K. Lim, J. Laskar, V. Sundaram, J. Hobbs, G.E.White, and R. Tummala, “RF-microwave multi-layer integrated passivesusing fully organic system on package (SOP) technology,” in Proc. IEEEInt. Microwave Symp., Phoenix, AZ, May 2001, vol. 3, pp. 1731-1734.


Product Info - www.ieee.org/magazines/DirectAccess Product Info - www.ieee.org/magazines/DirectAccess

rf-system-on-package (sop) for wireless...

Documents