review porous silicon 1

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3 Chapter 2 Porous silicon 0 50 100 150 200 250 300 350 400 450 500 56 66 76 86 96 Year Number of publications Figure 2-1 Number of publications per year regarding porous silicon since it was first discovered Although porous silicon was first discovered by Uhlir [1] in 1956, significant interest in this material is more recent. Figure 2-1 [2,3] illustrates this increasing interest by plotting the number of publications per year on the subject of porous silicon since 1956. The small amount of interest shown in porous silicon from the mid-1970’s and throughout the 1980’s relates almost exclusively to its use for device isolation in integrated circuits [4,5] . The more noticeable interest shown from the start of this decade came with the demonstration by Canham [6] of room temperature photoluminescence from this material. Since this time the majority of research into porous silicon has focussed on observations of and explanations for both photoluminescence and electroluminescence from this material, and its potential optoelectronic applications. The work described in this thesis uses p-type porous silicon in the main. This chapter briefly reviews the fabrication and structure of porous silicon this p-type silicon and possible applications of both n- and p-type porous silicon. The demonstration of photoluminescence from porous silicon stimulated research into the use of porous silicon for optoelectronic circuits and forms around half of the literature currently available on porous silicon. Several mechanisms have been proposed for this photoluminescence and a brief review of both the observations and possible mechanisms is given in Appendix A. From a device point of view it is electroluminescence rather than photoluminescence which is important, and this is discussed in section 2.2.3 of this chapter. Porous silicon fabricated from a p + substrate is abbreviated to p + porous silicon and likewise for porous silicon fabricated from p , n and n + substrates. Porous silicon fabricated from p-type substrates or n-type substrates where the doping level is unspecified will be referred to p-type porous silicon and n-type porous silicon respectively.

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Page 1: Review Porous Silicon 1

3

Chapter 2

Porous silicon

0

50

100

150

200

250

300

350

400

450

500

56 66 76 86 96

Year

Num

ber o

f pub

licat

ions

Figure 2-1 Number of publications per year regarding porous silicon since it was firstdiscovered

Although porous silicon was first discovered by Uhlir[1] in 1956, significant interest in this material ismore recent. Figure 2-1[2,3] illustrates this increasing interest by plotting the number of publications peryear on the subject of porous silicon since 1956. The small amount of interest shown in porous siliconfrom the mid-1970’s and throughout the 1980’s relates almost exclusively to its use for device isolationin integrated circuits[4,5]. The more noticeable interest shown from the start of this decade came withthe demonstration by Canham[6] of room temperature photoluminescence from this material. Since thistime the majority of research into porous silicon has focussed on observations of and explanations forboth photoluminescence and electroluminescence from this material, and its potential optoelectronicapplications.

The work described in this thesis uses p-type† porous silicon in the main. This chapter briefly reviewsthe fabrication and structure of porous silicon this p-type silicon and possible applications of both n-and p-type porous silicon.

The demonstration of photoluminescence from porous silicon stimulated research into the use ofporous silicon for optoelectronic circuits and forms around half of the literature currently available onporous silicon. Several mechanisms have been proposed for this photoluminescence and a briefreview of both the observations and possible mechanisms is given in Appendix A. From a device pointof view it is electroluminescence rather than photoluminescence which is important, and this isdiscussed in section 2.2.3 of this chapter.

† Porous silicon fabricated from a p+ substrate is abbreviated to p+ porous silicon and likewise for

porous silicon fabricated from p–, n– and n+ substrates. Porous silicon fabricated from p-typesubstrates or n-type substrates where the doping level is unspecified will be referred to p-typeporous silicon and n-type porous silicon respectively.

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Porous Silicon

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Metal contact

O-ring

CathodeCell

Silicon wafer

From pump

Porous silicon

Electrode

_

To pump

+

a) Single-tank Cell b) Double-tank Cell

Figure 2-2 Schematic diagram of two arrangements commonly used to fabricate porous silicon(adapted from ref [15])

2.1 The fabrication and structure of porous silicon.The porous silicon described in this thesis was fabricated by the electrochemical anodisation of siliconin a hydrofluoric acid (HF) based electrolyte. This is the most common method of fabricating poroussilicon though the use of an ammonium fluoride based electrolyte has also been reported[7,8,9]. Thefabrication is usually conducted in the dark to prevent photogenerated currents contributing to theformation process.

An alternative method for fabrication is by a chemical stain etch[10,11,12] that requires dipping the siliconsubstrate in a hydrofluoric acid : nitric acid : water solution for 3-15 minutes. The porous siliconfabricated using this method is, however, inhomogeneous in both porosity and thickness due to thefact that hydrogen gas evolved during fabrication remains on the surface of the wafer[10]. For thesereasons the use of this method is rare, although it has been reported that the physical structure ofthese layers is similar to those fabricated by the anodisation method[12].

Porous silicon is composed of a silicon skeleton permeated by a network of pores. It is possible todefine the characteristics of a particular porous silicon layer in a number of ways. The methods ofidentification include the average pore and silicon branch widths, porosity, pore and branchorientation, and layer thickness. The specific nature of a layer depends upon the fabrication conditionsused, including the substrate doping and type, the hydrofluoric acid (HF) concentration and theacidity(pH value) of the electrolyte, the anodisation current density and anodisation time. Thetechniques used to assess these properties include various microscopy techniques (pore diameter,microstructure and layer thickness), gravimetric analysis[13] (porosity and layer thickness‡) and gasadsorption isotherms[14] (pore diameter).

2.1.1 Fabrication of porous silicon.Schematic diagrams for the two methods used to form porous silicon using the anodisation methodare shown in Figure 2-2[15]. Both these arrangements are essentially the same; the silicon wafer to beanodised forms the anode during anodisation and, together with an O-ring, seals the anodisation cell.In the double tank cell of Figure 2-2b porous silicon is only formed on the substrate surface in contactwith the anodising electrolyte of the left side cell. This is because porous silicon is only formed duringan anodic reaction.

Using either of the two arrangements the porous silicon layers fabricated are usually homogenous inboth porosity and thickness, except within approximately 2mm of the O-ring[15]. For the work presentedhere the area to be anodised had a radius of either 2.25cm or 4 inches; the inhomogeneity at theedges could therefore be avoided when selecting the portion of the porous silicon wafer with which towork.

‡ The porosity of a layer can be determined by weighing the silicon substrate both before and after

anodisation (m1 and m2 respectively) and again after porous silicon layer has been removed (m3).The porosity(P) and layer thickness(W) are then calculated by

P = (m1-m2)/(m1-m3) and W = (m1-m3)/(Sd)where S is the surface area of the wafer which is anodised and d is the density of bulk silicon

Page 3: Review Porous Silicon 1

Porous Silicon

5

0

100

200

300

0 100 200 300 400

NA = 1x1019 cm-3

NA = 1x1017 cm-3

Gro

wth

rate

(nm

/s)

Current density (mA/cm2)

Figure 2-3 Growth rate of porous silicon as a function of current density (Data taken from ref.[16])

Good homogeneity within the porous silicon layers is obtained because the electrical contact to thesilicon substrate is made using the entire back surface of the wafer. This prevents lateral potentialvariation across the wafer that would cause changes in the local current density. As discussed insection 2.1.3 the porosity of a layer is partly determined by current density. Thus maintaining aconstant current density throughout the substrate allows constant porosity porous silicon to beobtained, providing there are no local variations in the concentration of the hydrofluoric acid in theelectrolyte and that chemical leaching does not occur. The hydrofluoric acid concentration andchemical leaching are also factors that determine the porosity of a porous silicon layer, as discussedin section 2.1.3. Despite the nature of the anodic contact, however, hydrogen bubbles evolved duringthe anodisation can cling to the surface of the wafer and cause variations in the local potential. Forthis reason the electrolyte may be circulated during the anodisation to remove these bubbles. This isparticularly important in the double tank arrangement where the gas evolves during the cathodicreaction[15] and can cause local variations in potential throughout the substrate.

Figure 2-3 illustrates how the growth rate of porous silicon depends upon the anodisation currentdensity for starting substrates that are both lightly and heavily doped. It is obvious from the graph thatthe thickness of a porous silicon layer after a given time period depends upon the current density atwhich it has been anodised. The thickness of a porous silicon layer is therefore uniform providing aconstant current density is maintained whilst any variation in the local current density across the waferwould cause changes in the thickness of a layer across the wafer[6].

The electrical contact to silicon substrates with low doping levels can be improved by a high doseback implant. A metal evaporation is also necessary for these substrates when they are to beanodised in the single tank cell of Figure 2-2a. This is unnecessary for anodisation in the double tankbecause the contact is electrolytic and not metallic. An advantage of the double tank arrangement isthat it avoids a potential source of contamination of the porous silicon in any subsequent thermal andchemical processing[15]. Substrates with high doping levels require neither a back implant nor a metalevaporation for either arrangement.

The choice of electrolyte is determined by the necessity for the electro-active species required for theanodisation to be efficiently transported to the porous silicon - silicon interface where the anodisationprocess primarily occurs. The hydrophobic[17] and organophillic[15] nature of porous silicon means thatethanol is a more suitable carrier than water, hence its use in the electrolyte. It can be seen fromFigure 2-4, however, that roughness is still observed at the porous silicon – silicon interface. In thework described in Chapter 6 it will be seen that similar roughness also occurs at the interface betweenporous silicon layers of different porosity. The amplitude of this roughness does decrease withincreasing porosity. In one example[18] increasing the porosity from 65% to 85% caused the amplitudeof the roughness to be reduced from 6nm to 3nm. It is thought that this reduction is a result of theincreasing pore widths associated with increasing porosity allowing easier access of the electrolyte tothe pore tips. Ethanol also acts as a surfactant agent and assists in removing hydrogen bubbles fromthe surface(s) of the silicon substrate.

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Silic

onP

orou

s Si

licon

Figure 2-4 Interface between porous silicon and silicon substrate. The porous silicon layer hasa thickness of 5µm and a porosity of 56%.

The electrolyte used for the fabrication of the porous silicon described in chapter 6 of this thesisconsisted of a 1:1:2 ratio of HF, water and ethanol. Water forms part of the electrolyte merely becausethe hydrofluoric acid was supplied in a 50% aqueous form. Details of the electrolytes used for theporous silicon described in chapter 5 and section 6.4 are given in those sections.

2.1.2 Pore formation and interfacial roughnessThe first models of porous silicon layer formation assumed that the porous layer was formed on thesilicon substrate by a deposition process that involved the reduction of divalent silicon to amorphoussilicon[19,20]. It was later shown that this did not occur and a selective etching process within the siliconand not a deposition process formed the porous silicon layers[21].

The electrochemical anodisation of silicon will only provide porous silicon if the supply of holes to thesilicon substrate is the rate-limiting step. Anodisation where the diffusion of chemical reactants in theelectrolyte is the limiting step for dissolution causes a surface charge of holes to accumulate. If thisoccurs, hills on the surface of the silicon wafer (caused by surface roughness) dissolve faster thandepressions because they are more exposed to the electrolyte. Instead of forming porous silicon, thesilicon surface is then (electro-)polished. The critical current density below which porous silicon willform is defined as Jps

[22].

The exact mechanism for pore formation in a silicon substrate is still uncertain and severalmechanisms have been proposed[20]. Figure 2-5 illustrates the chemical dissolution mechanismsuggested by Lehmann and Gösele[23] that has received some attention[20,24]. Whether this is thecorrect dissolution process is unclear[20] but it does explain the hydrogen gas evolved duringanodisation[15], and the need for a hole supply for the dissolution to occur, a generally acceptedrequirement[19]. Another attraction of this mechanism is that it explains the fluoride contaminatedhydride passivation layer observed immediately following anodisation. Once exposed to an airambient, however, this surface changes to an oxide contaminated surface, the major contaminantsbeing mainly those elements that occur in the air in gaseous form[25,26].

Lehmann and Gösele expanded their model by suggesting that, providing the current density remainsbelow Jps, the pore formation is self-limited by the availability of holes within the silicon branches. Forp-type silicon substrates under anodic bias, the limitation of the hole supply may be caused byquantum confinement.

Figure 2-6, adapted from reference [24], shows the suggested band structure at the silicon - poroussilicon interface. It is initially assumed that the pore walls are depleted of the holes necessary for thedissolution. If a hole in the silicon substrate has sufficient energy it can penetrate into the siliconbranch causing additional dissolution and a further increase in the band gap. Holes will continue topenetrate into the branches until the band gap has increased sufficiently to prevent further migration ofholes into the branches, limiting the dissolution to the bulk silicon - pore interface. Increaseddissolution of the branches (increased porosity) is observed as the current density is increased due tothe additional energy the increased current density gives to the hole.

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1. In the absence of electron holes, a hydrogen saturatedsilicon surface is virtually free from attack by flouride ionsin the HF based electrolyte. The induced polarisationbetween the hydrogen and silicon atoms is low becausethe electron affinity of hydrogen is about that of silicon.

2. If a hole reaches the surface, nucleophillic attack on anSi-H bond by a fluoride ion can occur and a Si-F bond isformed.

3. The Si-F bond causes a polarisation effect allowing asecond fluorine ion to attack and replace the remaininghydrogen bond. Two hydrogen atoms can then combine,injecting an electron into the substrate.

4. The polarisation induced by the Si-F bonds reduces theelectron density of the remaining Si-Si backbonds makingthem susceptible to attack by the HF in a manner suchthat the remaining silicon surface atoms are bonded to thehydrogen atoms.

5. The silicon tretrafluoride molecule reacts with the HF toform the highly stable SiF6

¯ fluoroanion.

The surface returns to its ‘neutral’ state until another holeis made available.

Si

Si Si

H H

Si

Si Si

H HF

Si

Si Si

F H

H

F

H+

F

Si

Si Si

F F

H+

F

H2

Si

F F

FF

Si

H

Si

H

+2HF2H++SiF6

2-

Figure 2-5 Suggested mechanism for the electrochemical dissolution of silicon (after ref [23])

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- +

HFElectrolyte

Si

Porous silicon

HFelectrolyte

H

Si

+

Porous silicon Silicon

+

HF electrolyte Silicon

+

Top left - schematic diagram for the formation of poroussilicon

Top right - silicon branch isolated by two pores. Twopossible ways for the hole to cross the silicon - poroussilicon interface are shown (broken and dotted arrow).

Bottom - band diagram of the silicon - porous siliconinterface and the two different energy barriers for the holepenetrating into the wall (broken arrow) or into theelectolyte (solid arrow)

Figure 2-6 Band diagram of the silicon - porous silicon interface where the radius of a siliconbranch is small enough to exhibit quantum confinement (adapted from ref [24])

Current density (mA/cm2)

Poro

sity

(%)

40

50

60

70

80

90

0 100 200 300 400

NA = 1x1019 cm-3

NA = 1x1017 cm-3

Figure 2-7 Porosity - current density curve for p– and p+ porous silicon (taken from ref. [16])

2.1.3 PorosityThe factors that determine the porosity of a porous silicon layer include the substrate doping,anodisation current density and the HF concentration and pH value of the anodising electrolyte. Therelationship between porosity and current density is shown in Figure 2-7 for the porous silicon used forthe fabrication of optoelectronic components described in chapter 6. This graph shows how theporosity of a layer increases with increasing current density and decreasing substrate doping[22]. Theporosity also increases with decreasing HF concentrations and increasing pH values of the electrolyte.

Page 7: Review Porous Silicon 1

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a

b

c

Figure 2-8 Microstructure of porous silicon - a) Cross section of p– porous silicon (photographtaken from ref. [20]), b) Cross section of p+ porous silicon (photograph supplied byBerger [27]), c) Planar view of p+ porous silicon (photograph supplied by Loni [28])

The relationship between porosity and pH values is caused by chemical dissolution of the poroussilicon branches by OH– ions present in the electrolyte. The dissolution rate increases with increasinglevels of the OH– ions in the electrolyte and therefore increasing pH values. This chemical dissolutioncontinues for as long as the porous silicon remains in contact with the electrolyte, increasing theporosity of a layer even after the anodisation process is completed. The dissolution rate is partiallydependent upon the surface area available for reaction, a measurement that can be determined bygas adsorption isotherms[14]. The surface area density, defined as the surface area of the siliconbranches forming the porous silicon, varies from 200m2/cm3 for porous silicon formed from p+ silicon(ρ = 0.01Ωcm) to 600m2/cm3 for p– silicon (ρ = 1Ωcm)[14,15], though it decreases with increasingporosity above 50%[15].

The effect of chemical dissolution on a porous silicon skeleton is to reduce the diameter of theindividual silicon branches. At higher porosities, already thin branches may disappear weakening theremaining structure. Drying such layers can cause cracking or complete disintegration of the branchesdue to capillary tensions that occur on the branch surface at the liquid - vapour phase of drying. Theseforces can be avoided by supercritical drying. The use of such a technique has enabled layers of up to97% porosity to be fabricated[29].

2.1.4 Microstructure.The width and orientation of the branches and pores that form a porous silicon skeleton change as thelevel of doping in the original substrate is altered. Figure 2-8 shows SEM and TEM photographs ofboth p– and p+ porous silicon. As can be seen from Figure 2-8a porous silicon fabricated from lightlydoped p-type substrates consist of a highly inter-connected network of fine silicon branches. Thesebranches are typically less than 5nm wide and separated by pores of similar dimensions[30]. Figure 2-

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8b and Figure 2-8c illustrate how porous silicon fabricated from more heavily doped p-type substratesproduces layers with wider pores and silicon branches which run parallel to each other. The widths ofthe pores and branches of the p+ porous silicon typically have widths of 10 – 25nm though widths upto 100nm have been reported[31]. These wider pores explain the lower density of the surface area[31] ofp+ porous silicon reported in the previous section. Figure 2-8c shows how the silicon branches ofthese heavily doped layers have many small ‘buds’ that are not constrained to any plane[32]. It hasbeen noted that the distribution of the pore widths and the average pore width both increase withincreasing current density and decreasing HF concentrations in the electrolyte[14].

2.2 Applications of porous siliconA variety of applications for porous silicon have emerged since it was first discovered. It has alreadybeen noted that possible applications for porous silicon have been found in dielectric isolation ofintegrated circuits and various optoelectronic applications. Another area is that of micromachining[33] inwhich the porous silicon acts as a sacrificial layer. These main research areas are briefly reviewedbelow.

2.2.1 FIPOS process

During the 1980’s the main focus of porous silicon research lay in its potential application as analternative to other developing silicon on insulator (SOI) and silicon on sapphire (SOS) technologiesfor device isolation in integrated circuits. These were developed as an alternative to the conventionalmethods of isolation by doped channel-stops, suitably biased pn-junctions and thick dielectric layers.Compared to these conventional methods, the FIPOS (full isolation by porous oxidised silicon), SOIand SOS methods all offered the advantages of higher speed, lower power consumption, greaterpacking density and a reduced number of fabrication steps[34]. The additional attraction of the FIPOSprocess was the simplicity of processing and low leakage current[35].

The method is based on the oxidation of porous silicon to isolate pre-defined islands of crystallinesilicon from the bulk silicon substrate. Providing the porosity of the porous silicon was sufficiently high,the expansion of the silicon branches would fill the pores and not increase the thickness of the layercausing the silicon islands to warp. The ideal porosity was estimated to be near 56%[36]. Figure 2-10illustrates the methods used to implement the FIPOS process. This was achieved by either thepreferential anodisation to isolate predefined islands of silicon[5,39] or the epitaxial growth of silicon ona porous silicon layer that retains the monocrystalline character of the bulk substrate[37].

The original FIPOS method suggested by Imai was the preferential anodisation of a p-type bulk siliconsubstrate over implanted islands of n– silicon[5]. The current density - voltage characteristics ofdifferent substrates vary, as shown in Figure 2-10[15]. Limiting the potential during anodisationfacilitates the preferential anodisation of p+ substrate over p– substrates, n+ substrates over n– or p-type substrates and p-type substrates over n– substrates.

The original structures that were fabricated displayed the advantages of SOI and FIPOS devicesalready mentioned. Unfortunately devices fabricated in this manner required thick porous silicon layersin order to fabricate silicon islands of moderate widths. This was caused by the rate of pore formationbeing uniform in all directions giving rise to a layer of at least half the island width[5]. The layerthickness was reduced by either ion implantation or epitaxial growth to define the layers that wouldform the porous silicon[39]. The silicon islands were then formed by the epitaxial growth and etching ofan additional silicon layer. Another problem was that of wafer warpage that was resolved byimplementing the FIPOS method in an n/n+/n structure[38]. This also removed the remaining problemsof non-uniform porous silicon layers, and the thin wisp of silicon that remained under the silicon islandwhere the anodisation fronts met[39].

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Figure 2-9 Methods of implementing FIPOS technique

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Porous Silicon

12

0

20

40

60

80

100

120

140

-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

Potential (volts)

Cur

rent

den

sity

(mA

/cm

2)

n+

p+p-

n-

Figure 2-10 Current density - potential graph for p+, p–, n+ and n– silicon substrates (taken fromref [15])

2.2.2 MicromachiningThe techniques employed for dielectric isolation using porous silicon can also be used formicromachining applications. Micromachining is used to fabricate small-scale mechanical devices thatare integrated with conventional microelectronics. Examples of micromachined devices includemotors, cantilevers and a wide variety of sensors that are designed to sense temperature, IR and UVradiation, fluid flow or gas flow. Many of these structures are fabricated on free-standing membranes,structures that can be easily fabricated using porous silicon.

Conventional micromachining methods to form free-standing membranes include anisotropicallyetching[42] the rear of a substrate. This is a well established technology whose main drawback it theneed for double sided lithography. The use of double sided lithography is avoided when surfacemicromachining technology[42] is used. Instead an easily etchable sacrificial layer is deposited on tothe substrate surface followed by a second layer that will form the membrane. A second layer is thendeposited that, after defining the micromachined device and removing the sacrificial layer, forms thefree-standing membrane. The drawback of this method is the limited distance that can be obtainedbetween the membrane and substrate. The limiting factor is defined by the maximum thicknessobtainable for the sacrificial layer and is typically limited to several microns. Although this distancemay be sufficient for applications such as micromotors, applications such as sensing often requirethickness for the sacrificial layer to be several tens of microns to reduce heat transfer to the substrate.

Porous silicon provides a good alternative to both methods described above. It is formed without theuse of double-sided lithography and can be fabricated to thicknesses of several tens of microns. Thefabricated layers, regardless of thickness, are then easily removed using a weak potassium hydroxidesolution or even photoresist developing solution. Additionally, unlike anisotropic etching the geometryof the porous silicon layers is not limited to certain planes and so they can be formed locally on awafer with controlled undercutting.

A variety of devices have been demonstrated using this fabrication method including cantileverbeams[40], bolometers for thermal measurements[41], flow channels and wires[42]. Bridges[42] have beenshown to be stable under heat treatment and gas flow though not, unfortunately, to being dropped onthe floor! It has recently been suggested[41] that the porous silicon may not need to be removed in allapplications as was originally demonstrated over a decade ago for flow sensors[43]. The low thermalconductivity of p- porous silicon means that the porous silicon may provide sufficient thermal isolationfrom the substrate. This removes the need for removing the porous silicon to provide an air gap,providing an almost identical thermal isolation function whilst improving the mechanical robustness ofthe device.

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2.2.3 Light Emitting DiodesThe possibility of electroluminescent devices fabricated from porous silicon was soon realised soonafter the demonstration of photoluminescence from porous silicon. Electroluminescent devices usuallytake the form of either light emitting diodes (LEDs) or injection lasers. Though it is not certain whethera laser will ever be fabricated from porous silicon, LEDs emitting in the red part of the spectrum havebeen successfully demonstrated[44].

Electroluminescence from porous silicon was first reported in 1991[45] and was observed during anodicoxidation that is using a liquid contact which is not practical for device applications. The first solid stateLED was reported a short time later[46] and used a Schottky-type junction between gold and n-typeporous silicon to generate red light. Unfortunately the LED emitted light with the same intensity in boththe forward and reverse bias, had a high (200V) threshold voltage and operated with a low efficiency.Several groups demonstrated LEDs with a rectifying behaviour in 1992 that using a variety of contacts(gold[47], ITO[48] and n-type silicon carbide[49]). The emission spectra of each of the devices werecomparable to that of the LED of ref [46] but operated with a forward bias voltage of less than 10V andan efficiency less than 0.001%[44].

The critical characteristics concerning an LED are those of emission wavelength selection, externalefficiency, threshold voltage, carrier lifetime, width of the emission spectra, and device lifetime.Wavelength selection throughout the visible wavelengths has been demonstrated using either differentmetallic contacts[50] or by varying the fabrication conditions[48]. The external efficiency of these LEDshas slowly been increased with the best efficiencies reported to be in excess of 0.1% (up to 0.18%) forCW operation[27] and 0.2% for pulsed operation[51]. The operational lifetime of the LEDs has slowlybeen increased and experiments to calculate the lifetime of an integrated seven segment display oflow quantum efficiency were stopped after several hundred hours[52]. Similar results have also beenobserved in a separate demonstrator device[53]. Unfortunately the main disadvantages of poroussilicon LEDs are fundamental, those being the long carrier lifetime restricting the modulation rate tobetween 100kHz and 10MHz with the higher modulation rates only obtainable through a trade-off withthe quantum efficiency of the device[54].

2.2.4 Photodetectors and sensors.To complement light emission from porous silicon a variety of MSM[55] and p-n[56] photodetectorsutilising porous silicon have also been demonstrated. These detectors have been reported withresponse time as low as 2ns[57] and sensitivities in excess of 0.7A/W at 500nm[58]. The quantumefficiency of these devices has been reported[57] as high as 97% whilst the noise equivalent power hasbeen reported[59] to be as low as 6 x 10-13 W Hz1/2.

Porous silicon has also been investigated as a possible AR coating in solar cells[60]. Superlatticesformed using porous silicon have also been shown to act as filters allowing for the wavelengthselection of light[61]. These structures have been shown to make photodetectors colour sensitive whenused to replace the basic porous silicon layer[62]. Though as-anodised porous silicon can be used forcolour sensitivity in the red region of the electromagnetic spectrum, blue-sensitive filters are obtainedthrough oxidation of the porous silicon.

The use of porous silicon/silicon substrate junctions has also been used for sensing applications. Thestructures are fabricated by forming a porous silicon layer on a silicon substrate and contacting boththe porous silicon surface and the rear face of the substrate. Using these structures a gas sensorbased upon the changing current due to the dipole moment of the gas[63], and a humidity sensor basedupon the changing current with humidity[64] have both been demonstrated. Additionally applications forporous silicon in biosensing have also been demonstrated[65], using penicillin as an example. Coatingthe large surface area of the porous silicon with a penicillin sensitive enzyme causes the capacitance-voltage curve of the junction to shift with changing concentrations of penicillin.

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2.3 References1 A Uhlir, Electrolytic shaping of germanium and silicon, The Bell System Technical Journal, Vol

35, pp 333-347 (1956)2 Bath Information and Data Service, ISI and Compendex 1 databases3 Science Citation Indexes, 1956 - 19814 Y Wanatabe, Y Arita, T Yokoyama and Y Igarashi, Formation and properties of porous silicon

and its applications, J Electrochem Soc: Solid-State Science and Technology, Vol 122, No 10, pp1351-1355 (1975)

5 K Imai, A new dielectric isolation method using porous silicon, Solid-State Electronics, Vol 24,pp 159-164 (1981)

6 LT Canham, Silicon quantum wire array fabricated by electrochemical and chemicaldissolution of wafers, Appl Phys Lett, Vol 57, No 10, pp 1046-1048 (1990)

7 MM Koltun, Nature of film on surface of silicon photocell during anodic etching, R JournalPhys Chem, Vol 38, pp 381 (1964)

8 GM O’Halloran, M Kuhl, PM Sarro, PTJ Gennissen and PJ French, New etchant for thefabrications of porous silicon, Meetings Abstracts, Spring meeting of the ElectrochemicalSociety, Vol 96-1, pp 414 (1996)

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