1

Restoration of Star-Field Images Using High-Level

Languages and Core Libraries

Robin Bruce, Caroline Ruet, Dr Malachy Devlin, Prof Stephen

Marshall

28/03/2007 – Robin Bruce MRSC 2007 2

Overview

• Introduction• MED – SA algorithm• ANSI C implementation• DIME-C implementation• Comparison software/hardware• Application• Conclusion & further work

28/03/2007 – Robin Bruce MRSC 2007 3

Introduction

• There is a need for objective research in reconfigurable computing (RC)• Don’t just pick battles you know you’ll win

• Need to evaluate effectiveness of RC as a general purpose solution• How does it work on arbitrarily-selected

problems?

• There is a range of measures that we can apply to determine the performance improvement

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Hardware Comparisons

• Can Compare FPGAs to:

• Digital Signal Processors (DSPs)• Application-Specific Integrated Circuits

(ASICs)• Microprocessors• Other, could include

• Graphics Processing Units (GPUs)• Cell BE Processor• Clearspeed CX600

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Hardware Comparisons II

• Can compare with respect to:• Raw performance• Power consumption• Unit cost• Board footprint • Non-Recurring Engineering Cost (NRE)• Design time and Design cost

• The key metrics for a particular application may also include ratios of these metrics, e.g. performance/power, or performance/unit cost.

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Application Choice

• Implementation of the Minimum Entropy Deconvolution algorithm using Simulated Annealing method: representative of a computationally intense image-processing application

• Chosen Fairly Arbitrarily• Only knew that it was a compute-intensive

algorithm• Did not know how suitable the algorithm was for

implementation on RCs before committing to it

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Chosen Comparison

• Comparing a 90nm-process commodity microprocessor with a platform based around a 90nm-process FPGA • 3.2 GHz Intel Pentium D processor with 2 GB of

DRAM, with the gcc compiler • Nallatech H101-PCIXM card, with the DIME-C

compiler • Xilinx Virtex-4 LX160 FPGA, 512 MB of DRAM and

4 banks of 200MHz, 4 MB SRAM.

• Focussing on design time and raw performance improvement.

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MED – SA algorithm• Restore blurred images• MED algorithm with SA used to converge

towards the globally-optimum solution• y = x ٭ h + n

• y: observed image, x: original image, h: Gaussian filter, n: white Gaussian noise

• Estimate x from y

• Computation of 2 gradients: Δx=∂E/∂x, Δd=∂E/∂d

Estimated image Estimated filter Observed image

* =

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MED – SA algorithm

• Assumptions

• PSF is a Gaussian function

• m1, m2 designates the size of the PSF• d corresponds to the width of the PSF (blurring

level)• γ is a constant to normalise the Gaussian

function:

),0[

,0

2,1,0,1,22,1,exp)(

22

21

d

otherwise

mmford

mmdh

1 2

1)(m m

dh

28/03/2007 – Robin Bruce MRSC 2007 10

MED – SA algorithm

• Algorithm – minimising the Energy E

• Step 0: Set p=0 and initialise xp, Tp, dp and α, β, λ

• Step 1: Compute the energy Ep(xp, h(dp))

)(

),(),(),(),(

),(

1

))(,(1 2

1 2

1 2 2212121

214

2

212

xsizeof

kkykkhkkxkkx

kkx

dhxE

k kk k

k k

28/03/2007 – Robin Bruce MRSC 2007 11

MED – SA algorithm• Step 2: Select a candidate solution

x’p+1 = xp - αΔxp

d’p+1 = dp - βΔdp

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MED – SA algorithm• Step 3: Compute the energy E’p+1(x’p+1, h(d’p+1))

ΔE = E’p+1 - Ep

• Step 4:

If: where r is a random number Є [0,1]

Then:

Else: where f(.) is a decreasing function

• Step 5: p = p + 1, #_iterations = #_iterations – 1

• Step 6: Output xp+1 is the estimation image

pppppp TTandddxx 11111 ','

)(, 111 pppppp TfTandddxx

28/03/2007 – Robin Bruce MRSC 2007 13

ANSI C Implementation• Algorithm organisation

• The C program is not initially optimised

main

Energy DeDd

Apply_filter

DeDx

PSF

1st level

2nd level

3rd level

Functional Hierarchy

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• Code modification

• Loop Fusion

• Pipelining

• Spatial parallelism

• Resource optimisation

DIME-C Implementation

5/9

Spatial parallelism

Pipelining

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Example Optimisation

• Filter Application

• number of cycles: ≈ 480,111 (before optimisation: 12,000,133)

• number of slices: = 27733 (before optimisation: 3184)

Graphical representations of the filter implementation

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Core Libraries

• Made use of single-precision mathematical operators that are integrated into DIME-C

• Project depended on random number generator and exponential function• Not in compute intensive region of algorithm• Functions acted as an enabler to full algorithm

implementation

• Hear more about Core Libraries from me later today

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Implementation Procedure

1. Created a DIME-C project using the original source from the ANSI C project2.       Adapted source to allow compilation in both DIME-C and ANSI C environments

3.       Took advantage of the most obvious pipelining opportunities to create 1st FPGA implementation

4.       Examining the source code and the output of DIME-C, created an equation that expressed the runtime of the algorithm in cycles, as a function of the parameters of the algorithm, divided into key sections.

5.       Determined for a typical set of algorithm parameters the section that took up the majority of the runtime, and optimised the DIME-C for this section to create the 2nd FPGA implementation

6.       Repeated sections 4&5 to produce the 3rd FPGA implementation,

28/03/2007 – Robin Bruce MRSC 2007 18

Time to Solution

• Developing the initial ANSI C Implementation• 125 Person Hours

• Developing the DIME-C Implementation• 35 Person Hours

• Most time spent developing the software

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Software versus Hardware

Software 1st FPGA 2nd FPGA 3rd FPGA 4th FPGA

Cycles 7.98×1010 8.72×1010 4.30×1010 2.59×1010

Time in Seconds 216 798.00 87.24 42.96 25.92

Speedup vs. Software

1 0.27 2.48 5.03 8.33

% Contribution of:

De_Dx 5.02 45.94 93.29 88.91

Filter 94.74 51.86 2.24 3.71

Rest of Algorithm

0.24 2.20 4.47 7.38

• Several generations of the FPGA implementation compared to software

• DeDx remains the focus of a 5th version

28/03/2007 – Robin Bruce MRSC 2007 20

Example Results

• Simulation of real Black and White pictures• 200 x 200 image• 7 x 7 filter

Observed image:blurred and noisy

Restored image300 iterations

Original image

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Conclusion

• Good performance: speedup ≈ 8 • Design productivity was high using

DIME-C• Increased performance and productivity

possible using libraries of low-level IP cores

• 100-Page report available for those who want to know more

28/03/2007 – Robin Bruce MRSC 2007 22

Microprocessor Speedups

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Speedup in Context

• Moore’s Law Tells us Performance Doubles Every 18 months• Does it really?

• Hennessey & Patterson (2007) tell us that processor performance improved by 52% a year until 2002.

• Since 2002 it’s been running at around 20% a year

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Speedup in Context II

• If an FPGA gives you an 8x speedup now, how many years would it take for the microprocessor to catch up?

• Assumption Alert!• Benchmark used to evaluate processors gives a

good idea of how our application would perform• Comparing two best-effort implementations on

the same process node, FPGA and uP

• 8x Speedup would take 11-12 years to attain at 20% per annum improvements

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The Magic Numbers

• How much is being 12 years ahead of the competition worth?

• Reconfigurable Computing must offer (insert magic number) X improvement over conventional computing to see widespread adoption• Such a blanket statement is meaningless

• Depends on the economics of the application

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Acknowledgements

• Research is sponsored by Nallatech• Institute for System Level Integration

made everything possible• Caroline did all the hard work

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Quote

• Alan Perlis - When someone says "I want a programming language in which I need only say what I wish done," give him a lollipop.