research article area optimized fpga-based ...downloads.hindawi.com/archive/2013/820216.pdfresearch...

Hindawi Publishing CorporationISRNMachine VisionVolume 2013 Article ID 820216 6 pageshttpdxdoiorg1011552013820216

Research ArticleArea Optimized FPGA-Based Implementation ofThe Sobel Compass Edge Detector

Sanjay Singh1 Anil Kumar Saini1 Ravi Saini1 A S Mandal1

Chandra Shekhar1 and Anil Vohra2

1 CSIR-Central Electronics Engineering Research Institute (CSIR-CEERI) Pilani Rajasthan 333031 India2 Electronic Science Department Kurukshetra University Kurukshetra Haryana 136119 India

Correspondence should be addressed to Sanjay Singh sanjaycsirceerigmailcom

Received 22 December 2012 Accepted 4 February 2013

Academic Editors V Alchanatis and A Nikolaidis

Copyright copy 2013 Sanjay Singh et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compassoperator The architecture uses a single processing element to compute the gradient for all directions This greatly economizes onthe FPGA resourcesrsquo usages (more than 40 reduction) while maintaining real-time video frame ratesThemeasured performanceof the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video The use of pipelining further improved theperformance (185 fps for PAL size video and 740 fps for CIF size video) without significant increase in FPGA resources

1 Introduction

Edge detection is one of the most important areas in lowerlevel image processing Quality of detected edges plays avery important role in realization of complex automatedcomputermachine vision systems [1] Various edge detectionalgorithms are available in the literature and give differentresponses and details to the same input imageThe Sobel edgedetector is very popular than simple gradient operators dueto its property to counteract the noise sensitivity and easierimplementation [2] The accuracy of the Sobel operator foredge detection is relatively low because it uses two maskswhich detect the edges in horizontal and vertical directionsonly The accuracy can be enhanced by using the Sobel com-pass operator which uses a larger set of masks with narrowlyspaced orientations [3 4] But use of the Sobel compassedge detector increases the computational complexity signifi-cantly for computing edges It is hard to perform this compu-tationally intensive task in real-time with serial processorsAlternative to this is design of specific hardware (ASICs orFPGAs) for the Sobel compass edge detector The size andspeed of current generation FPGAs are comparable to ASICsbut FPGAs provide the possibility to perform algorithmchanges in later stages of the system development and reduce

the design cost and time [5]This makes the FPGAs a suitablechoice for such applications

Some recent FPGA implementations are available in theliterature for the Sobel compass edge detector In [6 7] theauthors discussed the most obvious FPGA implementationof the Sobel compass edge detector which uses multiple pro-cessing elements in parallel to compute gradient along eachdirectionThis increased the FPGA resourcesThe hardware-software codesign-based approach has been discussed in [8]for Sobel compass operator implementation which uses eightprocessing elements in parallel It is observed that the mainfocus of most of existing FPGA-based implementations ofthe Sobel compass edge detector has been on achieving real-time performance by using highly parallel architecture andthus fully ignored the FPGA resourcesrsquo optimizations FPGAresource (area) optimization is important for edge detectionas it is one of basic modules in the large automated videosurveillance system (which uses many complex algorithmsrequiring large FPGA resources)

In this paper an FPGA resource optimized hardwarearchitecture for the Sobel compass edge detector for real-timevideo surveillance applications is investigated We show thata single processing element is sufficient to compute the gra-dient along all directions in real-time As the Sobel compass

2 ISRNMachine Vision

Buffermemory

Maximum gradient

Gradient (45) To display controllerEdge

mapInput pixel

Gradient (0)

Gradient (90)

Gradient (135)

Figure 1 The Sobel compass edge detector block diagram

edge detector is sliding window operator smart buffer-basedmemory architecture is used to move the incoming pixels incomputing window The specific datapaths are designed andcontroller is developed to perform the complete task Thedesign and simulation are done using VHDL and targetedto Xilinx ML510 (Virtex-5 FX130T) FPGA platform Customcamera interface PCB is designed to interface Sony PTZ cam-era with ML510 FPGA platform Complete system is testedfor real-world scenario and it robustly detects the edges inreal-time for video sequences captured by camera

2 The Sobel Compass Edge Detector

In this section the used algorithm is briefly described fora more detailed description we refer to [3 4] The Sobeloperator is widely used for edge detection in images It hasadvantage over simple gradient operators because of its prop-erty to counteract the noise sensitivity It is based on comput-ing an approximation of the gradient of the image intensityfunction It uses two 3 times 3 spatial masks (119867119909 and119867119910) whichare convolvedwith the original image to calculate the approx-imations of the gradient The Sobel operator uses two filters

119867119909 = [

[

minus1 0 1

minus2 0 2

minus1 0 1

]

]

119867119910 = [

[

minus1 minus2 minus1

0 0 0

1 2 1

]

]

(1)

These compute the average gradient components acrossthe neighboring lines or columns respectivelyThe local edgestrength is defined as the gradient magnitude given by

119866119872(119909 119910) = radic1198671199092 + 1198671199102 (2)

The accuracy of the Sobel operator for edge detection isrelatively low because it uses two masks which detect theedges in horizontal and vertical directions onlyThis problemcan be addressed by using the Sobel compass operator whichuses a larger set of masks with narrowly spaced orientationsIt uses eight masks (119867

01198674511986790119867135

119867180

119867225

119867270

and

119867315

) each providing edge strength along one of the eightpossible directions of the compass

1198670= [

[


0 0 0

1 2 1

]

]

11986745= [

[

minus2 minus1 0

minus1 0 1

0 1 2

]

]

11986790= [

[

minus1 0 1

minus2 0 2

minus1 0 1

]

]

119867135= [

[

0 1 2

minus1 0 1

minus2 minus1 0

]

]

119867180= [

[

1 2 1

0 0 0


]

]

119867225= [

[

2 1 0

1 0 minus1

0 minus1 minus2

]

]

119867270= [

[

1 0 minus1

2 0 minus2

1 0 minus1

]

]

119867315= [

[

0 minus1 minus2

1 0 minus1

2 1 0

]

]

(3)

Only the result of four (1198670 11986745 11986790 and 119867

135) of the

above eight masks must actually be computed since the fourothers are identical except for the reversed sign The edgestrength 119864 at position (119909 119910) is defined as themaximum of theeight masks output (119863

0 11986345 11986390 119863135 119863180 119863225 119863270

and119863315

) that is

119864119909119910= max (119863

0 11986345 11986390 119863135 119863180 119863225 119863270 119863315)

(4)

Since119863180= minus1198630119863225= minus11986345119863270= minus11986390 and119863

135=

minus119863315

therefore the above equation can be rewritten as

119864119909119910= max (10038161003816100381610038161198630

1003816100381610038161003816 1003816100381610038161003816119863451003816100381610038161003816 1003816100381610038161003816119863901003816100381610038161003816 10038161003816100381610038161198631351003816100381610038161003816) (5)

Therefore to find the edges in all possible directions thefour masks (119867

01198674511986790 and119867

315) must be applied to each

pixel of the input imageThe Sobel compass edge detector hasthe advantage of not requiring the computation of squaresand square roots (which are considered relatively expensiveoperations)

3 Proposed Architecture

This section describes the details of the proposed architecturefor the Sobel compass edge detector Figure 1 shows the basic

ISRNMachine Vision 3

11987513 11987512 11987511

11987523 11987522 11987521

11987533 11987532 11987531

11987511

11987512

11987513

11987521

11987522

11987523

11987531

11987532

11987533

1198752119873 1198752119873minus1 11987524

1198753119873 1198753119873minus1 11987534

middot middot middot


119868119875 119875

Figure 2 Buffer memory architecture

Max gradient

PE0

PE45

PE90

PE135

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533Edge 119864

119866

Figure 3 The standard Sobel compass edge detector architecture

block level data flow diagram for computation of the Sobelcompass edge detector It consists of mainly four stages Inthe first stage the incoming pixel data from camera interfacelogic is stored in buffer memory Four gradients alongdifferent directions are computed in the second stage Themaximum gradient is selected and final edge map is com-puted by comparing the maximum gradient value with athreshold in the third and fourth stages respectively

In the Sobel compass operator the 3 times 3 masks are usedto compute gradient values along different directions over aninput image Therefore it is necessary to store at least tworows of input image data in FPGA on-chip memory beforethe processing begins To achieve this we have used smartbuffer-based memory architecture [9 10] which utilizes twoFIFOs and a set of registers in order to shift the image datainto computing window (Figure 2) The length of the shiftregister depends on input image width

The standard implementations of the Sobel compass edgedetector [6 7] use four processing elements in parallel forcomputing gradient along different directions For compar-ison of results with our proposed architecture we coded thestandard architecture (Figure 3) in VHDL synthesized usingXilinx ISE 103 and implemented on XilinxML510 (Virtex-5)FPGA boardThe resultedmaximum clock frequency for thisarchitecture is 1185MHz

It is observed that in the above implementation eachprocessing element (PE) performs the same set of operation

GR

ABC

A1B1

A2B2

A3B3

Processing elementA1minus B1

A3minus B3

(A2 minus B2)≪1 ∣A + B + C∣

Figure 4 Processing element architecture

(addition subtraction and multiplication by 2) on inputsapplied to them Processing element (PE) architecture for gra-dient computation is shown in Figure 4 The only differencefor four gradient computation units (PE

0 PE45 PE90 and

PE135

) is in inputs applied to them at a particular timeThere-fore by switching the inputs applied to anyone of processingelement in appropriate manner the same processing elementcan be used to compute all four gradients along differentdirectionsThis forms the basis for the proposed architecture

For real-time video surveillance applications therequired frame rate is 25 fps (frames per second) for PAL sizevideo (30 fps for NTSC size video) For high speed videosurveillance application for a frame rate of 50 fps for PAL size


Max Gr

Edge map

R1

Clk108

Out

PE

R2

R3

R4

Clk108

Clk27 Clk27

Control signals

Control signals

MU

X

DM

UX

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533

11987531 11987511

11987532 11987512

11987533 11987513

11987523 11987521

11987533 11987511

11987532 11987512

11987513 11987511

11987523 11987521

11987533 11987531

11987512 11987532

11987513 11987531

11987523 11987521

For1198670

For11986745

For11986790

For119867135

1198670

11986745

11986790

119867135

119867

Figure 5 The proposed Sobel compass edge detector architecture

video (60 fps for NTSC size video) clock frequency at whichthe image pixel data samples are available is 27MHz If theprocessing element is operated at 108MHz (4 times 27MHz) allthe four gradients can be computed for available image pixeldata before the arrival of next image pixel data using singleprocessing element The operating frequency of 108MHzis well within the limits of maximum operating frequency(1185MHz) resulted from synthesis results The digital clockmanagers available on FPGA are used to generate 108MHzclock from 27MHz pixel data clock

Figure 5 shows the proposed architecture for real-timecomputation of edges in an image using the Sobel compassedge detector Gradient computation for all directions isrealized through single processing element (operating at108MHz) The PE is used in appropriate sequential order indifferent time slots for computing gradients along all direc-tions This architecture greatly economizes on the FPGAresourcesrsquo usages (area) but needs storage elements to storeresults for future use and set of multiplexers for switching ofinputs and outputs in different time slots This architecturealso requires a controller which insures proper functioningof complete design Control signals for input selection mul-tiplexer and output selection demultiplexer are generated at108MHz so that inputs to processing element can be switchedand output can be stored properly Image pixel data movesthrough computing window at 27MHz Gradient values fordirections along 0 degree 45 degree 90 degree and 135

degree are computed by processing element in 4 cycles at108MHz clock frequency and the results are stored in R1R2 R3 and R4 registers which works at 108MHz frequencyFinally the maximum gradient is selected by using the valuesstored in registers R1 to R4 and final edge map is computedby comparing the maximum gradient value with a thresholdTherefore before the arrival of next image data samples (at27MHz) the final edge map of current pixel data is available

The performance of the system is further improved byusing a pipelined processing element (Figure 6) at the costof area occupied by pipelined registers Resulted maximumclock frequency is 405MHzTherefore a frame rate of 185 fpscan be achieved for standard PAL size video The improve-ment in clock frequency in pipelined architecture is due toreduced maximum combinational path delay in processingelement architecture

4 Results

The proposed architecture has been designed using VHDLsimulated in ModelSim and synthesized using Xilinx ISE103 It has been implemented on Xilinx ML510 (Virtex-5)FPGAplatform It is capable of computing the edgemap of aninput image well within the real-time constraints while utiliz-ing much less FPGA resourcesThe synthesis results (Table 1)reveal that the FPGA resources utilized by proposed edgedetection architecture are more than 40 less as compared


Table 1 Comparison of synthesis results

Synthesis parameters Standard [6 7]Figures 3ndash4

Proposed Figures 4 and 5(percentage of reduction)

Proposed pipelinedFigures 5ndash6 (percentage of reduction)

FPGA slices 67 40 (403) 42 (373)Slice LUTs 222 109 (509) 117 (473)LUT FF pairs 222 118 (468) 133 (401)Slice register 2 40 95Route-thrus 16 2 (875) 2 (875)

GR

A1B1

A2B2

A3B3

R11

R12

R13

R21

R22

Pipelined processing elementA1minus B1

A3minus B3

A2 minus B2

∣R21+ R22∣

R11 + R12

R13 ≪ 1

Figure 6 Pipelined processing element architecture

Figure 7 Input test images and output images

to the standard architecture The synthesis parameters arenumber of FPGA slices used by the logic number of sliceLUTs (Look Up Tables) number of LUT Flip Flop Pairs (LUTFlip Flop pair represents one LUT paired with one Flip Flopwithin a slice) number of slice registers andnumber of route-thrus (used for routing only) The resource reduction is notone-fourth of the resources utilized by standard architecturebecause of resource utilization by additional input and outputswitching logics The measured performance of our systemat 108MHz operating frequency for PAL size video is 50 fps

(frames per second) and CIF size video is 200 fps Pipelinedimplementation resulted in 185 fps frame rate for PAL sizevideo and 740 fps for CIF size video PAL size and CIF sizeimages are most commonly used video formats for videosurveillance cameras Therefore implemented system caneasily detect edges for high frame rate surveillance applica-tions while utilizing much less FPGA resources The inputtest images (PAL size) taken from camera and output imagesproduced by implemented system and displayed on monitorare shown in Figure 7


5 Conclusion

In this paper the hardware architecture for the Sobel compassedge detector implemented onXilinxML510 FPGAplatformhas been presented This architecture greatly economizes onthe FPGA resourcesrsquo usages (area) The architecture usedmore than 40 less FPGA resources as compared to thestandard implementations presented in the literature andmaintained real-time constraints for video processing Theimplemented architecture is integrated with camera anddisplaymonitorThe integrated system is tested for real-worldscenario It robustly detects the edge in real-time It can beefficiently used as part of complex computer vision systemwithout occupying much area

Acknowledgment

S Singh would like to thankMr Raj Singh Group Leader ICDesign Group for his constant guidance suggestions sup-port and encouragement

References

[1] M B Ahmad and T S Choi ldquoLocal threshold and booleanfunction based edge detectionrdquo IEEE Transactions on ConsumerElectronics vol 45 no 3 pp 674ndash679 1999

[2] T A Abbasi and M U Abbasi ldquoA novel FPGA-based architec-ture for Sobel edge detection operatorrdquo International Journal ofElectronics vol 94 no 9 pp 889ndash896 2007

[3] W Burger and M J Burge Digital Image Processing An Algo-rithmic Introduction Using Java Springer New York NY USA2008

[4] R C Gonzalez and R E Woods Digital Image ProcessingPearson Education New Delhi India 2009

[5] H Jiang H Ardo and V Owall ldquoA hardware architecture forreal-time video segmentation utilizingmemory reduction tech-niquesrdquo IEEE Transactions on Circuits and Systems for VideoTechnology vol 19 no 2 pp 226ndash236 2009

[6] Z Guo W Xu and Z Chai ldquoImage edge detection based onFPGArdquo in Proceedings of the 9th International Symposium onDistributedComputing andApplications to Business Engineeringand Science pp 169ndash171 August 2010

[7] A Nosrat and Y S Kavian ldquoHardware description of multi-directional fast sobel edge detection processor by VHDL forimplementing on FPGArdquo International Journal of ComputerApplications vol 47 no 25 pp 1ndash7 2012

[8] K C Sudeep and J Majumdar ldquoA novel architecture for realtime implementation of edge detectors on FPGArdquo InternationalJournal of Computer Science Issues vol 8 no 1 pp 193ndash202 2011

[9] Z Vasicek and L Sekanina ldquoNovel hardware implementationof adaptive median filtersrdquo in Proceedings of the 11th IEEEWorkshop on Design and Diagnostics of Electronic Circuits andSystems (DDECS rsquo11) pp 1ndash6 April 2008

[10] CMoore H Devos andD Stroobandt ldquoOptimizing the FPGAmemory design for a sobel edge detectorrdquo in Proceedings of the20th Annual Workshop on Circuits Systems and Signal Process-ing 2009

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



Buffermemory

Maximum gradient

Gradient (45) To display controllerEdge

mapInput pixel

Gradient (0)

Gradient (90)

Gradient (135)

Figure 1 The Sobel compass edge detector block diagram

edge detector is sliding window operator smart buffer-basedmemory architecture is used to move the incoming pixels incomputing window The specific datapaths are designed andcontroller is developed to perform the complete task Thedesign and simulation are done using VHDL and targetedto Xilinx ML510 (Virtex-5 FX130T) FPGA platform Customcamera interface PCB is designed to interface Sony PTZ cam-era with ML510 FPGA platform Complete system is testedfor real-world scenario and it robustly detects the edges inreal-time for video sequences captured by camera

2 The Sobel Compass Edge Detector

In this section the used algorithm is briefly described fora more detailed description we refer to [3 4] The Sobeloperator is widely used for edge detection in images It hasadvantage over simple gradient operators because of its prop-erty to counteract the noise sensitivity It is based on comput-ing an approximation of the gradient of the image intensityfunction It uses two 3 times 3 spatial masks (119867119909 and119867119910) whichare convolvedwith the original image to calculate the approx-imations of the gradient The Sobel operator uses two filters

119867119909 = [

[

minus1 0 1

minus2 0 2

minus1 0 1

]

]

119867119910 = [

[


0 0 0

1 2 1

]

]

(1)

These compute the average gradient components acrossthe neighboring lines or columns respectivelyThe local edgestrength is defined as the gradient magnitude given by

119866119872(119909 119910) = radic1198671199092 + 1198671199102 (2)

The accuracy of the Sobel operator for edge detection isrelatively low because it uses two masks which detect theedges in horizontal and vertical directions onlyThis problemcan be addressed by using the Sobel compass operator whichuses a larger set of masks with narrowly spaced orientationsIt uses eight masks (119867

01198674511986790119867135

119867180

119867225

119867270

and

119867315

) each providing edge strength along one of the eightpossible directions of the compass

1198670= [

[


0 0 0

1 2 1

]

]

11986745= [

[

minus2 minus1 0

minus1 0 1

0 1 2

]

]

11986790= [

[

minus1 0 1

minus2 0 2

minus1 0 1

]

]

119867135= [

[

0 1 2

minus1 0 1

minus2 minus1 0

]

]

119867180= [

[

1 2 1

0 0 0


]

]

119867225= [

[

2 1 0

1 0 minus1

0 minus1 minus2

]

]

119867270= [

[

1 0 minus1

2 0 minus2

1 0 minus1

]

]

119867315= [

[

0 minus1 minus2

1 0 minus1

2 1 0

]

]

(3)

Only the result of four (1198670 11986745 11986790 and 119867

135) of the

above eight masks must actually be computed since the fourothers are identical except for the reversed sign The edgestrength 119864 at position (119909 119910) is defined as themaximum of theeight masks output (119863

0 11986345 11986390 119863135 119863180 119863225 119863270

and119863315

) that is

119864119909119910= max (119863

0 11986345 11986390 119863135 119863180 119863225 119863270 119863315)

(4)

Since119863180= minus1198630119863225= minus11986345119863270= minus11986390 and119863

135=

minus119863315

therefore the above equation can be rewritten as

119864119909119910= max (10038161003816100381610038161198630

1003816100381610038161003816 1003816100381610038161003816119863451003816100381610038161003816 1003816100381610038161003816119863901003816100381610038161003816 10038161003816100381610038161198631351003816100381610038161003816) (5)

Therefore to find the edges in all possible directions thefour masks (119867

01198674511986790 and119867

315) must be applied to each

pixel of the input imageThe Sobel compass edge detector hasthe advantage of not requiring the computation of squaresand square roots (which are considered relatively expensiveoperations)

3 Proposed Architecture

This section describes the details of the proposed architecturefor the Sobel compass edge detector Figure 1 shows the basic


11987513 11987512 11987511

11987523 11987522 11987521

11987533 11987532 11987531

11987511

11987512

11987513

11987521

11987522

11987523

11987531

11987532

11987533

1198752119873 1198752119873minus1 11987524

1198753119873 1198753119873minus1 11987534



119868119875 119875


Max gradient

PE0

PE45

PE90

PE135

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533Edge 119864

119866






GR

ABC

A1B1

A2B2

A3B3


A3minus B3

(A2 minus B2)≪1 ∣A + B + C∣



0 PE45 PE90 and

PE135




Max Gr

Edge map

R1

Clk108

Out

PE

R2

R3

R4

Clk108

Clk27 Clk27

Control signals

Control signals

MU

X

DM

UX

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533

11987531 11987511

11987532 11987512

11987533 11987513

11987523 11987521

11987533 11987511

11987532 11987512

11987513 11987511

11987523 11987521

11987533 11987531

11987512 11987532

11987513 11987531

11987523 11987521

For1198670

For11986745

For11986790

For119867135

1198670

11986745

11986790

119867135

119867






4 Results








GR

A1B1

A2B2

A3B3

R11

R12

R13

R21

R22


A3minus B3

A2 minus B2

∣R21+ R22∣

R11 + R12

R13 ≪ 1






5 Conclusion


Acknowledgment


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










11987513 11987512 11987511

11987523 11987522 11987521

11987533 11987532 11987531

11987511

11987512

11987513

11987521

11987522

11987523

11987531

11987532

11987533

1198752119873 1198752119873minus1 11987524

1198753119873 1198753119873minus1 11987534



119868119875 119875


Max gradient

PE0

PE45

PE90

PE135

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533Edge 119864

119866






GR

ABC

A1B1

A2B2

A3B3


A3minus B3

(A2 minus B2)≪1 ∣A + B + C∣



0 PE45 PE90 and

PE135




Max Gr

Edge map

R1

Clk108

Out

PE

R2

R3

R4

Clk108

Clk27 Clk27

Control signals

Control signals

MU

X

DM

UX

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533

11987531 11987511

11987532 11987512

11987533 11987513

11987523 11987521

11987533 11987511

11987532 11987512

11987513 11987511

11987523 11987521

11987533 11987531

11987512 11987532

11987513 11987531

11987523 11987521

For1198670

For11986745

For11986790

For119867135

1198670

11986745

11986790

119867135

119867






4 Results








GR

A1B1

A2B2

A3B3

R11

R12

R13

R21

R22


A3minus B3

A2 minus B2

∣R21+ R22∣

R11 + R12

R13 ≪ 1






5 Conclusion


Acknowledgment


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Max Gr

Edge map

R1

Clk108

Out

PE

R2

R3

R4

Clk108

Clk27 Clk27

Control signals

Control signals

MU

X

DM

UX

11987511 11987512 11987513

11987521 11987522 11987523

11987531 11987532 11987533

11987531 11987511

11987532 11987512

11987533 11987513

11987523 11987521

11987533 11987511

11987532 11987512

11987513 11987511

11987523 11987521

11987533 11987531

11987512 11987532

11987513 11987531

11987523 11987521

For1198670

For11986745

For11986790

For119867135

1198670

11986745

11986790

119867135

119867






4 Results








GR

A1B1

A2B2

A3B3

R11

R12

R13

R21

R22


A3minus B3

A2 minus B2

∣R21+ R22∣

R11 + R12

R13 ≪ 1






5 Conclusion


Acknowledgment


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation















GR

A1B1

A2B2

A3B3

R11

R12

R13

R21

R22


A3minus B3

A2 minus B2

∣R21+ R22∣

R11 + R12

R13 ≪ 1






5 Conclusion


Acknowledgment


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










5 Conclusion


Acknowledgment


References













RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









research article area optimized fpga-based ...downloads.hindawi.com/archive/2013/820216.pdfresearch...

Documents