modeling registers with uvm tom fitzpatrick
TRANSCRIPT
Tom Fitzpatrick
Design and Verification in the SoC Era: Modeling Registers with UVM
Verification Evangelist DVT
October 2011
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The Idea Behind The Methodology
OVM & UVM underpin best practices — It's all about people... — Team Development
Peopleware is most important — Develop Skill Set — Common language — Strategy and cohesion — Clarity and transparency
A Guiding Methodology — Provides Freedom From Choice — Avoids Chaos and Repetition — Ease of Use APIs
— Not just for Super-heroes!
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Objective Separation of stimulus
generation from delivery Raise the abstraction level of
stimulus and checking Test bench configuration Interoperability
— Standard class library & API
Reuse — VIP — Testbench components — Stimulus
Justification Several people can develop
stimulus Increase productivity
Avoid expensive recompilation Important for intra and inter
company development Key to productivity
UVM Foundations
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• What does it do? • What are the use cases? • Which test cases are required? • What type of stimulus scenarios are required? • What represents correct behavior? • What kind of functional coverage do I need?
For the Design:
UVM Testbench - Architectural Design
DUT
SPI I/F
APB
IRQ
• How does the interface work? • What information is transferred? • Transaction variants? • Uni/bidirectional? Pipelined?
For Each Interface:
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UVC Structural Building Block
DUT
One per interface
UVC(agent)
Sequencer Driver
Monitor Configuration
Object
Stimulus Converts seq_item to pin wiggles
Sends stimulus to Driver
Detects transactions on the interface
Analysis port: Send transactions for checking
- Contains virtual interface handle - Pass information on how agent should behave
seq_item
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UVM Registers are Layered
UVM Register Layer provides protocol-independent register-based layering
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DUT
UVC(agent)
Sequencer Driver
Monitor Configuration
Object
UVM Reg Layer
Predict
RegSeq
Bus specific wr(0xAF, 0xDE);
Device specific cfg.write(0xDE);
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Registers, Blocks & Maps
Registers contain bits & fields
Register Map contains Registers
Register Block contains Maps
One Map per physical interface
Blocks are hierarchical
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R/W Char_Len
R Rsrv
R/W GoBsy
R/W RxNeg
R/W TxNeg
R/W LSB
R/W IE
R/W ASS
R Reserved
31:14 13 12 11 10 9 8 7 6:0 R/W
Char_Len R
Rsrv R/W
GoBsy R/W RxNeg
R/W TxNeg
R/W LSB
R/W IE
R/W ASS
R Reserved
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The Register Map – uvm_reg_map
Contains offsets for: — Registers and Memories — (Hierachical blocks) — (Sub-maps)
Also provides means to access registers — Handle for target sequencer — Handle for register layer adapter
A block can have > 1 map — AXI Master1, AXI Master2 (Fabric)
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DUT
UVC(agent)
Sequencer Driver
Monitor
SQR
SQR
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UVM Register Use Models
Stimulus Generation — Abstraction of stimulus:
– i.e. Set this bit in this register rather than write x to address y — Stimulus reuse
– If the bus agent changes, the stimulus still works — Front and Back Door access:
– Front door is via an agent – Back door is directly to the hardware via the simulator database
Configuration — Register model reflects hardware programmable registers — Set up desired configuration in register model then dump to DUT
– Randomization with configuration constraints
Analysis ‘Mirror’ — Current state of the register model matches the DUT hardware — Useful for scoreboards and functional coverage monitors
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class spi_reg_block extends uvm_reg_block; `uvm_object_utils(spi_reg_block) rand divider divider_reg; uvm_reg_map APB_map; // Block map function new(string name = "spi_reg_block"); super.new(name, build_coverage(UVM_CVR_ADDR_MAP)); endfunction virtual function void build(); divider_reg = divider::type_id::create("divider"); divider_reg.build(); divider_reg.configure(this, null, ""); divider_reg.add_hdl_path_slice("divider", 0, 16); APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN); APB_map.add_reg(divider_reg, 32'h00000014, "RW"); add_hdl_path("DUT", "RTL"); lock_model(); endfunction: build endclass: spi_reg_block
Block containing Register
Register Model Code Example (Only 1 Reg)
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class divider extends uvm_reg; `uvm_object_utils(divider) uvm_reg_field reserved; rand uvm_reg_field ratio; function new(string name = "divider"); super.new(name, 32, UVM_NO_COVERAGE); endfunction virtual function void build(); ratio = uvm_reg_field::type_id::create("ratio"); ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1); endfunction endclass
Register class with one field
Build is not the component build
A map is a component of a block
#bits Coverage
#bits lsb mode reset
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class spi_reg_block extends uvm_reg_block; `uvm_object_utils(spi_reg_block) rand divider divider_reg; uvm_reg_map APB_map; // Block map function new(string name = "spi_reg_block"); super.new(name, build_coverage(UVM_CVR_ADDR_MAP)); endfunction virtual function void build(); divider_reg = divider::type_id::create("divider"); divider_reg.build(); divider_reg.configure(this, null, ""); divider_reg.add_hdl_path_slice("divider", 0, 16); APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN); APB_map.add_reg(divider_reg, 32'h00000014, "RW"); add_hdl_path("DUT", "RTL"); lock_model(); endfunction: build endclass: spi_reg_block
Block containing Register
Register Model Code Example (Only 1 Reg)
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class divider extends uvm_reg; `uvm_object_utils(divider) uvm_reg_field reserved; rand uvm_reg_field ratio; function new(string name = "divider"); super.new(name, 32, UVM_NO_COVERAGE); endfunction virtual function void build(); ratio = uvm_reg_field::type_id::create("ratio"); ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1); endfunction endclass
Register class with one field
Build is not the component build
A map is a component of a block
UVM_NO_COVERAGE UVM_CVR_REG_BITS UVM_CVR_ADDR_MAP UVM_CVR_FIELD_VALS UVM_CVR_ALL
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Register Assistant* Overview Register/Memory Definition & Management for the Entire Design Process
Central, Scalable & Extensible Register/Memory Datamodel — Enables easy specification of registers — Manages register changes — Eliminates hand coding & resultant mistakes — Completely customizable
Automatically Generates Register Outputs — OVM/UVM Register Package — Synthesizable RTL — Documentation — Extensive roadmap
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* Included with Certe Testbench Studio Supports the entire design team
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Common Register Path
Generate the UVM/OVM register model Generate the DUT registers Use Certe templates to generate
UVM sequences, adaptor class & the bus agent
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Template-Generated
DUT
UVC(agent)
Sequencer Driver
Monitor RegSeq
SQR
Template Generated
Register Assistant -Generation
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UVM Register Package Generation
Register Definitions
Optional Blocks & Block Maps
Customer Example Early in project: 335 Registers 11,500 lines Final project: 1,000 Registers 35,000+ lines of Register Package code
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Register Documentation Generation
Communicate the register layer to all team members
Final documents auto-generated
Customizable content & style
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The Architecture – Open & Extensible
Datamodel A P I
A P I
Block Map
Reg. Definitions
Blocks
Documentation
OVM/UVM Pkg.
Readers Writers
Checks
Control File
RTL
Spreadsheet (CSV) IP-XACT API calls
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UVM Coverage
You can specify the coverage model you wish to generate for instances in a block
Simply add a column to your spreadsheet
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UVM Register Class Access API
Direct access methods reg.read() and reg.write()
— Access the hardware register and update the register database — Can specify front or back door access
– Front door access takes time and may create side effects – Uses bus agent and consumes clock cycles
– Back door access is instant and does not cause side effects – Uses simulation database and access API (VPI)
— Not used for individual fields
reg.peek() and reg.poke() — For back door accesses, register model updated with result — Can be used for individual fields
The register model has two register variables: — Desired value
– For when a field has been updated, but not the hardware — Mirrored value
– Containing the latest known value
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Register Access Method Fields
Type Name Purpose
uvm_status_e status Indicates Access completed OK
uvm_reg_data_t value Data value transfered
uvm_path_e path Front or back door access
uvm_reg_map map Map to use for access
uvm_sequence_base parent Parent sequence
int prior Sequence priority on sequencer
uvm_object extension Transfer extension object
string fname Filename (For reporting)
int lineno Line number (For reporting)
Good news – most of these fields have defaults!
A typical register access only needs a few of these: spi_rm.ctrl.write(status, wdata, .parent(this));
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Register Stimulus Examples – Base Class class spi_bus_base_seq extends uvm_sequence #(uvm_sequence_item); `uvm_object_utils(spi_bus_base_seq) // SPI Register model: spi_reg_block spi_rm; // SPI env config object (contains register model handle) spi_env_config m_cfg; // Properties used by the various register access methods: rand uvm_reg_data_t data; // For passing data uvm_status_e status; // Returning access status // Common functionality: // Getting a handle to the register model task body; m_cfg = spi_env_config::get_config(m_sequencer); spi_rm = m_cfg.spi_rm; endtask: body endclass: spi_bus_base_seq
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Sequence base class contains variables common to all register sequences: • data, status • register model handle
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Register Stimulus Example: Set Divider Value class div_load_seq extends spi_bus_base_seq; `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2, 16'h4, 16'h8, 16'h10, 16'h20, 16'h40, 16'h80};} task body; super.body; // Randomize the local data value assert(this.randomize()); // Write to the divider register spi_rm.divider_reg.write(status, data, .parent(this)); endtask: body endclass: div_load_seq
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Extends base sequence Randomizes data value with specific constraint Writes data to divider register
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Register Sequence Example – TX Data Load class data_load_seq extends spi_bus_base_seq; `uvm_object_utils(data_load_seq) uvm_reg data_regs[]; // Array of registers task body; super.body; // Set up the data register handle array data_regs = '{spi_rm.rxtx0_reg, spi_rm.rxtx1_reg, spi_rm.rxtx2_reg, spi_rm.rxtx3_reg}; // Randomize order data_regs.shuffle(); foreach(data_regs[i]) begin // Randomize register content and then update assert(data_regs[i].randomize()); data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this)); end endtask: body endclass: data_load_seq
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Extends the base class
Gets an array of register handles
Randomizes the array index order
Foreach reg in the array: Randomize the content Updates the register
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How Do Front Door Register Accesses Work?
When an explicit register access method is called — The register access method forms a generic register command:
– Address, Data, Read or Write — This is then sent through a layering to the target bus agent
The layering has to convert: — Generic register requests to
target bus sequence items
This conversion takes place in the adapter — Extended from uvm_reg_adapter
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DUT
UVC(agent)
Sequencer Driver
Monitor RegSeq
SQR
B
Reg
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Register Adapter Class Example class reg2ahb_adapter extends uvm_reg_adapter; `uvm_object_utils(reg2ahb_adapter) function new(string name = "reg2ahb_adapter"); super.new(name); endfunction virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb"); ahb.HWRITE = (rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE; ahb.HADDR = rw.addr; ahb.DATA = rw.data; return ahb; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); ahb_seq_item ahb; if (!$cast(ahb, bus_item)) begin `uvm_fatal("NOT_AHB_TYPE","Provided bus_item is not of the correct type") return; end rw.kind = (ahb.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE; rw.addr = ahb.HADDR; rw.data = ahb.DATA; rw.status = UVM_IS_OK; endfunction endclass: reg2ahb_adapter
reg2bus() converts register item to bus item – note single access only
bus2reg() converts bus item to reg item
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Keeping The Register Model Up To Date
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Need to update register model with results of hardware access — This is referred to as prediction
Two ways: — Auto prediction
– Register model updates based on value written or read back – OK in simple situations where only one way to access the DUT
registers – Requires no additional components
— Explicit prediction (UVM Default)
– A predictor component: – Observes bus analysis transactions – Updates the register model on what it observes
– Works for normal to complex scenarios – Supports hierarchical reuse
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UVC(agent)
Sequencer Driver
Monitor
reg
Auto Prediction
For ‘simple’ scenarios: — Only sequences accessing the bus agent are register sequences — Register can only be accessed via one bus
The register model updates itself — Based on value read or written to the register
Has to be enabled – reg_model.set_auto_predict(1);
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RegSeq
SQR
Breq
Reg
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Predictor
Explicit Prediction - Recommended
Supports arbitrary complexity
Predictor component updates register model — Based on any detected bus transaction — Regardless of origin
Supports vertical reuse
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UVC(agent)
Sequencer Driver
Monitor
RegSeq
SQR
reg
Breq
Reg Breq
Reg
Breq Breq
Reg
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SQR
Explicit Prediction - Recommended
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Predictor
UVC(agent)
Sequencer Driver
Monitor
RegSeq
SQR
reg
reg
Predictor UVC(agent)
Sequencer Driver
Monitor
RegSeq
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Register Model Testbench Integration class spi_env extends uvm_env; apb_agent m_apb_agent; spi_env_config m_cfg; // Register layering adapter: reg2apb_adapter reg2apb; // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; // Set the predictor adapter: apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect
Predictor is a parameterised uvm base class
Predictor is integrated during the connect phase
Register adapter specific to bus agent
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Register Read And The Register Mirror
Read cycle results in the register model being updated
mirrored value
desired value
hardware value
Mirrored and desired value out of step with hardware value
Before
mirrored value
desired value
hardware value
Mirrored and desired value updated at the end of the bus read cycle
After
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Register Write And The Register Mirror
mirrored value
desired value
hardware value
Mirrored and desired value updated at the end of the write cycle
After
mirrored value
desired value
hardware value
mirrored value
desired value
hardware value
Hardware value changed by bus write cycle
During
Initial state, hardware and reg model in sync
Before
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Register Model Internal Access And Update()
Indirect methods: — Only access the register database
reg.get(), reg.set(), — Can be used on registers and fields
reg.reset(), reg.get_reset() — set/get the register or field reset value
reg.update() — Cause the hardware to be updated if register model content has
changed via reg.set(), reg.reset() or reg.randomize() — Can specify front or back door access
These methods set the desired value
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Register Write And The Register Mirror
mirrored value
desired value
hardware value
Mirrored value updated at the end of the write cycle
After
mirrored value
desired value
hardware value
mirrored value
desired value
hardware value
Desired value changed by indirect access method (e.g. set())
set()
Initial state, hardware and reg model in sync
Before
mirrored value
desired value
hardware value
Update() transfers desired value to HW via a write bus cycle
update()
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Built-In Sequences
Sequences are automatic — Low overhead to use — Useful for initial sanity checks on bus connectivity
Access modes are respected — e.g. Read only registers are not bit bashed — Read only memories are not tested
Memories, Registers or Fields can be opted out of a test — e.g. Clock enable bit — Mechanism is to use the uvm_resource_db to set an attribute for
the register
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Register Built-In Sequences
Sequence Name Description
uvm_reg_hw_reset_seq Checks register reset values
uvm_reg_single_bit_bash_seq Checks R/W path to each register bit in a register
uvm_reg_bit_bash_seq Runs single_bit_bash_seq on a register block
uvm_reg_single_access_seq Checks that both front and back door accesses work correctly for a register
uvm_reg_access_seq Runs single_access_seq on a register block
uvm_reg_shared_access_seq If a register is in multiple maps, checks that accesses can be made from each map
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Stimulus Reuse (Bridge Example)
SPI master is integrated inside an AHB peripheral block
Host bus sequences can reused as is
Testbench structure changes
SPI Master
APB SPI
AHB to APB Bridge
Another DUT
APB ANI Another DUT
APB ANI Another DUT
APB ANI
AHB
Bus Agent
SPI Host Bus Sequence
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APB
Bus Agent
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Stimulus Reuse Code Example class spi_env extends uvm_env; apb_agent m_apb_agent; spi_env_config m_cfg; // Register layering adapter: reg2apb_adapter reg2apb; // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; // Set the predictor adapter: apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect
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Stimulus Reuse Code Example class spi_env extends uvm_env; apb_agent m_apb_agent; spi_env_config m_cfg; // Register layering adapter: reg2apb_adapter reg2apb; // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; // Set the predictor adapter: apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect
class io_ss_env extends uvm_env; ahb_agent m_ahb_agent; io_ss_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2ahb; // Register predictor: uvm_reg_predictor #(ahb_seq_item) ahb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_ahb_agent_cfg.active == UVM_ACTIVE) begin reg2ahb = reg2ahb_adapter::type_id::create("reg2ahb"); // Register sequencer layering part: m_cfg.io_ss_rm.TOP_map.set_sequencer(m_ahb_agent.m_sequencer, reg2ahb); // Set the predictor map: ahb2reg_predictor.map = m_cfg.io_ss_rm.TOP_map; // Set the predictor adapter: ahb2reg_predictor.adapter = reg2ahb; // Connect the predictor to the bus agent monitor analysis port m_ahb_agent.ap.connect(ahb2reg_predictor.bus_in); end endfunction: connect
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Stimulus Reuse Layer II – Across Fabric
SPI Master
APB SPI
AHB to APB Bridge
AXI
Bus Agent
SPI Host Bus Sequence
AXI Bus
Fabric AXI
2 AHB
Bridge
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Register Stimulus Reuse: Set Divider Value
class div_load_seq extends spi_bus_base_seq; `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2, 16'h4, 16'h8, 16'h10, 16'h20, 16'h40, 16'h80};} task body; super.body; // Randomize the local data value assert(this.randomize()); // Write to the divider register spi_rm.divider_reg.write(status, data, .parent(this)); endtask: body endclass: div_load_seq
Extends base sequence which gets register model handle from config object. Sequence works as before but via the AHB agent
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Relevant Parts Of Top Level Environment
class sys_env extends uvm_env; axi_agent m_axi_agent; sys_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2axi; // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"); // Register sequencer layering part: m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi); // Set the predictor map: axi2reg_predictor.map = m_cfg.sys_rm.TOP_map; // Set the predictor adapter: axi2reg_predictor.adapter = reg2axi; // Connect the predictor to the bus agent monitor analysis port m_axi_agent.ap.connect(axi2reg_predictor.bus_in); end endfunction: connect
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UVM Register Package Works with OVM
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`include “ovm_macros.svh” `include “uvm_reg_macros.svh” import ovm_pkg::*; import uvm_reg_pkg::*; class sys_env extends ovm_env; axi_agent m_axi_agent; sys_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2axi; // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor; function void spi_env::connect(); if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"); // Register sequencer layering part: m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi); // Set the predictor map: axi2reg_predictor.map = m_cfg.sys_rm.TOP_map; // Set the predictor adapter: axi2reg_predictor.adapter = reg2axi; // Connect the predictor to the bus agent monitor analysis port m_axi_agent.ap.connect(axi2reg_predictor.bus_in); end endfunction: connect
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UVM Register Summary
Register model follows hardware structure — Fields, Registers, Blocks, Maps
Register model generator available: — Certe Register Assistant
Register access API: — Internal access – get(), set() etc
– Sets up desired value — External access – Front and Backdoor
Access layered via model — Generic sequences adapted to target bus sequences — Sequence reuse straight-forward
Use explicit prediction Built in sequences available for initial testing Works with OVM
TF - UVM Recipe of the Month 10/11 45
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TF - UVM Recipe of the Month 10/11 46
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