registers and counters

Registers and Counters

What is a Register?

A Register is a collection of n flip-flops with some common function or characteristic Control signals - common clock, clear, load, etc. Function - part of multi-bit storage, counter, or

shift register

At a minimum, we must be able to: Observe the stored binary value Change the stored binary value

What is a Register?

What is a Register?

n bit output

n bit input

Clear

Clock A

Load

Load input controls the transfer of data(input) to A.

Load is controlled either by the clock or FF inputs.

Parallel Load Register with clock gating

Load is controlled by clock input-may cause ‘clock skew’:

Clock arrives at different times to different FF’s

C=Load’+Clock

Kinds of Registers

Storage RegisterGroup of storage elements read/written as a unit

4-bit register constructed from 4 D FFsShared clock and clear lines

TTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)

Schematic Shape

Q1

CLR

D3D2D1D0

171

Q1

Q0Q0

CLK Q3Q3Q2Q2

11

109

5

67

43

2

14

13

151

12

V+

D3

D2

D1

D0

CLR

CLK

Q3

Q3F

Q2

Q2F

Q1

Q1F

Q0

Q0F

D Q

C Q

D Q

C Q

D Q

C Q

D Q

C Q

Kinds of Registers and Counters

Input/Output Variations Selective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs

74377 Octal D-type FFswith input enable

74374 Octal D-type FFswith output enable

EN enabled low and lo-to-hi clock transition to load new

data into register

OE asserted low presents FF state to output pins; otherwise

high impedence

HGFEDCBA

QHQGQFQEQDQCQBQA

OE

37411

1

3478

13141718

256912151619

CLK

D3

D6Q5

Q2

377

Q1Q0

Q3

EN CLK

Q6

Q4

Q7

D5

D2D1D0

D4

D7

1

3478

13141718

11

256912151619

FF input controlled load:This Register will not cause a clock skew

Register Files

A Register File is a collection of m registers, like a very small memory.

All CPU’s have register files of varying sizes A typical one is: 32 registers of 32 bits each Consider a small, 4 register file Each register is specified by a 2 bit code. An input might be loaded to a register with a given

code(select) An output might be picked up from a register with

a given code

Register Files

a 4-register file:

2x4 decoder

Register Select

LoadR1

R2

R3

R4

n-bit input

n-bit output

Read/Write

EN

Kinds of Registers

Register Files

Two dimensional array of flip-flopsAddress used as index to a particular wordWord contents read or written

74670 4x4 Register File withTri-state Outputs

Separate Read and Write EnablesSeparate Read and Write AddressData Input, Q Outputs

Contains 16 D-ffs, organized asfour rows (words) of four elements (bits)

670

Q4

D1

D4D3D2

Q3Q2Q1

WE

WAWB

RE

RARB

54

11

1413

12

15123

10976

Microoperations

Registers and transfers may be represented by standard symbols

A microoperation: an operation on registers or in other parts of a computer performed in one clock cycle.

Transfer, Arithmetic-Logic, Shift microoperations

Data Transfer

Information is moved from register to register by: Parallel data transfer Serial data transfer

For example: Older printers use parallel data transfer USB devices use serial data transfer

Parallel Data Transfer

Parallel data transfer moves data from one registerto another at one time

clock

Reg. A Reg. B

When clock occurs, all bits of A are copied to B

Register Transfer Microperations

R1 R2 means: Transfer the contents of

Register R2 to register R1 at the edge of the clock in parallel.

We might also have:

K1: R1 R2 which means: The transfer occurs only when the control condition T1

is 1.

Register Transfer Microperations

Register transfer- one to one

Register Transfer-2 to one:

K1: R0 R1

K1’K2: R0 R2

Assume K1 and K2 never becomes 1 at the same time

We maY extend the idea to many to one

Arithmetic Microoperations

Implementation of add-subtract

Microoperations:

X’.K1: R1 R1+ R2

X .K1: R1 R1+R2’ +1

Logic Microoperations


Uses of Logic microoperations Usually used to change the desired bits of a

register Use a ‘mask’ as the contents of the second

operand for the logic operation AND: masks and clears, OR: sets, XOR:

complements desired bits(remember

1 EXOR X=X’, 0 EXOR X= X


Examples: R1: 0010 1101

R2: 0000 1111(mask register)

R1 AND R2 : 0000 1101(clears left bits) R1 OR R2: 0010 1111(sets right

bits) R1 EXOR R2: 0010 0010(left bits

complemented)

Shift Microoperations

Shift Registers

Storage + ability to circulate data among storage elements

Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal

Wrap around from rightmost element to leftmost element

Shift DirectionReset

ResetShift

CLK CLK CLK CLK

Vcc

Vcc

J Q

K Q

J Q

K Q

J Q

K Q

J Q

K Q

Q1 Q2 Q3 Q4

Q 1 1

0

0

0

Q 2 0

1

0

0

Q 3 0

0

1

0

Q 4 0

0

0

1

Shift

Shift

Shift

Serial Data Transfer

Serial transfer moves data bits from A to B one bit per clock Rx and Tx have single wire between the two. For ‘n’ bit registers, it takes ‘n’ clocks for data move

Reg. R2

1 bitsignal

Usual implementation is with a shift register.

Reg. R1

clock


Typical serial transfer is a multi-step process Load transmit shift register with data to send Shift data bit by bit from transmit to receive SR Transfer received data to other registers

The transmit SR must have parallel load AKA parallel to serial shift register

The receive SR must have parallel outputs AKA serial to parallel shift register

Other control/timing signals usually needed


Reg. A (P to S)

1 bit signal(serial data)

Reg. B (S to P)

clock

Parallel Transmit

Data

Parallel Receive

Data

‘n’ bits

‘n’ bits

load

SL


Serial data transfer used where data rate is relatively slow and/or parallel bit transfer channels are expensive PC serial port and USB interfaces wireless/fiber optic data transmissions

Cell phonesWireless networksSatellite telephone/TVMars rover/orbiter communications

Typical Multi-Function Shift Register

Shift Register I/OSerial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. Right

74194 4-bit UniversalShift Register

Serial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered Devices

S1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold state

Multiplexing logic on input to each FF!

Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications

S1S0

LSI

ABCD

RSI

CLK

CLR

QAQBQCQD

Shift Register with Parallel Load

Right shift only

Shift Register with Parallel Load

Serial Transfer with Shift Registers

Shift Register Application: Parallel to Serial Conversion

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

D7D6D5D4

Sender

D3D2D1D0

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

QAQBQCQD

S1S0LSIDCBA

RSICLK

CLR

Receiver

D7D6D5D4

D3D2D1D0

Clock

194 194

194194

ParallelInputs

Serialtransmission

ParallelOutputs

Counters

Counters

Proceed through a well-defined sequence of states in response to the count signal.

3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...

3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...

The count sequence can be Binary or BCD or Gray Code or any other sequence you want.

Usually there will be a set of control inputs (enable, load, reset)in addition to the clock.

The basic counter is a sequential circuitwhere the state (the count value) is the output.

The basic counter is a sequential circuitwhere the state (the count value) is the output.

The counter circuit may have no other input other than the clock. This is known as an autonomous sequential circuit.The counter circuit may have no other input other than the clock. This is known as an autonomous sequential circuit.

Counters

A common 4-bit counter

74163 Synchronous4-Bit Upcounter

Synchronous Load and Clear Inputs

Positive Edge Triggered FFs

Parallel Load Data from D, C, B, A

P, T Enable Inputs: both must be asserted to enable counting

RCO: asserted when counter enters its highest state 1111, used for cascading counters "Ripple Carry Output"

74161: similar in function, asynchronous load and reset

QAQBQCQD

163RCO

PT

ABCD

LOAD

CLR

CLK2

710

15

9

1

3456

14

1211

13

Counters

Ring Counter

V+

J CLK K

S

R

Q

Q

+V +V +V

0 1

Shift

Q 1 Q 2 Q 3 Q 4

\Reset

J

K

S

R

Q

Q

J

K

S

R

Q

Q

J

K

S

R

Q

Q CLK CLK CLK

1

0

0

0

Shift

Q1

Q2

Q3

Q4

100

0

1

0

0

0

0

1

0

0

0

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1

1

0

0

0

End-Around

4 possible states, single bit change per state, useful for avoiding glitches

Must be initialized

Counters

Twisted Ring (Johnson, Mobius) CounterInvertedEnd-Around

8 possible states, single bit change per state, useful for avoiding glitches

+V

J CLK K

S

R

Q

Q

+V +V +V

0 1

Shift

Q 1 Q 2 Q 3 Q 4

\Reset

J

K

S

R

Q

Q

J

K

S

R

Q

Q

J

K

S

R

Q

Q CLK CLK CLK

1

0

0

0

1

1

0

0

1

1

1

0

1

1

1

1

0

1

1

1

0

0

1

1

0

0

0

1

0

0

0

0

Shift

Q 1

Q 2

Q 3

Q 4

100

Counter Design : Synchronous Counters

Introduction

The process is a special case of the general sequential circuit design procedure.

no decisions on state assignment or transitions current state is the output

Example: 3-bit Binary Upcounter Decide to implement withToggle Flipflops

What inputs must bepresented to the T FFsto get them to change

to the desired state bit?

We need to use the T FF excitation table to

translate the present/next state values to FF inputs

00001111

00110011

01010101

00011110

01100110

10101010

Presentstate

Nextstate

000

001

010

011

111

110

101

100

Self-Starting Counters

Start-Up StatesAt power-up, counter may be in any possible stateDesigner must guarantee that it (eventually) enters a valid stateEspecially a problem for counters that validly use a subset of states

Self-Starting Solution:Design counter so that even the invalid states eventually transition to valid state

Two Self-Starting State Transition Diagrams

S0 S4

S3S1

S2

S6

S5 S7

S0 S4

S3S1

S2

S5

S6 S7

4 bit syncronous binary counter

Up-down counter with parallel load

Asynchronous vs. Synchronous Counters

Ripple Counters: Asynchronous

Deceptively attractive alternative to synchronous design style

Count signal ripples from left to right

State transitions are not sharp!

Can lead to "spiked outputs" from combinational logic decoding the counter's state

Can lead to "spiked outputs" from combinational logic decoding the counter's state

T

Count

Q

QA

T Q

QB

T

CLK

Q

QC

CLK CLK

Ripple Counters (Up or Down)

Three characteristics determine if a ripple counter counts up or down FF clock input polarity FF output to clock polarity Counter output polarity

A ripple counter with negative clock polarity, Q to next FF clock, and Q counter outputs counts UP

Change an odd number of characteristics and the counter counts DOWN

Cascaded Counters

Cascaded Synchronous Counters with Ripple Carry Outputs

First stage RCO enables second stage for counting

RCO assertedsoon after stageenters state 1111

also a functionof the T Enable

Downstream stageslag in their 1111 to0000 transitions

Affects Count periodand decoding logic

ABCD

QAQBQCQD

ETEP

LD

CLR

RCO

ABCD

QAQBQCQD

ETEP

LD

CLR

RCO

Clock

Load

D

C

B

A

100

Other Counter SequencesThe Power of Synchronous Clear and Load

Starting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, 0110, ...

Use RCO signal to trigger Load of a new state

Since 74163 Load is synchronous, state changes only on the next rising clock edge

0110is the state

to be loaded

D C B A

L O A D

C L R

C L K

R C O

P T

Q A

Q B

Q C

Q D1

6 3

Load

D C B A

0 1++

Other Counter Sequences

Offset Counters Continued

Ending Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

Decode state todetermine when to

reset to 0000

Clear signal takes effect on the rising count edge

Replace '163 with '161, Counter with Async ClearClear takes effect immediately!

D C B A

C L R

L O A D

C L KP T

1 6 3

R C O

Q Q Q Q D C B A

CLR

D C B A

1 0

registers and counters

Documents

register fileeach register

parallel load register

clock input

clock gatingload

clock cycle

clock transition

bwhen clock

d ffsshared clock