Slide 1A register includes a set of flip-flops.
Since each flip-flop is capable of storing one bit of information, an n-bit register, including n flip-flops, is capable of storing n bits of binary information.
A register consists of a set of flip-flops together with gates that implement their state transitions.
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Counters
A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses.
The gates in the counter are connected in such a way as to produce the prescribed sequence of binary states.
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Counters
A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter.
The input pulses may be clock pulses or may originate from some other source, and they may occur at fixed internals of time or at random intervals.
The sequence of states may follow the binary number sequence or any other of states.
A counter that follows the binary number sequence is called binary counter.
A n-bit binary counter consists of n flip-flops and can count in binary from 0 through 2n-1.
Counters are available in two categories.
Ripple Counters
Synchronous Counters.
Ripple Counters
In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-flops.
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Synchronous Counters
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The advantage of ripple counters is their simple hardware.
But they are asynchronous circuits and , with added logic, can be unreliable and delay dependent.
This is particularly true for logic that provides feedback paths from counter outputs to counter inputs.
Due to the length of time required for the ripple to occur, large ripple counters are slow circuits.
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clock , // Clock input of the design
reset , // active high, synchronous Reset input enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
output [3:0] counter_out ;
//-Input ports Data Type-// By rule all the input ports should be wires
wire clock , reset , enable ;
//-------------Output Ports Data
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;
//------------Code Starts Here----------
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset == 1'b1) begin
else if (enable == 1'b1) begin
counter_out <= counter_out + 1;
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Frequency Division
Another application of a flip-flop is dividing (reducing) the frequency of a periodic wave form.
When a pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle (J=K=1), the Q output is a square wave with one–half the frequency of the clock input.
Thus, a single flip-flop can be applied as a dived-by-2 device.
The flip-flop changes state on each triggering clock edge (positive edge-triggered in this case).
This results in an output that changes at half the frequency of the clock waveform.
Further division of a clock frequency can be achieved by using the output of one flip-flop as the clock input to a second flip-flop.
The frequency of the QA output is divided by 2 by flip-flop B.
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The flip-flops are negative edge-triggered J-Ks. Both flip-flops are initially RESET.
Flip-Flop A toggles on the negative-going transition of each clock pulse.
The Q output of flip-flop A clock flip-flop B, so each time QA makes a HIGH-to-LOW transition, flip-flop B toggles.
Observe the sequence of QA and QB in the figure on the next slide.
Prior to clock pulse 1, QA = 0 and QB = 1; and after clock pulse 3, QA=1 and QB=1.
If we take QA as the least significant bit, a 2-bit binary sequence is produced as the flip-flips are clocked.
This binary sequence repeats every four clock pulses.
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Parallel Data Storage
A common requirement in digital systems is to store several bits of data form parallel lines simultaneously in a group of flip-flops.
This is done by using four flip-flops.
Each of four parallel data lines is connected to the D input of a flip-flop.
The clock inputs of the flip-flops are connected together, so that each flip-flop is triggered by the same clock pulse.
In this example +ve edge-triggered flip-flop are used, so the data on the D inputs are stored simultaneously by the flip-flops on the +ve edge of the clock.
Also the asynchronous reset (R ) inputs are connected to a common line, which initially resets all the flip-flops.
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